xref: /illumos-gate/usr/src/uts/sun4u/io/px/px_regs.h (revision a616a11e)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 
27 #ifndef _SYS_PX_REGS_H
28 #define	_SYS_PX_REGS_H
29 
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /* Register tools history */
36 #pragma ident	"@(#)hdgen	1.3	03/11/10"
37 #pragma	ident	"@(#)firedefiner.pl	1.7	03/11/19"
38 
39 /* jcs.csr  JCS module defines */
40 
41 #define	JCS_CSR_BASE	0x000000
42 #define	JBUS_DEVICE_ID	0x0
43 #define	JBUS_DEVICE_ID_COOKIE	56
44 #define	JBUS_DEVICE_ID_COOKIE_MASK	0xff
45 #define	JBUS_DEVICE_ID_JVPORT	27
46 #define	JBUS_DEVICE_ID_JVPORT_MASK	0x7f
47 #define	JBUS_DEVICE_ID_JPID_4	  21
48 #define	JBUS_DEVICE_ID_JPID_3_0	17
49 #define	JBUS_DEVICE_ID_JPID_3_0_MASK	0xf
50 #define	JBUS_DEVICE_ID_M_S	  16
51 #define	JBUS_DEVICE_ID_MID	10
52 #define	JBUS_DEVICE_ID_MID_MASK	0x3f
53 #define	JBUS_DEVICE_ID_MT	4
54 #define	JBUS_DEVICE_ID_MT_MASK	0x3f
55 #define	JBUS_DEVICE_ID_MR	0
56 #define	JBUS_DEVICE_ID_MR_MASK	0xf
57 #define	EBUS_OFFSET_BASE	0x400020
58 #define	EBUS_OFFSET_BASE_V	  63
59 #define	EBUS_OFFSET_BASE_BASE	24
60 #define	EBUS_OFFSET_BASE_BASE_MASK	0xfff
61 #define	EBUS_OFFSET_MASK	0x400028
62 #define	EBUS_OFFSET_MASK_MASK_HI	36
63 #define	EBUS_OFFSET_MASK_MASK_HI_MASK	0x7f
64 #define	EBUS_OFFSET_MASK_MASK	24
65 #define	EBUS_OFFSET_MASK_MASK_MASK	0xfff
66 #define	PCIE_A_MEM32_OFFSET_BASE	0x400040
67 #define	PCIE_A_MEM32_OFFSET_BASE_V	  63
68 #define	PCIE_A_MEM32_OFFSET_BASE_BASE	24
69 #define	PCIE_A_MEM32_OFFSET_BASE_BASE_MASK	0xfff
70 #define	PCIE_A_MEM32_OFFSET_MASK	0x400048
71 #define	PCIE_A_MEM32_OFFSET_MASK_MASK_HI	36
72 #define	PCIE_A_MEM32_OFFSET_MASK_MASK_HI_MASK	0x7f
73 #define	PCIE_A_MEM32_OFFSET_MASK_MASK	24
74 #define	PCIE_A_MEM32_OFFSET_MASK_MASK_MASK	0xfff
75 #define	PCIE_A_CFG_IO_OFFSET_BASE	0x400050
76 #define	PCIE_A_CFG_IO_OFFSET_BASE_V	  63
77 #define	PCIE_A_CFG_IO_OFFSET_BASE_BASE	24
78 #define	PCIE_A_CFG_IO_OFFSET_BASE_BASE_MASK	0xfff
79 #define	PCIE_A_CFG_IO_OFFSET_MASK	0x400058
80 #define	PCIE_A_CFG_IO_OFFSET_MASK_MASK_HI	36
81 #define	PCIE_A_CFG_IO_OFFSET_MASK_MASK_HI_MASK	0x7f
82 #define	PCIE_A_CFG_IO_OFFSET_MASK_MASK	24
83 #define	PCIE_A_CFG_IO_OFFSET_MASK_MASK_MASK	0xfff
84 #define	PCIE_B_MEM32_OFFSET_BASE	0x400060
85 #define	PCIE_B_MEM32_OFFSET_BASE_V	  63
86 #define	PCIE_B_MEM32_OFFSET_BASE_BASE	24
87 #define	PCIE_B_MEM32_OFFSET_BASE_BASE_MASK	0xfff
88 #define	PCIE_B_MEM32_OFFSET_MASK	0x400068
89 #define	PCIE_B_MEM32_OFFSET_MASK_MASK_HI	36
90 #define	PCIE_B_MEM32_OFFSET_MASK_MASK_HI_MASK	0x7f
91 #define	PCIE_B_MEM32_OFFSET_MASK_MASK	24
92 #define	PCIE_B_MEM32_OFFSET_MASK_MASK_MASK	0xfff
93 #define	PCIE_B_CFG_IO_OFFSET_BASE	0x400070
94 #define	PCIE_B_CFG_IO_OFFSET_BASE_V	  63
95 #define	PCIE_B_CFG_IO_OFFSET_BASE_BASE	24
96 #define	PCIE_B_CFG_IO_OFFSET_BASE_BASE_MASK	0xfff
97 #define	PCIE_B_CFG_IO_OFFSET_MASK	0x400078
98 #define	PCIE_B_CFG_IO_OFFSET_MASK_MASK_HI	36
99 #define	PCIE_B_CFG_IO_OFFSET_MASK_MASK_HI_MASK	0x7f
100 #define	PCIE_B_CFG_IO_OFFSET_MASK_MASK	24
101 #define	PCIE_B_CFG_IO_OFFSET_MASK_MASK_MASK	0xfff
102 #define	PCIE_A_MEM64_OFFSET_BASE	0x400080
103 #define	PCIE_A_MEM64_OFFSET_BASE_V	  63
104 #define	PCIE_A_MEM64_OFFSET_BASE_BASE	24
105 #define	PCIE_A_MEM64_OFFSET_BASE_BASE_MASK	0xfff
106 #define	PCIE_A_MEM64_OFFSET_MASK	0x400088
107 #define	PCIE_A_MEM64_OFFSET_MASK_MASK_HI	36
108 #define	PCIE_A_MEM64_OFFSET_MASK_MASK_HI_MASK	0x7f
109 #define	PCIE_A_MEM64_OFFSET_MASK_MASK	24
110 #define	PCIE_A_MEM64_OFFSET_MASK_MASK_MASK	0xfff
111 #define	PCIE_B_MEM64_OFFSET_BASE	0x400090
112 #define	PCIE_B_MEM64_OFFSET_BASE_V	  63
113 #define	PCIE_B_MEM64_OFFSET_BASE_BASE	24
114 #define	PCIE_B_MEM64_OFFSET_BASE_BASE_MASK	0xfff
115 #define	PCIE_B_MEM64_OFFSET_MASK	0x400098
116 #define	PCIE_B_MEM64_OFFSET_MASK_MASK_HI	36
117 #define	PCIE_B_MEM64_OFFSET_MASK_MASK_HI_MASK	0x7f
118 #define	PCIE_B_MEM64_OFFSET_MASK_MASK	24
119 #define	PCIE_B_MEM64_OFFSET_MASK_MASK_MASK	0xfff
120 #define	FIRE_CONTROL_STATUS	0x410000
121 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_LOAD_4	  63
122 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_LOAD_3	  62
123 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_LOAD_2	  61
124 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_LOAD_1	  60
125 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_LOAD_0	  59
126 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL	54
127 #define	FIRE_CONTROL_STATUS_SPARE_CONTROL_MASK	0x1f
128 #define	FIRE_CONTROL_STATUS_SPARE_STATUS	49
129 #define	FIRE_CONTROL_STATUS_SPARE_STATUS_MASK	0x1f
130 #define	FIRE_CONTROL_STATUS_PAR_DELAY	  44
131 #define	FIRE_CONTROL_STATUS_PAR_EN	  43
132 #define	FIRE_CONTROL_STATUS_JPACK_DELAY	36
133 #define	FIRE_CONTROL_STATUS_JPACK_DELAY_MASK	0x7f
134 #define	FIRE_CONTROL_STATUS_DTL_MODE	34
135 #define	FIRE_CONTROL_STATUS_DTL_MODE_MASK	0x3
136 #define	FIRE_CONTROL_STATUS_JTO	32
137 #define	FIRE_CONTROL_STATUS_JTO_MASK	0x3
138 #define	FIRE_CONTROL_STATUS_ARB_MODE	27
139 #define	FIRE_CONTROL_STATUS_ARB_MODE_MASK	0x3
140 #define	FIRE_CONTROL_STATUS_UE_PROP_MODE	  26
141 #define	FIRE_CONTROL_STATUS_JPID_4	  25
142 #define	FIRE_CONTROL_STATUS_JPID_3_0	21
143 #define	FIRE_CONTROL_STATUS_JPID_3_0_MASK	0xf
144 #define	FIRE_CONTROL_STATUS_AOK_THRESH	17
145 #define	FIRE_CONTROL_STATUS_AOK_THRESH_MASK	0xf
146 #define	FIRE_CONTROL_STATUS_DOK_THRESH	13
147 #define	FIRE_CONTROL_STATUS_DOK_THRESH_MASK	0xf
148 #define	FIRE_CONTROL_STATUS_NIAGARA_MODE	  12
149 #define	FIRE_CONTROL_STATUS_PDQ	10
150 #define	FIRE_CONTROL_STATUS_PDQ_MASK	0x3
151 #define	FIRE_CONTROL_STATUS_J_AD4_DIAG	  9
152 #define	FIRE_CONTROL_STATUS_LPDQ	0
153 #define	FIRE_CONTROL_STATUS_LPDQ_MASK	0x1ff
154 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL	0x410050
155 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_50	55
156 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_50_MASK	0x1f
157 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_25	50
158 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_25_MASK	0x1f
159 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_50	45
160 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_50_MASK	0x1f
161 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_25	40
162 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_25_MASK	0x1f
163 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_DTL_TST2_SCHEME	  39
164 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_50_O	32
165 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_50_O_MASK	0x7f
166 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_25_O	24
167 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EP_25_O_MASK	0x7f
168 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_50_O	16
169 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_50_O_MASK	0x7f
170 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_25_O	8
171 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_EN_25_O_MASK	0x7f
172 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_DTL_TST2_MODE	6
173 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_DTL_TST2_MODE_MASK	0x3
174 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_PLL_LOCK	  5
175 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_DTL_CHAR	  4
176 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_JITLMT	2
177 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_JITLMT_MASK	0x3
178 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_CNTLMT	0
179 #define	JBUS_PLL_CONTROL_AND_DTL_CONTROL_CNTLMT_MASK	0x3
180 #define	JBUS_ENERGY_STAR_CONTROL	0x410058
181 #define	JBUS_ENERGY_STAR_CONTROL_S1_32	  5
182 #define	JBUS_ENERGY_STAR_CONTROL_S1_2	  1
183 #define	JBUS_ENERGY_STAR_CONTROL_FULL	  0
184 #define	JBUS_CHANGE_INITIATION_CONTROL	0x410060
185 #define	JBUS_CHANGE_INITIATION_CONTROL_CINIT	3
186 #define	JBUS_CHANGE_INITIATION_CONTROL_CINIT_MASK	0x3
187 #define	JBUS_CHANGE_INITIATION_CONTROL_CDELAY	0
188 #define	JBUS_CHANGE_INITIATION_CONTROL_CDELAY_MASK	0x7
189 #define	RESET_GENERATION	0x417010
190 #define	RESET_GENERATION_PU_RST	  2
191 #define	RESET_GENERATION_XIR	  1
192 #define	RESET_GENERATION_PO_RST	  0
193 #define	RESET_SOURCE	0x417018
194 #define	RESET_SOURCE_FATAL	  6
195 #define	RESET_SOURCE_PB_XIR	  5
196 #define	RESET_SOURCE_PB_RST	  4
197 #define	RESET_SOURCE_PU	  3
198 #define	RESET_SOURCE_PU_RST	  2
199 #define	RESET_SOURCE_XIR	  1
200 #define	RESET_SOURCE_PO_RST	  0
201 #define	GPIO_PORT_0_PIN_0_DATA	0x460000
202 #define	GPIO_PORT_0_PIN_0_DATA_DATA	  0
203 #define	GPIO_PORT_0_PIN_1_DATA	0x460008
204 #define	GPIO_PORT_0_PIN_1_DATA_DATA	  0
205 #define	GPIO_PORT_0_PIN_2_DATA	0x460010
206 #define	GPIO_PORT_0_PIN_2_DATA_DATA	  0
207 #define	GPIO_PORT_0_PIN_3_DATA	0x460018
208 #define	GPIO_PORT_0_PIN_3_DATA_DATA	  0
209 #define	GPIO_PORT_0_DATA	0x460020
210 #define	GPIO_PORT_0_DATA_DATA_3	  3
211 #define	GPIO_PORT_0_DATA_DATA_2	  2
212 #define	GPIO_PORT_0_DATA_DATA_1	  1
213 #define	GPIO_PORT_0_DATA_DATA_0	  0
214 #define	GPIO_PORT_0_CONTROL	0x460028
215 #define	GPIO_PORT_0_CONTROL_DIR_3	  3
216 #define	GPIO_PORT_0_CONTROL_DIR_2	  2
217 #define	GPIO_PORT_0_CONTROL_DIR_1	  1
218 #define	GPIO_PORT_0_CONTROL_DIR_0	  0
219 #define	GPIO_PORT_1_PIN_0_DATA	0x462000
220 #define	GPIO_PORT_1_PIN_0_DATA_DATA	  0
221 #define	GPIO_PORT_1_PIN_1_DATA	0x462008
222 #define	GPIO_PORT_1_PIN_1_DATA_DATA	  0
223 #define	GPIO_PORT_1_PIN_2_DATA	0x462010
224 #define	GPIO_PORT_1_PIN_2_DATA_DATA	  0
225 #define	GPIO_PORT_1_PIN_3_DATA	0x462018
226 #define	GPIO_PORT_1_PIN_3_DATA_DATA	  0
227 #define	GPIO_PORT_1_DATA	0x462020
228 #define	GPIO_PORT_1_DATA_DATA_3	  3
229 #define	GPIO_PORT_1_DATA_DATA_2	  2
230 #define	GPIO_PORT_1_DATA_DATA_1	  1
231 #define	GPIO_PORT_1_DATA_DATA_0	  0
232 #define	GPIO_PORT_1_CONTROL	0x462028
233 #define	GPIO_PORT_1_CONTROL_DIR_3	  3
234 #define	GPIO_PORT_1_CONTROL_DIR_2	  2
235 #define	GPIO_PORT_1_CONTROL_DIR_1	  1
236 #define	GPIO_PORT_1_CONTROL_DIR_0	  0
237 #define	EBUS_EPROM_TIMING_CONTROL	0x464000
238 #define	EBUS_EPROM_TIMING_CONTROL_ENABLE	  61
239 #define	EBUS_EPROM_TIMING_CONTROL_READY_COUNT	40
240 #define	EBUS_EPROM_TIMING_CONTROL_READY_COUNT_MASK	0x1fffff
241 #define	EBUS_EPROM_TIMING_CONTROL_PROTOCOL_COUNT	32
242 #define	EBUS_EPROM_TIMING_CONTROL_PROTOCOL_COUNT_MASK	0xff
243 #define	EBUS_EPROM_TIMING_CONTROL_STROBE_COUNT	24
244 #define	EBUS_EPROM_TIMING_CONTROL_STROBE_COUNT_MASK	0xff
245 #define	EBUS_EPROM_TIMING_CONTROL_RECOVERY_COUNT	16
246 #define	EBUS_EPROM_TIMING_CONTROL_RECOVERY_COUNT_MASK	0xff
247 #define	EBUS_EPROM_TIMING_CONTROL_HOLD_COUNT	8
248 #define	EBUS_EPROM_TIMING_CONTROL_HOLD_COUNT_MASK	0xff
249 #define	EBUS_EPROM_TIMING_CONTROL_SETUP_COUNT	0
250 #define	EBUS_EPROM_TIMING_CONTROL_SETUP_COUNT_MASK	0xff
251 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL	0x464008
252 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_READY_COUNT	40
253 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_READY_COUNT_MASK	0x1fffff
254 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_PROTOCOL_COUNT	32
255 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_PROTOCOL_COUNT_MASK	0xff
256 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_STROBE_COUNT	24
257 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_STROBE_COUNT_MASK	0xff
258 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_RECOVERY_COUNT	16
259 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_RECOVERY_COUNT_MASK	0xff
260 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_HOLD_COUNT	8
261 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_HOLD_COUNT_MASK	0xff
262 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_SETUP_COUNT	0
263 #define	EBUS_CHIP_SELECT_1_TIMING_CONTROL_SETUP_COUNT_MASK	0xff
264 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL	0x464010
265 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_READY_COUNT	40
266 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_READY_COUNT_MASK	0x1fffff
267 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_PROTOCOL_COUNT	32
268 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_PROTOCOL_COUNT_MASK	0xff
269 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_STROBE_COUNT	24
270 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_STROBE_COUNT_MASK	0xff
271 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_RECOVERY_COUNT	16
272 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_RECOVERY_COUNT_MASK	0xff
273 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_HOLD_COUNT	8
274 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_HOLD_COUNT_MASK	0xff
275 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_SETUP_COUNT	0
276 #define	EBUS_CHIP_SELECT_2_TIMING_CONTROL_SETUP_COUNT_MASK	0xff
277 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL	0x464018
278 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_READY_COUNT	40
279 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_READY_COUNT_MASK	0x1fffff
280 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_PROTOCOL_COUNT	32
281 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_PROTOCOL_COUNT_MASK	0xff
282 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_STROBE_COUNT	24
283 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_STROBE_COUNT_MASK	0xff
284 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_RECOVERY_COUNT	16
285 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_RECOVERY_COUNT_MASK	0xff
286 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_HOLD_COUNT	8
287 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_HOLD_COUNT_MASK	0xff
288 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_SETUP_COUNT	0
289 #define	EBUS_CHIP_SELECT_3_TIMING_CONTROL_SETUP_COUNT_MASK	0xff
290 #define	I2C_0_INPUT_MONITOR	0x466000
291 #define	I2C_0_INPUT_MONITOR_SDC	  1
292 #define	I2C_0_INPUT_MONITOR_SDA	  0
293 #define	I2C_0_DATA_DRIVE	0x466008
294 #define	I2C_0_DATA_DRIVE_SDA	  0
295 #define	I2C_0_CLOCK_DRIVE	0x466010
296 #define	I2C_0_CLOCK_DRIVE_SCL	  0
297 #define	I2C_1_INPUT_MONITOR	0x468000
298 #define	I2C_1_INPUT_MONITOR_SDC	  1
299 #define	I2C_1_INPUT_MONITOR_SDA	  0
300 #define	I2C_1_DATA_DRIVE	0x468008
301 #define	I2C_1_DATA_DRIVE_SDA	  0
302 #define	I2C_1_CLOCK_DRIVE	0x468010
303 #define	I2C_1_CLOCK_DRIVE_SCL	  0
304 #define	PCIE_A_LEAF_CSR_RING_SLOW_ONLY_ACCESS	0x470000
305 #define	PCIE_A_LEAF_CSR_RING_SLOW_ONLY_ACCESS_SLOW_ONLY	  0
306 #define	PCIE_B_LEAF_CSR_RING_SLOW_ONLY_ACCESS	0x470008
307 #define	PCIE_B_LEAF_CSR_RING_SLOW_ONLY_ACCESS_SLOW_ONLY	  0
308 #define	JBUS_PARITY_CONTROL	0x470010
309 #define	JBUS_PARITY_CONTROL_P_EN	  63
310 #define	JBUS_PARITY_CONTROL_INVERT_PAR	2
311 #define	JBUS_PARITY_CONTROL_INVERT_PAR_MASK	0xf
312 #define	JBUS_PARITY_CONTROL_NEXT_DATA	  1
313 #define	JBUS_PARITY_CONTROL_NEXT_ADDR	  0
314 #define	JBUS_SCRATCH_1	0x470018
315 #define	JBUS_SCRATCH_1_DATA	0
316 #define	JBUS_SCRATCH_1_DATA_MASK	0xffffffffffffffff
317 #define	JBUS_SCRATCH_2	0x470020
318 #define	JBUS_SCRATCH_2_DATA	0
319 #define	JBUS_SCRATCH_2_DATA_MASK	0xffffffffffffffff
320 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR	0x470028
321 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_S_INT_EN	61
322 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_S_INT_EN_MASK	0x7
323 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_UNMAP_RD_S_INT_EN	  60
324 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_ACC_RD_S_INT_EN	  59
325 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_EBUS_TO_S_LOG_EN	  58
326 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PEA_S_INT_EN	  57
327 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PER_S_INT_EN	  56
328 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PEW_S_INT_EN	  55
329 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UE_ASYN_S_INT_EN	  54
330 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_CE_ASYN_S_INT_EN	  53
331 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTE_S_INT_EN	  52
332 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JBE_S_INT_EN	  51
333 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JUE_S_INT_EN	  50
334 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_IJP_S_INT_EN	  49
335 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ICISE_S_INT_EN	  48
336 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_CPE_S_INT_EN	  47
337 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_APE_S_INT_EN	  46
338 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_WR_DPE_S_INT_EN	  45
339 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_RD_DPE_S_INT_EN	  44
340 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_BMW_S_INT_EN	  43
341 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_BMR_S_INT_EN	  42
342 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_BJC_S_INT_EN	  41
343 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_UNMAP_S_INT_EN	  40
344 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_DPE_S_INT_EN	  39
345 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_CPE_S_INT_EN	  38
346 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_ACC_S_INT_EN	  37
347 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UNSOL_RD_S_INT_EN	  36
348 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UNSOL_INTR_S_INT_EN	  35
349 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEEW_S_INT_EN	  34
350 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEEI_S_INT_EN	  33
351 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEER_S_INT_EN	  32
352 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_P_INT_EN	29
353 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_SPARE_P_INT_EN_MASK	0x7
354 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_UNMAP_RD_P_INT_EN	  28
355 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_ACC_RD_P_INT_EN	  27
356 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_EBUS_TO_P_LOG_EN	  26
357 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PEA_P_INT_EN	  25
358 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PER_P_INT_EN	  24
359 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_MB_PEW_P_INT_EN	  23
360 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UE_ASYN_P_INT_EN	  22
361 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_CE_ASYN_P_INT_EN	  21
362 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTE_P_INT_EN	  20
363 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JBE_P_INT_EN	  19
364 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JUE_P_INT_EN	  18
365 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_IJP_P_INT_EN	  17
366 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ICISE_P_INT_EN	  16
367 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_CPE_P_INT_EN	  15
368 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_APE_P_INT_EN	  14
369 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_WR_DPE_P_INT_EN	  13
370 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_RD_DPE_P_INT_EN	  12
371 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_BMW_P_INT_EN	  11
372 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_BMR_P_INT_EN	  10
373 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_BJC_P_INT_EN	  9
374 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_UNMAP_P_INT_EN	  8
375 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_DPE_P_INT_EN	  7
376 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_PIO_CPE_P_INT_EN	  6
377 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_ILL_ACC_P_INT_EN	  5
378 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UNSOL_RD_P_INT_EN	  4
379 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_UNSOL_INTR_P_INT_EN	  3
380 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEEW_P_INT_EN	  2
381 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEEI_P_INT_EN	  1
382 #define	JBC_ERR_LG_ANLYZ_TRIG_ENB_FOR_J_ERR_JTCEER_P_INT_EN	  0
383 #define	JBUS_SCRATCH_PERSISTENT	0x470030
384 #define	JBUS_SCRATCH_PERSISTENT_DATA	0
385 #define	JBUS_SCRATCH_PERSISTENT_DATA_MASK	0xffffffffffffffff
386 #define	JBC_ERROR_LOG_ENABLE	0x471000
387 #define	JBC_ERROR_LOG_ENABLE_SPARE_LOG_EN	29
388 #define	JBC_ERROR_LOG_ENABLE_SPARE_LOG_EN_MASK	0x7
389 #define	JBC_ERROR_LOG_ENABLE_PIO_UNMAP_RD_LOG_EN	  28
390 #define	JBC_ERROR_LOG_ENABLE_ILL_ACC_RD_LOG_EN	  27
391 #define	JBC_ERROR_LOG_ENABLE_EBUS_TO_LOG_EN	  26
392 #define	JBC_ERROR_LOG_ENABLE_MB_PEA_LOG_EN	  25
393 #define	JBC_ERROR_LOG_ENABLE_MB_PER_LOG_EN	  24
394 #define	JBC_ERROR_LOG_ENABLE_MB_PEW_LOG_EN	  23
395 #define	JBC_ERROR_LOG_ENABLE_UE_ASYN_LOG_EN	  22
396 #define	JBC_ERROR_LOG_ENABLE_CE_ASYN_LOG_EN	  21
397 #define	JBC_ERROR_LOG_ENABLE_JTE_LOG_EN	  20
398 #define	JBC_ERROR_LOG_ENABLE_JBE_LOG_EN	  19
399 #define	JBC_ERROR_LOG_ENABLE_JUE_LOG_EN	  18
400 #define	JBC_ERROR_LOG_ENABLE_IJP_LOG_EN	  17
401 #define	JBC_ERROR_LOG_ENABLE_ICISE_LOG_EN	  16
402 #define	JBC_ERROR_LOG_ENABLE_CPE_LOG_EN	  15
403 #define	JBC_ERROR_LOG_ENABLE_APE_LOG_EN	  14
404 #define	JBC_ERROR_LOG_ENABLE_WR_DPE_LOG_EN	  13
405 #define	JBC_ERROR_LOG_ENABLE_RD_DPE_LOG_EN	  12
406 #define	JBC_ERROR_LOG_ENABLE_ILL_BMW_LOG_EN	  11
407 #define	JBC_ERROR_LOG_ENABLE_ILL_BMR_LOG_EN	  10
408 #define	JBC_ERROR_LOG_ENABLE_BJC_LOG_EN	  9
409 #define	JBC_ERROR_LOG_ENABLE_PIO_UNMAP_LOG_EN	  8
410 #define	JBC_ERROR_LOG_ENABLE_PIO_DPE_LOG_EN	  7
411 #define	JBC_ERROR_LOG_ENABLE_PIO_CPE_LOG_EN	  6
412 #define	JBC_ERROR_LOG_ENABLE_ILL_ACC_LOG_EN	  5
413 #define	JBC_ERROR_LOG_ENABLE_UNSOL_RD_LOG_EN	  4
414 #define	JBC_ERROR_LOG_ENABLE_UNSOL_INTR_LOG_EN	  3
415 #define	JBC_ERROR_LOG_ENABLE_JTCEEW_LOG_EN	  2
416 #define	JBC_ERROR_LOG_ENABLE_JTCEEI_LOG_EN	  1
417 #define	JBC_ERROR_LOG_ENABLE_JTCEER_LOG_EN	  0
418 #define	JBC_INTERRUPT_ENABLE	0x471008
419 #define	JBC_INTERRUPT_ENABLE_SPARE_S_INT_EN	61
420 #define	JBC_INTERRUPT_ENABLE_SPARE_S_INT_EN_MASK	0x7
421 #define	JBC_INTERRUPT_ENABLE_PIO_UNMAP_RD_S_INT_EN	  60
422 #define	JBC_INTERRUPT_ENABLE_ILL_ACC_RD_S_INT_EN	  59
423 #define	JBC_INTERRUPT_ENABLE_EBUS_TO_S_LOG_EN	  58
424 #define	JBC_INTERRUPT_ENABLE_MB_PEA_S_INT_EN	  57
425 #define	JBC_INTERRUPT_ENABLE_MB_PER_S_INT_EN	  56
426 #define	JBC_INTERRUPT_ENABLE_MB_PEW_S_INT_EN	  55
427 #define	JBC_INTERRUPT_ENABLE_UE_ASYN_S_INT_EN	  54
428 #define	JBC_INTERRUPT_ENABLE_CE_ASYN_S_INT_EN	  53
429 #define	JBC_INTERRUPT_ENABLE_JTE_S_INT_EN	  52
430 #define	JBC_INTERRUPT_ENABLE_JBE_S_INT_EN	  51
431 #define	JBC_INTERRUPT_ENABLE_JUE_S_INT_EN	  50
432 #define	JBC_INTERRUPT_ENABLE_IJP_S_INT_EN	  49
433 #define	JBC_INTERRUPT_ENABLE_ICISE_S_INT_EN	  48
434 #define	JBC_INTERRUPT_ENABLE_CPE_S_INT_EN	  47
435 #define	JBC_INTERRUPT_ENABLE_APE_S_INT_EN	  46
436 #define	JBC_INTERRUPT_ENABLE_WR_DPE_S_INT_EN	  45
437 #define	JBC_INTERRUPT_ENABLE_RD_DPE_S_INT_EN	  44
438 #define	JBC_INTERRUPT_ENABLE_ILL_BMW_S_INT_EN	  43
439 #define	JBC_INTERRUPT_ENABLE_ILL_BMR_S_INT_EN	  42
440 #define	JBC_INTERRUPT_ENABLE_BJC_S_INT_EN	  41
441 #define	JBC_INTERRUPT_ENABLE_PIO_UNMAP_S_INT_EN	  40
442 #define	JBC_INTERRUPT_ENABLE_PIO_DPE_S_INT_EN	  39
443 #define	JBC_INTERRUPT_ENABLE_PIO_CPE_S_INT_EN	  38
444 #define	JBC_INTERRUPT_ENABLE_ILL_ACC_S_INT_EN	  37
445 #define	JBC_INTERRUPT_ENABLE_UNSOL_RD_S_INT_EN	  36
446 #define	JBC_INTERRUPT_ENABLE_UNSOL_INTR_S_INT_EN	  35
447 #define	JBC_INTERRUPT_ENABLE_JTCEEW_S_INT_EN	  34
448 #define	JBC_INTERRUPT_ENABLE_JTCEEI_S_INT_EN	  33
449 #define	JBC_INTERRUPT_ENABLE_JTCEER_S_INT_EN	  32
450 #define	JBC_INTERRUPT_ENABLE_SPARE_P_INT_EN	29
451 #define	JBC_INTERRUPT_ENABLE_SPARE_P_INT_EN_MASK	0x7
452 #define	JBC_INTERRUPT_ENABLE_PIO_UNMAP_RD_P_INT_EN	  28
453 #define	JBC_INTERRUPT_ENABLE_ILL_ACC_RD_P_INT_EN	  27
454 #define	JBC_INTERRUPT_ENABLE_EBUS_TO_P_LOG_EN	  26
455 #define	JBC_INTERRUPT_ENABLE_MB_PEA_P_INT_EN	  25
456 #define	JBC_INTERRUPT_ENABLE_MB_PER_P_INT_EN	  24
457 #define	JBC_INTERRUPT_ENABLE_MB_PEW_P_INT_EN	  23
458 #define	JBC_INTERRUPT_ENABLE_UE_ASYN_P_INT_EN	  22
459 #define	JBC_INTERRUPT_ENABLE_CE_ASYN_P_INT_EN	  21
460 #define	JBC_INTERRUPT_ENABLE_JTE_P_INT_EN	  20
461 #define	JBC_INTERRUPT_ENABLE_JBE_P_INT_EN	  19
462 #define	JBC_INTERRUPT_ENABLE_JUE_P_INT_EN	  18
463 #define	JBC_INTERRUPT_ENABLE_IJP_P_INT_EN	  17
464 #define	JBC_INTERRUPT_ENABLE_ICISE_P_INT_EN	  16
465 #define	JBC_INTERRUPT_ENABLE_CPE_P_INT_EN	  15
466 #define	JBC_INTERRUPT_ENABLE_APE_P_INT_EN	  14
467 #define	JBC_INTERRUPT_ENABLE_WR_DPE_P_INT_EN	  13
468 #define	JBC_INTERRUPT_ENABLE_RD_DPE_P_INT_EN	  12
469 #define	JBC_INTERRUPT_ENABLE_ILL_BMW_P_INT_EN	  11
470 #define	JBC_INTERRUPT_ENABLE_ILL_BMR_P_INT_EN	  10
471 #define	JBC_INTERRUPT_ENABLE_BJC_P_INT_EN	  9
472 #define	JBC_INTERRUPT_ENABLE_PIO_UNMAP_P_INT_EN	  8
473 #define	JBC_INTERRUPT_ENABLE_PIO_DPE_P_INT_EN	  7
474 #define	JBC_INTERRUPT_ENABLE_PIO_CPE_P_INT_EN	  6
475 #define	JBC_INTERRUPT_ENABLE_ILL_ACC_P_INT_EN	  5
476 #define	JBC_INTERRUPT_ENABLE_UNSOL_RD_P_INT_EN	  4
477 #define	JBC_INTERRUPT_ENABLE_UNSOL_INTR_P_INT_EN	  3
478 #define	JBC_INTERRUPT_ENABLE_JTCEEW_P_INT_EN	  2
479 #define	JBC_INTERRUPT_ENABLE_JTCEEI_P_INT_EN	  1
480 #define	JBC_INTERRUPT_ENABLE_JTCEER_P_INT_EN	  0
481 #define	JBC_INTERRUPT_STATUS	0x471010
482 #define	JBC_INTERRUPT_STATUS_SPARE_S	61
483 #define	JBC_INTERRUPT_STATUS_SPARE_S_MASK	0x7
484 #define	JBC_INTERRUPT_STATUS_PIO_UNMAP_RD_S	  60
485 #define	JBC_INTERRUPT_STATUS_ILL_ACC_RD_S	  59
486 #define	JBC_INTERRUPT_STATUS_EBUS_TO_S	  58
487 #define	JBC_INTERRUPT_STATUS_MB_PEA_S	  57
488 #define	JBC_INTERRUPT_STATUS_MB_PER_S	  56
489 #define	JBC_INTERRUPT_STATUS_MB_PEW_S	  55
490 #define	JBC_INTERRUPT_STATUS_UE_ASYN_S	  54
491 #define	JBC_INTERRUPT_STATUS_CE_ASYN_S	  53
492 #define	JBC_INTERRUPT_STATUS_JTE_S	  52
493 #define	JBC_INTERRUPT_STATUS_JBE_S	  51
494 #define	JBC_INTERRUPT_STATUS_JUE_S	  50
495 #define	JBC_INTERRUPT_STATUS_IJP_S	  49
496 #define	JBC_INTERRUPT_STATUS_ICISE_S	  48
497 #define	JBC_INTERRUPT_STATUS_CPE_S	  47
498 #define	JBC_INTERRUPT_STATUS_APE_S	  46
499 #define	JBC_INTERRUPT_STATUS_WR_DPE_S	  45
500 #define	JBC_INTERRUPT_STATUS_RD_DPE_S	  44
501 #define	JBC_INTERRUPT_STATUS_ILL_BMW_S	  43
502 #define	JBC_INTERRUPT_STATUS_ILL_BMR_S	  42
503 #define	JBC_INTERRUPT_STATUS_BJC_S	  41
504 #define	JBC_INTERRUPT_STATUS_PIO_UNMAP_S	  40
505 #define	JBC_INTERRUPT_STATUS_PIO_DPE_S	  39
506 #define	JBC_INTERRUPT_STATUS_PIO_CPE_S	  38
507 #define	JBC_INTERRUPT_STATUS_ILL_ACC_S	  37
508 #define	JBC_INTERRUPT_STATUS_UNSOL_RD_S	  36
509 #define	JBC_INTERRUPT_STATUS_UNSOL_INTR_S	  35
510 #define	JBC_INTERRUPT_STATUS_JTCEEW_S	  34
511 #define	JBC_INTERRUPT_STATUS_JTCEEI_S	  33
512 #define	JBC_INTERRUPT_STATUS_JTCEER_S	  32
513 #define	JBC_INTERRUPT_STATUS_SPARE_P	29
514 #define	JBC_INTERRUPT_STATUS_SPARE_P_MASK	0x7
515 #define	JBC_INTERRUPT_STATUS_PIO_UNMAP_RD_P	  28
516 #define	JBC_INTERRUPT_STATUS_ILL_ACC_RD_P	  27
517 #define	JBC_INTERRUPT_STATUS_EBUS_TO_P	  26
518 #define	JBC_INTERRUPT_STATUS_MB_PEA_P	  25
519 #define	JBC_INTERRUPT_STATUS_MB_PER_P	  24
520 #define	JBC_INTERRUPT_STATUS_MB_PEW_P	  23
521 #define	JBC_INTERRUPT_STATUS_UE_ASYN_P	  22
522 #define	JBC_INTERRUPT_STATUS_CE_ASYN_P	  21
523 #define	JBC_INTERRUPT_STATUS_JTE_P	  20
524 #define	JBC_INTERRUPT_STATUS_JBE_P	  19
525 #define	JBC_INTERRUPT_STATUS_JUE_P	  18
526 #define	JBC_INTERRUPT_STATUS_IJP_P	  17
527 #define	JBC_INTERRUPT_STATUS_ICISE_P	  16
528 #define	JBC_INTERRUPT_STATUS_CPE_P	  15
529 #define	JBC_INTERRUPT_STATUS_APE_P	  14
530 #define	JBC_INTERRUPT_STATUS_WR_DPE_P	  13
531 #define	JBC_INTERRUPT_STATUS_RD_DPE_P	  12
532 #define	JBC_INTERRUPT_STATUS_ILL_BMW_P	  11
533 #define	JBC_INTERRUPT_STATUS_ILL_BMR_P	  10
534 #define	JBC_INTERRUPT_STATUS_BJC_P	  9
535 #define	JBC_INTERRUPT_STATUS_PIO_UNMAP_P	  8
536 #define	JBC_INTERRUPT_STATUS_PIO_DPE_P	  7
537 #define	JBC_INTERRUPT_STATUS_PIO_CPE_P	  6
538 #define	JBC_INTERRUPT_STATUS_ILL_ACC_P	  5
539 #define	JBC_INTERRUPT_STATUS_UNSOL_RD_P	  4
540 #define	JBC_INTERRUPT_STATUS_UNSOL_INTR_P	  3
541 #define	JBC_INTERRUPT_STATUS_JTCEEW_P	  2
542 #define	JBC_INTERRUPT_STATUS_JTCEEI_P	  1
543 #define	JBC_INTERRUPT_STATUS_JTCEER_P	  0
544 #define	JBC_ERROR_STATUS_CLEAR	0x471018
545 #define	JBC_ERROR_STATUS_CLEAR_SPARE_S	61
546 #define	JBC_ERROR_STATUS_CLEAR_SPARE_S_MASK	0x7
547 #define	JBC_ERROR_STATUS_CLEAR_PIO_UNMAP_RD_S	  60
548 #define	JBC_ERROR_STATUS_CLEAR_ILL_ACC_RD_S	  59
549 #define	JBC_ERROR_STATUS_CLEAR_EBUS_TO_S	  58
550 #define	JBC_ERROR_STATUS_CLEAR_MB_PEA_S	  57
551 #define	JBC_ERROR_STATUS_CLEAR_MB_PER_S	  56
552 #define	JBC_ERROR_STATUS_CLEAR_MB_PEW_S	  55
553 #define	JBC_ERROR_STATUS_CLEAR_UE_ASYN_S	  54
554 #define	JBC_ERROR_STATUS_CLEAR_CE_ASYN_S	  53
555 #define	JBC_ERROR_STATUS_CLEAR_JTE_S	  52
556 #define	JBC_ERROR_STATUS_CLEAR_JBE_S	  51
557 #define	JBC_ERROR_STATUS_CLEAR_JUE_S	  50
558 #define	JBC_ERROR_STATUS_CLEAR_IJP_S	  49
559 #define	JBC_ERROR_STATUS_CLEAR_ICISE_S	  48
560 #define	JBC_ERROR_STATUS_CLEAR_CPE_S	  47
561 #define	JBC_ERROR_STATUS_CLEAR_APE_S	  46
562 #define	JBC_ERROR_STATUS_CLEAR_WR_DPE_S	  45
563 #define	JBC_ERROR_STATUS_CLEAR_RD_DPE_S	  44
564 #define	JBC_ERROR_STATUS_CLEAR_ILL_BMW_S	  43
565 #define	JBC_ERROR_STATUS_CLEAR_ILL_BMR_S	  42
566 #define	JBC_ERROR_STATUS_CLEAR_BJC_S	  41
567 #define	JBC_ERROR_STATUS_CLEAR_PIO_UNMAP_S	  40
568 #define	JBC_ERROR_STATUS_CLEAR_PIO_DPE_S	  39
569 #define	JBC_ERROR_STATUS_CLEAR_PIO_CPE_S	  38
570 #define	JBC_ERROR_STATUS_CLEAR_ILL_ACC_S	  37
571 #define	JBC_ERROR_STATUS_CLEAR_UNSOL_RD_S	  36
572 #define	JBC_ERROR_STATUS_CLEAR_UNSOL_INTR_S	  35
573 #define	JBC_ERROR_STATUS_CLEAR_JTCEEW_S	  34
574 #define	JBC_ERROR_STATUS_CLEAR_JTCEEI_S	  33
575 #define	JBC_ERROR_STATUS_CLEAR_JTCEER_S	  32
576 #define	JBC_ERROR_STATUS_CLEAR_SPARE_P	29
577 #define	JBC_ERROR_STATUS_CLEAR_SPARE_P_MASK	0x7
578 #define	JBC_ERROR_STATUS_CLEAR_PIO_UNMAP_RD_P	  28
579 #define	JBC_ERROR_STATUS_CLEAR_ILL_ACC_RD_P	  27
580 #define	JBC_ERROR_STATUS_CLEAR_EBUS_TO_P	  26
581 #define	JBC_ERROR_STATUS_CLEAR_MB_PEA_P	  25
582 #define	JBC_ERROR_STATUS_CLEAR_MB_PER_P	  24
583 #define	JBC_ERROR_STATUS_CLEAR_MB_PEW_P	  23
584 #define	JBC_ERROR_STATUS_CLEAR_UE_ASYN_P	  22
585 #define	JBC_ERROR_STATUS_CLEAR_CE_ASYN_P	  21
586 #define	JBC_ERROR_STATUS_CLEAR_JTE_P	  20
587 #define	JBC_ERROR_STATUS_CLEAR_JBE_P	  19
588 #define	JBC_ERROR_STATUS_CLEAR_JUE_P	  18
589 #define	JBC_ERROR_STATUS_CLEAR_IJP_P	  17
590 #define	JBC_ERROR_STATUS_CLEAR_ICISE_P	  16
591 #define	JBC_ERROR_STATUS_CLEAR_CPE_P	  15
592 #define	JBC_ERROR_STATUS_CLEAR_APE_P	  14
593 #define	JBC_ERROR_STATUS_CLEAR_WR_DPE_P	  13
594 #define	JBC_ERROR_STATUS_CLEAR_RD_DPE_P	  12
595 #define	JBC_ERROR_STATUS_CLEAR_ILL_BMW_P	  11
596 #define	JBC_ERROR_STATUS_CLEAR_ILL_BMR_P	  10
597 #define	JBC_ERROR_STATUS_CLEAR_BJC_P	  9
598 #define	JBC_ERROR_STATUS_CLEAR_PIO_UNMAP_P	  8
599 #define	JBC_ERROR_STATUS_CLEAR_PIO_DPE_P	  7
600 #define	JBC_ERROR_STATUS_CLEAR_PIO_CPE_P	  6
601 #define	JBC_ERROR_STATUS_CLEAR_ILL_ACC_P	  5
602 #define	JBC_ERROR_STATUS_CLEAR_UNSOL_RD_P	  4
603 #define	JBC_ERROR_STATUS_CLEAR_UNSOL_INTR_P	  3
604 #define	JBC_ERROR_STATUS_CLEAR_JTCEEW_P	  2
605 #define	JBC_ERROR_STATUS_CLEAR_JTCEEI_P	  1
606 #define	JBC_ERROR_STATUS_CLEAR_JTCEER_P	  0
607 #define	JBC_ERROR_STATUS_SET	0x471020
608 #define	JBC_ERROR_STATUS_SET_SPARE_S	61
609 #define	JBC_ERROR_STATUS_SET_SPARE_S_MASK	0xfc
610 #define	JBC_ERROR_STATUS_SET_PIO_UNMAP_RD_S	  60
611 #define	JBC_ERROR_STATUS_SET_ILL_ACC_RD_S	  59
612 #define	JBC_ERROR_STATUS_SET_EBUS_TO_S	  58
613 #define	JBC_ERROR_STATUS_SET_MB_PEA_S	  57
614 #define	JBC_ERROR_STATUS_SET_MB_PER_S	  56
615 #define	JBC_ERROR_STATUS_SET_MB_PEW_S	  55
616 #define	JBC_ERROR_STATUS_SET_UE_ASYN_S	  54
617 #define	JBC_ERROR_STATUS_SET_CE_ASYN_S	  53
618 #define	JBC_ERROR_STATUS_SET_JTE_S	  52
619 #define	JBC_ERROR_STATUS_SET_JBE_S	  51
620 #define	JBC_ERROR_STATUS_SET_JUE_S	  50
621 #define	JBC_ERROR_STATUS_SET_IJP_S	  49
622 #define	JBC_ERROR_STATUS_SET_ICISE_S	  48
623 #define	JBC_ERROR_STATUS_SET_CPE_S	  47
624 #define	JBC_ERROR_STATUS_SET_APE_S	  46
625 #define	JBC_ERROR_STATUS_SET_WR_DPE_S	  45
626 #define	JBC_ERROR_STATUS_SET_RD_DPE_S	  44
627 #define	JBC_ERROR_STATUS_SET_ILL_BMW_S	  43
628 #define	JBC_ERROR_STATUS_SET_ILL_BMR_S	  42
629 #define	JBC_ERROR_STATUS_SET_BJC_S	  41
630 #define	JBC_ERROR_STATUS_SET_PIO_UNMAP_S	  40
631 #define	JBC_ERROR_STATUS_SET_PIO_DPE_S	  39
632 #define	JBC_ERROR_STATUS_SET_PIO_CPE_S	  38
633 #define	JBC_ERROR_STATUS_SET_ILL_ACC_S	  37
634 #define	JBC_ERROR_STATUS_SET_UNSOL_RD_S	  36
635 #define	JBC_ERROR_STATUS_SET_UNSOL_INTR_S	  35
636 #define	JBC_ERROR_STATUS_SET_JTCEEW_S	  34
637 #define	JBC_ERROR_STATUS_SET_JTCEEI_S	  33
638 #define	JBC_ERROR_STATUS_SET_JTCEER_S	  32
639 #define	JBC_ERROR_STATUS_SET_SPARE_P	29
640 #define	JBC_ERROR_STATUS_SET_SPARE_P_MASK	0xfc
641 #define	JBC_ERROR_STATUS_SET_PIO_UNMAP_RD_P	  28
642 #define	JBC_ERROR_STATUS_SET_ILL_ACC_RD_P	  27
643 #define	JBC_ERROR_STATUS_SET_EBUS_TO_P	  26
644 #define	JBC_ERROR_STATUS_SET_MB_PEA_P	  25
645 #define	JBC_ERROR_STATUS_SET_MB_PER_P	  24
646 #define	JBC_ERROR_STATUS_SET_MB_PEW_P	  23
647 #define	JBC_ERROR_STATUS_SET_UE_ASYN_P	  22
648 #define	JBC_ERROR_STATUS_SET_CE_ASYN_P	  21
649 #define	JBC_ERROR_STATUS_SET_JTE_P	  20
650 #define	JBC_ERROR_STATUS_SET_JBE_P	  19
651 #define	JBC_ERROR_STATUS_SET_JUE_P	  18
652 #define	JBC_ERROR_STATUS_SET_IJP_P	  17
653 #define	JBC_ERROR_STATUS_SET_ICISE_P	  16
654 #define	JBC_ERROR_STATUS_SET_CPE_P	  15
655 #define	JBC_ERROR_STATUS_SET_APE_P	  14
656 #define	JBC_ERROR_STATUS_SET_WR_DPE_P	  13
657 #define	JBC_ERROR_STATUS_SET_RD_DPE_P	  12
658 #define	JBC_ERROR_STATUS_SET_ILL_BMW_P	  11
659 #define	JBC_ERROR_STATUS_SET_ILL_BMR_P	  10
660 #define	JBC_ERROR_STATUS_SET_BJC_P	  9
661 #define	JBC_ERROR_STATUS_SET_PIO_UNMAP_P	  8
662 #define	JBC_ERROR_STATUS_SET_PIO_DPE_P	  7
663 #define	JBC_ERROR_STATUS_SET_PIO_CPE_P	  6
664 #define	JBC_ERROR_STATUS_SET_ILL_ACC_P	  5
665 #define	JBC_ERROR_STATUS_SET_UNSOL_RD_P	  4
666 #define	JBC_ERROR_STATUS_SET_UNSOL_INTR_P	  3
667 #define	JBC_ERROR_STATUS_SET_JTCEEW_P	  2
668 #define	JBC_ERROR_STATUS_SET_JTCEEI_P	  1
669 #define	JBC_ERROR_STATUS_SET_JTCEER_P	  0
670 #define	JBC_FATAL_RESET_ENABLE	0x471028
671 #define	JBC_FATAL_RESET_ENABLE_SPARE_P_INT_EN	26
672 #define	JBC_FATAL_RESET_ENABLE_SPARE_P_INT_EN_MASK	0x3
673 #define	JBC_FATAL_RESET_ENABLE_MB_PEA_P_INT_EN	  25
674 #define	JBC_FATAL_RESET_ENABLE_CPE_P_INT_EN	  15
675 #define	JBC_FATAL_RESET_ENABLE_APE_P_INT_EN	  14
676 #define	JBC_FATAL_RESET_ENABLE_PIO_CPE_INT_EN	  6
677 #define	JBC_FATAL_RESET_ENABLE_JTCEEW_P_INT_EN	  2
678 #define	JBC_FATAL_RESET_ENABLE_JTCEEI_P_INT_EN	  1
679 #define	JBC_FATAL_RESET_ENABLE_JTCEER_P_INT_EN	  0
680 #define	JBCINT_IN_TRANSACTION_ERROR_LOG	0x471030
681 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_Q_WORD	54
682 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_Q_WORD_MASK	0x3
683 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_TRANSID	48
684 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_TRANSID_MASK	0x3f
685 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS	0
686 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK	0x7ffffffffff
687 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2	0x471038
688 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_ARB_WIN	28
689 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_ARB_WIN_MASK	0xffffff
690 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_J_REQ	21
691 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_J_REQ_MASK	0x7f
692 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_J_PACK	0
693 #define	JBCINT_IN_TRANSACTION_ERROR_LOG_2_J_PACK_MASK	0x1fffff
694 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG	0x471040
695 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_TRANSID	48
696 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_TRANSID_MASK	0x3f
697 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_ADDRESS	0
698 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_ADDRESS_MASK	0x7ffffffffff
699 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2	0x471048
700 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_ARB_WIN	28
701 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_ARB_WIN_MASK	0xffffff
702 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_J_REQ	21
703 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_J_REQ_MASK	0x7f
704 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_J_PACK	0
705 #define	JBCINT_OUT_TRANSACTION_ERROR_LOG_2_J_PACK_MASK	0x1fffff
706 #define	FATAL_ERROR_LOG_1	0x471050
707 #define	FATAL_ERROR_LOG_1_DATA	0
708 #define	FATAL_ERROR_LOG_1_DATA_MASK	0xffffffffffffffff
709 #define	FATAL_ERROR_LOG_2	0x471058
710 #define	FATAL_ERROR_LOG_2_ARB_WIN	28
711 #define	FATAL_ERROR_LOG_2_ARB_WIN_MASK	0xffffff
712 #define	FATAL_ERROR_LOG_2_J_REQ	21
713 #define	FATAL_ERROR_LOG_2_J_REQ_MASK	0x7f
714 #define	FATAL_ERROR_LOG_2_J_PACK	0
715 #define	FATAL_ERROR_LOG_2_J_PACK_MASK	0x1fffff
716 #define	MERGE_TRANSACTION_ERROR_LOG	0x471060
717 #define	MERGE_TRANSACTION_ERROR_LOG_Q_WORD	54
718 #define	MERGE_TRANSACTION_ERROR_LOG_Q_WORD_MASK	0x3
719 #define	MERGE_TRANSACTION_ERROR_LOG_TRANSID	48
720 #define	MERGE_TRANSACTION_ERROR_LOG_TRANSID_MASK	0x3f
721 #define	MERGE_TRANSACTION_ERROR_LOG_JBC_TAG	43
722 #define	MERGE_TRANSACTION_ERROR_LOG_JBC_TAG_MASK	0x1f
723 #define	MERGE_TRANSACTION_ERROR_LOG_ADDRESS	0
724 #define	MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK	0x7ffffffffff
725 #define	DMCINT_ODCD_ERROR_LOG	0x471068
726 #define	DMCINT_ODCD_ERROR_LOG_TRANS_ID	52
727 #define	DMCINT_ODCD_ERROR_LOG_TRANS_ID_MASK	0x3
728 #define	DMCINT_ODCD_ERROR_LOG_AID	48
729 #define	DMCINT_ODCD_ERROR_LOG_AID_MASK	0xf
730 #define	DMCINT_ODCD_ERROR_LOG_TRANS_TYPE	43
731 #define	DMCINT_ODCD_ERROR_LOG_TRANS_TYPE_MASK	0x1f
732 #define	DMCINT_ODCD_ERROR_LOG_ADDRESS	0
733 #define	DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK	0x7ffffffffff
734 #define	DMCINT_IDC_ERROR_LOG	0x471070
735 #define	DMCINT_IDC_ERROR_LOG_DMC_CTAG	16
736 #define	DMCINT_IDC_ERROR_LOG_DMC_CTAG_MASK	0xfff
737 #define	DMCINT_IDC_ERROR_LOG_TRANSID	14
738 #define	DMCINT_IDC_ERROR_LOG_TRANSID_MASK	0x3
739 #define	DMCINT_IDC_ERROR_LOG_AGNTID	10
740 #define	DMCINT_IDC_ERROR_LOG_AGNTID_MASK	0xf
741 #define	DMCINT_IDC_ERROR_LOG_SRCID	5
742 #define	DMCINT_IDC_ERROR_LOG_SRCID_MASK	0x1f
743 #define	DMCINT_IDC_ERROR_LOG_TARGID	0
744 #define	DMCINT_IDC_ERROR_LOG_TARGID_MASK	0x1f
745 #define	CSR_ERROR_LOG	0x471078
746 #define	CSR_ERROR_LOG_WRITE	  42
747 #define	CSR_ERROR_LOG_BMASK	26
748 #define	CSR_ERROR_LOG_BMASK_MASK	0xffff
749 #define	CSR_ERROR_LOG_ADDRESS	0
750 #define	CSR_ERROR_LOG_ADDRESS_MASK	0x3ffffff
751 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE	0x471800
752 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE_JBC	  63
753 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE_CSR	  3
754 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE_MERGE	  2
755 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE_JBCINT	  1
756 #define	JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE_DMCINT	  0
757 #define	JBC_CORE_AND_BLOCK_ERROR_STATUS	0x471808
758 #define	JBC_CORE_AND_BLOCK_ERROR_STATUS_CSR	  3
759 #define	JBC_CORE_AND_BLOCK_ERROR_STATUS_MERGE	  2
760 #define	JBC_CORE_AND_BLOCK_ERROR_STATUS_JBCINT	  1
761 #define	JBC_CORE_AND_BLOCK_ERROR_STATUS_DMCINT	  0
762 #define	JBC_PERFORMANCE_COUNTER_SELECT	0x472000
763 #define	JBC_PERFORMANCE_COUNTER_SELECT_SEL1	8
764 #define	JBC_PERFORMANCE_COUNTER_SELECT_SEL1_MASK	0xff
765 #define	JBC_PERFORMANCE_COUNTER_SELECT_SEL0	0
766 #define	JBC_PERFORMANCE_COUNTER_SELECT_SEL0_MASK	0xff
767 #define	JBC_PERFORMANCE_COUNTER_ZERO	0x472008
768 #define	JBC_PERFORMANCE_COUNTER_ZERO_CNT	0
769 #define	JBC_PERFORMANCE_COUNTER_ZERO_CNT_MASK	0xffffffffffffffff
770 #define	JBC_PERFORMANCE_COUNTER_ONE	0x472010
771 #define	JBC_PERFORMANCE_COUNTER_ONE_CNT	0
772 #define	JBC_PERFORMANCE_COUNTER_ONE_CNT_MASK	0xffffffffffffffff
773 #define	FIRE_AND_JBC_DEBUG_SELECT_A	0x473000
774 #define	FIRE_AND_JBC_DEBUG_SELECT_A_CORE_SEL	10
775 #define	FIRE_AND_JBC_DEBUG_SELECT_A_CORE_SEL_MASK	0x3
776 #define	FIRE_AND_JBC_DEBUG_SELECT_A_BLOCK_SEL	6
777 #define	FIRE_AND_JBC_DEBUG_SELECT_A_BLOCK_SEL_MASK	0x7
778 #define	FIRE_AND_JBC_DEBUG_SELECT_A_SUB_SEL	3
779 #define	FIRE_AND_JBC_DEBUG_SELECT_A_SUB_SEL_MASK	0x7
780 #define	FIRE_AND_JBC_DEBUG_SELECT_A_SIGNAL_SEL	0
781 #define	FIRE_AND_JBC_DEBUG_SELECT_A_SIGNAL_SEL_MASK	0x7
782 #define	FIRE_AND_JBC_DEBUG_SELECT_B	0x473008
783 #define	FIRE_AND_JBC_DEBUG_SELECT_B_CORE_SEL	10
784 #define	FIRE_AND_JBC_DEBUG_SELECT_B_CORE_SEL_MASK	0x3
785 #define	FIRE_AND_JBC_DEBUG_SELECT_B_BLOCK_SEL	6
786 #define	FIRE_AND_JBC_DEBUG_SELECT_B_BLOCK_SEL_MASK	0x7
787 #define	FIRE_AND_JBC_DEBUG_SELECT_B_SUB_SEL	3
788 #define	FIRE_AND_JBC_DEBUG_SELECT_B_SUB_SEL_MASK	0x7
789 #define	FIRE_AND_JBC_DEBUG_SELECT_B_SIGNAL_SEL	0
790 #define	FIRE_AND_JBC_DEBUG_SELECT_B_SIGNAL_SEL_MASK	0x7
791 
792 /* iss.csr  ISS module defines */
793 
794 #define	ISS_CSR_BASE	0x600000
795 #define	INTERRUPT_MAPPING	0x1000
796 #define	INTERRUPT_MAPPING_ENTRIES	64
797 #define	INTERRUPT_MAPPING_ENTRIES_MDO_MODE	  63
798 #define	INTERRUPT_MAPPING_ENTRIES_V	  31
799 #define	INTERRUPT_MAPPING_ENTRIES_T_JPID	26
800 #define	INTERRUPT_MAPPING_ENTRIES_T_JPID_MASK	0x1f
801 #define	INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM	6
802 #define	INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK	0xf
803 
804 /* Reserved 0x1200 - 0x13f8 */
805 
806 #define	INTERRUPT_CLEAR	0x1400
807 #define	INTERRUPT_CLEAR_ENTRIES	64
808 #define	INTERRUPT_CLEAR_ENTRIES_INT_STATE	0
809 #define	INTERRUPT_CLEAR_ENTRIES_INT_STATE_MASK	0x3
810 
811 /* Reserved 0x1600 - 0x17f8 */
812 
813 
814 /* Reserved 0x1808 - 0x19f8 */
815 
816 #define	INTERRUPT_RETRY_TIMER	0x1a00
817 #define	INTERRUPT_RETRY_TIMER_LIMIT	0
818 #define	INTERRUPT_RETRY_TIMER_LIMIT_MASK	0x1ffffff
819 
820 /* Reserved 0x1a08 - 0x1a08 */
821 
822 #define	INTERRUPT_STATE_STATUS_1	0x1a10
823 #define	INTERRUPT_STATE_STATUS_1_STATE	0
824 #define	INTERRUPT_STATE_STATUS_1_STATE_MASK	0xffffffffffffffff
825 #define	INTERRUPT_STATE_STATUS_2	0x1a18
826 #define	INTERRUPT_STATE_STATUS_2_STATE	0
827 #define	INTERRUPT_STATE_STATUS_2_STATE_MASK	0xffffffffffffffff
828 
829 /* intx.csr  INTX module defines */
830 
831 #define	INTX_CSR_BASE	0x600000
832 #define	INTX_STATUS	0xb000
833 #define	INTX_STATUS_INT_A	  3
834 #define	INTX_STATUS_INT_B	  2
835 #define	INTX_STATUS_INT_C	  1
836 #define	INTX_STATUS_INT_D	  0
837 #define	INT_A_CLEAR	0xb008
838 #define	INT_A_CLEAR_CLR	  0
839 #define	INT_B_CLEAR	0xb010
840 #define	INT_B_CLEAR_CLR	  0
841 #define	INT_C_CLEAR	0xb018
842 #define	INT_C_CLEAR_CLR	  0
843 #define	INT_D_CLEAR	0xb020
844 #define	INT_D_CLEAR_CLR	  0
845 
846 /* eqs.csr  EQS module defines */
847 
848 #define	EQS_CSR_BASE	0x600000
849 #define	EVENT_QUEUE_BASE_ADDRESS	0x10000
850 #define	EVENT_QUEUE_BASE_ADDRESS_ADDRESS	19
851 #define	EVENT_QUEUE_BASE_ADDRESS_ADDRESS_MASK	0x1fffffffffff
852 
853 /* Reserved 0x10008 - 0x10ff8 */
854 
855 #define	EVENT_QUEUE_CONTROL_SET	0x11000
856 #define	EVENT_QUEUE_CONTROL_SET_ENTRIES	36
857 #define	EVENT_QUEUE_CONTROL_SET_ENTRIES_ENOVERR	  57
858 #define	EVENT_QUEUE_CONTROL_SET_ENTRIES_EN	  44
859 
860 /* Reserved 0x11120 - 0x111f8 */
861 
862 #define	EVENT_QUEUE_CONTROL_CLEAR	0x11200
863 #define	EVENT_QUEUE_CONTROL_CLEAR_ENTRIES	36
864 #define	EVENT_QUEUE_CONTROL_CLEAR_ENTRIES_COVERR	  57
865 #define	EVENT_QUEUE_CONTROL_CLEAR_ENTRIES_E2I	  47
866 #define	EVENT_QUEUE_CONTROL_CLEAR_ENTRIES_DIS	  44
867 
868 /* Reserved 0x11320 - 0x113f8 */
869 
870 #define	EVENT_QUEUE_STATE	0x11400
871 #define	EVENT_QUEUE_STATE_ENTRIES	36
872 #define	EVENT_QUEUE_STATE_ENTRIES_STATE	0
873 #define	EVENT_QUEUE_STATE_ENTRIES_STATE_MASK	0x7
874 
875 /* Reserved 0x11520 - 0x115f8 */
876 
877 #define	EVENT_QUEUE_TAIL	0x11600
878 #define	EVENT_QUEUE_TAIL_ENTRIES	36
879 #define	EVENT_QUEUE_TAIL_ENTRIES_OVERR	  57
880 #define	EVENT_QUEUE_TAIL_ENTRIES_TAIL	0
881 #define	EVENT_QUEUE_TAIL_ENTRIES_TAIL_MASK	0x7f
882 
883 /* Reserved 0x11720 - 0x117f8 */
884 
885 #define	EVENT_QUEUE_HEAD	0x11800
886 #define	EVENT_QUEUE_HEAD_ENTRIES	36
887 #define	EVENT_QUEUE_HEAD_ENTRIES_HEAD	0
888 #define	EVENT_QUEUE_HEAD_ENTRIES_HEAD_MASK	0x7f
889 
890 /* msi.csr  MSI module defines */
891 
892 #define	MSI_CSR_BASE	0x600000
893 #define	MSI_MAPPING	0x20000
894 #define	MSI_MAPPING_ENTRIES	256
895 #define	MSI_MAPPING_ENTRIES_V	  63
896 #define	MSI_MAPPING_ENTRIES_EQWR_N	  62
897 #define	MSI_MAPPING_ENTRIES_EQNUM	0
898 #define	MSI_MAPPING_ENTRIES_EQNUM_MASK	0x3f
899 
900 /* Reserved 0x20800 - 0x27ff8 */
901 
902 #define	MSI_CLEAR	0x28000
903 #define	MSI_CLEAR_ENTRIES	256
904 #define	MSI_CLEAR_ENTRIES_EQWR_N	  62
905 
906 /* Reserved 0x28800 - 0x2bff8 */
907 
908 #define	INTERRUPT_MONDO_DATA_0	0x2c000
909 #define	INTERRUPT_MONDO_DATA_0_DATA	6
910 #define	INTERRUPT_MONDO_DATA_0_DATA_MASK	0x3ffffffffffffff
911 #define	INTERRUPT_MONDO_DATA_1	0x2c008
912 #define	INTERRUPT_MONDO_DATA_1_DATA	0
913 #define	INTERRUPT_MONDO_DATA_1_DATA_MASK	0xffffffffffffffff
914 
915 /* mess.csr  MESS module defines */
916 
917 #define	MESS_CSR_BASE	0x600000
918 #define	ERR_COR_MAPPING	0x30000
919 #define	ERR_COR_MAPPING_V	  63
920 #define	ERR_COR_MAPPING_EQNUM	0
921 #define	ERR_COR_MAPPING_EQNUM_MASK	0x3f
922 #define	ERR_NONFATAL_MAPPING	0x30008
923 #define	ERR_NONFATAL_MAPPING_V	  63
924 #define	ERR_NONFATAL_MAPPING_EQNUM	0
925 #define	ERR_NONFATAL_MAPPING_EQNUM_MASK	0x3f
926 #define	ERR_FATAL_MAPPING	0x30010
927 #define	ERR_FATAL_MAPPING_V	  63
928 #define	ERR_FATAL_MAPPING_EQNUM	0
929 #define	ERR_FATAL_MAPPING_EQNUM_MASK	0x3f
930 #define	PM_PME_MAPPING	0x30018
931 #define	PM_PME_MAPPING_V	  63
932 #define	PM_PME_MAPPING_EQNUM	0
933 #define	PM_PME_MAPPING_EQNUM_MASK	0x3f
934 #define	PME_TO_ACK_MAPPING	0x30020
935 #define	PME_TO_ACK_MAPPING_V	  63
936 #define	PME_TO_ACK_MAPPING_EQNUM	0
937 #define	PME_TO_ACK_MAPPING_EQNUM_MASK	0x3f
938 
939 /* ics.csr  ICS module defines */
940 
941 #define	ICS_CSR_BASE	0x600000
942 #define	IMU_ERROR_LOG_ENABLE	0x31000
943 #define	IMU_ERROR_LOG_ENABLE_SPARE_LOG_EN	10
944 #define	IMU_ERROR_LOG_ENABLE_SPARE_LOG_EN_MASK	0x1f
945 #define	IMU_ERROR_LOG_ENABLE_EQ_OVER_LOG_EN	  9
946 #define	IMU_ERROR_LOG_ENABLE_EQ_NOT_EN_LOG_EN	  8
947 #define	IMU_ERROR_LOG_ENABLE_MSI_MAL_ERR_LOG_EN	  7
948 #define	IMU_ERROR_LOG_ENABLE_MSI_PAR_ERR_LOG_EN	  6
949 #define	IMU_ERROR_LOG_ENABLE_PMEACK_MES_NOT_EN_LOG_EN	  5
950 #define	IMU_ERROR_LOG_ENABLE_PMPME_MES_NOT_EN_LOG_EN	  4
951 #define	IMU_ERROR_LOG_ENABLE_FATAL_MES_NOT_EN_LOG_EN	  3
952 #define	IMU_ERROR_LOG_ENABLE_NONFATAL_MES_NOT_EN_LOG_EN	  2
953 #define	IMU_ERROR_LOG_ENABLE_COR_MES_NOT_EN_LOG_EN	  1
954 #define	IMU_ERROR_LOG_ENABLE_MSI_NOT_EN_LOG_EN	  0
955 #define	IMU_INTERRUPT_ENABLE	0x31008
956 #define	IMU_INTERRUPT_ENABLE_SPARE_S_INT_EN	42
957 #define	IMU_INTERRUPT_ENABLE_SPARE_S_INT_EN_MASK	0x1f
958 #define	IMU_INTERRUPT_ENABLE_EQ_OVER_S_INT_EN	  41
959 #define	IMU_INTERRUPT_ENABLE_EQ_NOT_EN_S_INT_EN	  40
960 #define	IMU_INTERRUPT_ENABLE_MSI_MAL_ERR_S_INT_EN	  39
961 #define	IMU_INTERRUPT_ENABLE_MSI_PAR_ERR_S_INT_EN	  38
962 #define	IMU_INTERRUPT_ENABLE_PMEACK_MES_NOT_EN_S_INT_EN	  37
963 #define	IMU_INTERRUPT_ENABLE_PMPME_MES_NOT_EN_S_INT_EN	  36
964 #define	IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_S_INT_EN	  35
965 #define	IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_S_INT_EN	  34
966 #define	IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_S_INT_EN	  33
967 #define	IMU_INTERRUPT_ENABLE_MSI_NOT_EN_S_INT_EN	  32
968 #define	IMU_INTERRUPT_ENABLE_SPARE_P_INT_EN	10
969 #define	IMU_INTERRUPT_ENABLE_SPARE_P_INT_EN_MASK	0x1f
970 #define	IMU_INTERRUPT_ENABLE_EQ_OVER_P_INT_EN	  9
971 #define	IMU_INTERRUPT_ENABLE_EQ_NOT_EN_P_INT_EN	  8
972 #define	IMU_INTERRUPT_ENABLE_MSI_MAL_ERR_P_INT_EN	  7
973 #define	IMU_INTERRUPT_ENABLE_MSI_PAR_ERR_P_INT_EN	  6
974 #define	IMU_INTERRUPT_ENABLE_PMEACK_MES_NOT_EN_P_INT_EN	  5
975 #define	IMU_INTERRUPT_ENABLE_PMPME_MES_NOT_EN_P_INT_EN	  4
976 #define	IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_P_INT_EN	  3
977 #define	IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_P_INT_EN	  2
978 #define	IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_P_INT_EN	  1
979 #define	IMU_INTERRUPT_ENABLE_MSI_NOT_EN_P_INT_EN	  0
980 #define	IMU_INTERRUPT_STATUS	0x31010
981 #define	IMU_INTERRUPT_STATUS_SPARE_S	42
982 #define	IMU_INTERRUPT_STATUS_SPARE_S_MASK	0x1f
983 #define	IMU_INTERRUPT_STATUS_EQ_OVER_S	  41
984 #define	IMU_INTERRUPT_STATUS_EQ_NOT_EN_S	  40
985 #define	IMU_INTERRUPT_STATUS_MSI_MAL_ERR_S	  39
986 #define	IMU_INTERRUPT_STATUS_MSI_PAR_ERR_S	  38
987 #define	IMU_INTERRUPT_STATUS_PMEACK_MES_NOT_EN_S	  37
988 #define	IMU_INTERRUPT_STATUS_PMPME_MES_NOT_EN_S	  36
989 #define	IMU_INTERRUPT_STATUS_FATAL_MES_NOT_EN_S	  35
990 #define	IMU_INTERRUPT_STATUS_NONFATAL_MES_NOT_EN_S	  34
991 #define	IMU_INTERRUPT_STATUS_COR_MES_NOT_EN_S	  33
992 #define	IMU_INTERRUPT_STATUS_MSI_NOT_EN_S	  32
993 #define	IMU_INTERRUPT_STATUS_SPARE_P	10
994 #define	IMU_INTERRUPT_STATUS_SPARE_P_MASK	0x1f
995 #define	IMU_INTERRUPT_STATUS_EQ_OVER_P	  9
996 #define	IMU_INTERRUPT_STATUS_EQ_NOT_EN_P	  8
997 #define	IMU_INTERRUPT_STATUS_MSI_MAL_ERR_P	  7
998 #define	IMU_INTERRUPT_STATUS_MSI_PAR_ERR_P	  6
999 #define	IMU_INTERRUPT_STATUS_PMEACK_MES_NOT_EN_P	  5
1000 #define	IMU_INTERRUPT_STATUS_PMPME_MES_NOT_EN_P	  4
1001 #define	IMU_INTERRUPT_STATUS_FATAL_MES_NOT_EN_P	  3
1002 #define	IMU_INTERRUPT_STATUS_NONFATAL_MES_NOT_EN_P	  2
1003 #define	IMU_INTERRUPT_STATUS_COR_MES_NOT_EN_P	  1
1004 #define	IMU_INTERRUPT_STATUS_MSI_NOT_EN_P	  0
1005 #define	IMU_ERROR_STATUS_CLEAR	0x31018
1006 #define	IMU_ERROR_STATUS_CLEAR_SPARE_S	42
1007 #define	IMU_ERROR_STATUS_CLEAR_SPARE_S_MASK	0x1f
1008 #define	IMU_ERROR_STATUS_CLEAR_EQ_OVER_S	  41
1009 #define	IMU_ERROR_STATUS_CLEAR_EQ_NOT_EN_S	  40
1010 #define	IMU_ERROR_STATUS_CLEAR_MSI_MAL_ERR_S	  39
1011 #define	IMU_ERROR_STATUS_CLEAR_MSI_PAR_ERR_S	  38
1012 #define	IMU_ERROR_STATUS_CLEAR_PMEACK_MES_NOT_EN_S	  37
1013 #define	IMU_ERROR_STATUS_CLEAR_PMPME_MES_NOT_EN_S	  36
1014 #define	IMU_ERROR_STATUS_CLEAR_FATAL_MES_NOT_EN_S	  35
1015 #define	IMU_ERROR_STATUS_CLEAR_NONFATAL_MES_NOT_EN_S	  34
1016 #define	IMU_ERROR_STATUS_CLEAR_COR_MES_NOT_EN_S	  33
1017 #define	IMU_ERROR_STATUS_CLEAR_MSI_NOT_EN_S	  32
1018 #define	IMU_ERROR_STATUS_CLEAR_SPARE_P	10
1019 #define	IMU_ERROR_STATUS_CLEAR_SPARE_P_MASK	0x1f
1020 #define	IMU_ERROR_STATUS_CLEAR_EQ_OVER_P	  9
1021 #define	IMU_ERROR_STATUS_CLEAR_EQ_NOT_EN_P	  8
1022 #define	IMU_ERROR_STATUS_CLEAR_MSI_MAL_ERR_P	  7
1023 #define	IMU_ERROR_STATUS_CLEAR_MSI_PAR_ERR_P	  6
1024 #define	IMU_ERROR_STATUS_CLEAR_PMEACK_MES_NOT_EN_P	  5
1025 #define	IMU_ERROR_STATUS_CLEAR_PMPME_MES_NOT_EN_P	  4
1026 #define	IMU_ERROR_STATUS_CLEAR_FATAL_MES_NOT_EN_P	  3
1027 #define	IMU_ERROR_STATUS_CLEAR_NONFATAL_MES_NOT_EN_P	  2
1028 #define	IMU_ERROR_STATUS_CLEAR_COR_MES_NOT_EN_P	  1
1029 #define	IMU_ERROR_STATUS_CLEAR_MSI_NOT_EN_P	  0
1030 #define	IMU_ERROR_STATUS_SET	0x31020
1031 #define	IMU_ERROR_STATUS_SET_SPARE_S	42
1032 #define	IMU_ERROR_STATUS_SET_SPARE_S_MASK	0xfa
1033 #define	IMU_ERROR_STATUS_SET_EQ_OVER_S	  41
1034 #define	IMU_ERROR_STATUS_SET_EQ_NOT_EN_S	  40
1035 #define	IMU_ERROR_STATUS_SET_MSI_MAL_ERR_S	  39
1036 #define	IMU_ERROR_STATUS_SET_MSI_PAR_ERR_S	  38
1037 #define	IMU_ERROR_STATUS_SET_PMEACK_MES_NOT_EN_S	  37
1038 #define	IMU_ERROR_STATUS_SET_PMPME_MES_NOT_EN_S	  36
1039 #define	IMU_ERROR_STATUS_SET_FATAL_MES_NOT_EN_S	  35
1040 #define	IMU_ERROR_STATUS_SET_NONFATAL_MES_NOT_EN_S	  34
1041 #define	IMU_ERROR_STATUS_SET_COR_MES_NOT_EN_S	  33
1042 #define	IMU_ERROR_STATUS_SET_MSI_NOT_EN_S	  32
1043 #define	IMU_ERROR_STATUS_SET_SPARE_P	10
1044 #define	IMU_ERROR_STATUS_SET_SPARE_P_MASK	0xfa
1045 #define	IMU_ERROR_STATUS_SET_EQ_OVER_P	  9
1046 #define	IMU_ERROR_STATUS_SET_EQ_NOT_EN_P	  8
1047 #define	IMU_ERROR_STATUS_SET_MSI_MAL_ERR_P	  7
1048 #define	IMU_ERROR_STATUS_SET_MSI_PAR_ERR_P	  6
1049 #define	IMU_ERROR_STATUS_SET_PMEACK_MES_NOT_EN_P	  5
1050 #define	IMU_ERROR_STATUS_SET_PMPME_MES_NOT_EN_P	  4
1051 #define	IMU_ERROR_STATUS_SET_FATAL_MES_NOT_EN_P	  3
1052 #define	IMU_ERROR_STATUS_SET_NONFATAL_MES_NOT_EN_P	  2
1053 #define	IMU_ERROR_STATUS_SET_COR_MES_NOT_EN_P	  1
1054 #define	IMU_ERROR_STATUS_SET_MSI_NOT_EN_P	  0
1055 #define	IMU_RDS_ERROR_LOG	0x31028
1056 #define	IMU_RDS_ERROR_LOG_TYPE	58
1057 #define	IMU_RDS_ERROR_LOG_TYPE_MASK	0x3f
1058 #define	IMU_RDS_ERROR_LOG_LENGTH	48
1059 #define	IMU_RDS_ERROR_LOG_LENGTH_MASK	0x3ff
1060 #define	IMU_RDS_ERROR_LOG_REQ_ID	32
1061 #define	IMU_RDS_ERROR_LOG_REQ_ID_MASK	0xffff
1062 #define	IMU_RDS_ERROR_LOG_TLP_TAG	24
1063 #define	IMU_RDS_ERROR_LOG_TLP_TAG_MASK	0xff
1064 #define	IMU_RDS_ERROR_LOG_BE_MESS_CODE	16
1065 #define	IMU_RDS_ERROR_LOG_BE_MESS_CODE_MASK	0xff
1066 #define	IMU_RDS_ERROR_LOG_MSI_DATA	0
1067 #define	IMU_RDS_ERROR_LOG_MSI_DATA_MASK	0xffff
1068 #define	IMU_SCS_ERROR_LOG	0x31030
1069 #define	IMU_SCS_ERROR_LOG_TYPE	58
1070 #define	IMU_SCS_ERROR_LOG_TYPE_MASK	0x3f
1071 #define	IMU_SCS_ERROR_LOG_LENGTH	48
1072 #define	IMU_SCS_ERROR_LOG_LENGTH_MASK	0x3ff
1073 #define	IMU_SCS_ERROR_LOG_REQ_ID	32
1074 #define	IMU_SCS_ERROR_LOG_REQ_ID_MASK	0xffff
1075 #define	IMU_SCS_ERROR_LOG_TLP_TAG	24
1076 #define	IMU_SCS_ERROR_LOG_TLP_TAG_MASK	0xff
1077 #define	IMU_SCS_ERROR_LOG_BE_MESS_CODE	16
1078 #define	IMU_SCS_ERROR_LOG_BE_MESS_CODE_MASK	0xff
1079 #define	IMU_SCS_ERROR_LOG_EQ_NUM	0
1080 #define	IMU_SCS_ERROR_LOG_EQ_NUM_MASK	0x3f
1081 #define	IMU_EQS_ERROR_LOG	0x31038
1082 #define	IMU_EQS_ERROR_LOG_EQ_NUM	0
1083 #define	IMU_EQS_ERROR_LOG_EQ_NUM_MASK	0x3f
1084 
1085 /* Reserved 0x31040 - 0x317f8 */
1086 
1087 #define	DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE	0x31800
1088 #define	DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE_DMC	  63
1089 #define	DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE_MMU	  1
1090 #define	DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE_IMU	  0
1091 #define	DMC_CORE_AND_BLOCK_ERROR_STATUS	0x31808
1092 #define	DMC_CORE_AND_BLOCK_ERROR_STATUS_MMU	  1
1093 #define	DMC_CORE_AND_BLOCK_ERROR_STATUS_IMU	  0
1094 #define	MULTI_CORE_ERROR_STATUS	0x31810
1095 #define	MULTI_CORE_ERROR_STATUS_PEC	  1
1096 #define	MULTI_CORE_ERROR_STATUS_DMC	  0
1097 
1098 /* Reserved 0x31818 - 0x31ff8 */
1099 
1100 #define	IMU_PERFORMANCE_COUNTER_SELECT	0x32000
1101 #define	IMU_PERFORMANCE_COUNTER_SELECT_SEL1	8
1102 #define	IMU_PERFORMANCE_COUNTER_SELECT_SEL1_MASK	0xff
1103 #define	IMU_PERFORMANCE_COUNTER_SELECT_SEL0	0
1104 #define	IMU_PERFORMANCE_COUNTER_SELECT_SEL0_MASK	0xff
1105 #define	IMU_PERFORMANCE_COUNTER_ZERO	0x32008
1106 #define	IMU_PERFORMANCE_COUNTER_ZERO_CNT	0
1107 #define	IMU_PERFORMANCE_COUNTER_ZERO_CNT_MASK	0xffffffffffffffff
1108 #define	IMU_PERFORMANCE_COUNTER_ONE	0x32010
1109 #define	IMU_PERFORMANCE_COUNTER_ONE_CNT	0
1110 #define	IMU_PERFORMANCE_COUNTER_ONE_CNT_MASK	0xffffffffffffffff
1111 
1112 /* Reserved 0x32018 - 0x33ff8 */
1113 
1114 #define	MSI_32_BIT_ADDRESS	0x34000
1115 #define	MSI_32_BIT_ADDRESS_ADDR	16
1116 #define	MSI_32_BIT_ADDRESS_ADDR_MASK	0xffff
1117 #define	MSI_64_BIT_ADDRESS	0x34008
1118 #define	MSI_64_BIT_ADDRESS_ADDR	16
1119 #define	MSI_64_BIT_ADDRESS_ADDR_MASK	0xffffffffffff
1120 
1121 /* Reserved 0x34010 - 0x34010 */
1122 
1123 #define	MEM_64_PCIE_OFFSET	0x34018
1124 #define	MEM_64_PCIE_OFFSET_ADDR	24
1125 #define	MEM_64_PCIE_OFFSET_ADDR_MASK	0xffffffffff
1126 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_7	  23
1127 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_6	  22
1128 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_5	  21
1129 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_4	  20
1130 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_3	  19
1131 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_2	  18
1132 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_1	  17
1133 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_LOAD_0	  16
1134 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL	8
1135 #define	MEM_64_PCIE_OFFSET_SPARE_CONTROL_MASK	0xff
1136 #define	MEM_64_PCIE_OFFSET_SPARE_STATUS	0
1137 #define	MEM_64_PCIE_OFFSET_SPARE_STATUS_MASK	0xff
1138 
1139 /* csr.csr  CSR module defines */
1140 
1141 #define	CSR_CSR_BASE	0x600000
1142 #define	MMU_CONTROL_AND_STATUS	0x40000
1143 #define	MMU_CONTROL_AND_STATUS_SPARES	48
1144 #define	MMU_CONTROL_AND_STATUS_SPARES_MASK	0xf
1145 #define	MMU_CONTROL_AND_STATUS_PAQ	  45
1146 #define	MMU_CONTROL_AND_STATUS_VAQ	  44
1147 #define	MMU_CONTROL_AND_STATUS_TPL	  43
1148 #define	MMU_CONTROL_AND_STATUS_TIP	  42
1149 #define	MMU_CONTROL_AND_STATUS_TCM	40
1150 #define	MMU_CONTROL_AND_STATUS_TCM_MASK	0x3
1151 #define	MMU_CONTROL_AND_STATUS_ROE	16
1152 #define	MMU_CONTROL_AND_STATUS_ROE_MASK	0x7
1153 #define	MMU_CONTROL_AND_STATUS_ROE_BIT63_ENABLE	(1 << 2)
1154 #define	MMU_CONTROL_AND_STATUS_ROE_BIT43_ENABLE	(1 << 1)
1155 #define	MMU_CONTROL_AND_STATUS_ROE_BIT35_ENABLE	(1 << 0)
1156 #define	MMU_CONTROL_AND_STATUS_PD	  12
1157 #define	MMU_CONTROL_AND_STATUS_SE	  10
1158 #define	MMU_CONTROL_AND_STATUS_CM	8
1159 #define	MMU_CONTROL_AND_STATUS_CM_MASK	0x3
1160 #define	MMU_CONTROL_AND_STATUS_BE	  1
1161 #define	MMU_CONTROL_AND_STATUS_TE	  0
1162 #define	MMU_TSB_CONTROL	0x40008
1163 #define	MMU_TSB_CONTROL_TB	13
1164 #define	MMU_TSB_CONTROL_TB_MASK	0x3fffffff
1165 #define	MMU_TSB_CONTROL_PS	  8
1166 #define	MMU_TSB_CONTROL_TS	0
1167 #define	MMU_TSB_CONTROL_TS_MASK	0xf
1168 
1169 /* Reserved 0x40010 - 0x400f8 */
1170 
1171 #define	MMU_TTE_CACHE_FLUSH_ADDRESS	0x40100
1172 #define	MMU_TTE_CACHE_FLUSH_ADDRESS_FLSH_ADDR	6
1173 #define	MMU_TTE_CACHE_FLUSH_ADDRESS_FLSH_ADDR_MASK	0x1fffffffff
1174 #define	MMU_TTE_CACHE_INVALIDATE	0x40108
1175 #define	MMU_TTE_CACHE_INVALIDATE_FLSH_TTE	0
1176 #define	MMU_TTE_CACHE_INVALIDATE_FLSH_TTE_MASK	0xffffffffffffffff
1177 
1178 /* Reserved 0x40110 - 0x40ff8 */
1179 
1180 #define	MMU_ERROR_LOG_ENABLE	0x41000
1181 #define	MMU_ERROR_LOG_ENABLE_EN	0
1182 #define	MMU_ERROR_LOG_ENABLE_EN_MASK	0xffff
1183 #define	MMU_INTERRUPT_ENABLE	0x41008
1184 #define	MMU_INTERRUPT_ENABLE_EN_S	32
1185 #define	MMU_INTERRUPT_ENABLE_EN_S_MASK	0xffff
1186 #define	MMU_INTERRUPT_ENABLE_EN_P	0
1187 #define	MMU_INTERRUPT_ENABLE_EN_P_MASK	0xffff
1188 #define	MMU_INTERRUPT_STATUS	0x41010
1189 #define	MMU_INTERRUPT_STATUS_ERR_S	32
1190 #define	MMU_INTERRUPT_STATUS_ERR_S_MASK	0xffff
1191 #define	MMU_INTERRUPT_STATUS_ERR_P	0
1192 #define	MMU_INTERRUPT_STATUS_ERR_P_MASK	0xffff
1193 #define	MMU_INTERRUPT_STATUS_TBW_DPE_S	  47
1194 #define	MMU_INTERRUPT_STATUS_TBW_ERR_S	  46
1195 #define	MMU_INTERRUPT_STATUS_TBW_UDE_S	  45
1196 #define	MMU_INTERRUPT_STATUS_TBW_DME_S	  44
1197 #define	MMU_INTERRUPT_STATUS_SPARE3_S	  43
1198 #define	MMU_INTERRUPT_STATUS_SPARE2_S	  42
1199 #define	MMU_INTERRUPT_STATUS_TTC_CAE_S	  41
1200 #define	MMU_INTERRUPT_STATUS_TTC_DPE_S	  40
1201 #define	MMU_INTERRUPT_STATUS_TTE_PRT_S	  39
1202 #define	MMU_INTERRUPT_STATUS_TTE_INV_S	  38
1203 #define	MMU_INTERRUPT_STATUS_TRN_OOR_S	  37
1204 #define	MMU_INTERRUPT_STATUS_TRN_ERR_S	  36
1205 #define	MMU_INTERRUPT_STATUS_SPARE1_S	  35
1206 #define	MMU_INTERRUPT_STATUS_SPARE0_S	  34
1207 #define	MMU_INTERRUPT_STATUS_BYP_OOR_S	  33
1208 #define	MMU_INTERRUPT_STATUS_BYP_ERR_S	  32
1209 #define	MMU_INTERRUPT_STATUS_TBW_DPE_P	  15
1210 #define	MMU_INTERRUPT_STATUS_TBW_ERR_P	  14
1211 #define	MMU_INTERRUPT_STATUS_TBW_UDE_P	  13
1212 #define	MMU_INTERRUPT_STATUS_TBW_DME_P	  12
1213 #define	MMU_INTERRUPT_STATUS_SPARE3_P	  11
1214 #define	MMU_INTERRUPT_STATUS_SPARE2_P	  10
1215 #define	MMU_INTERRUPT_STATUS_TTC_CAE_P	  9
1216 #define	MMU_INTERRUPT_STATUS_TTC_DPE_P	  8
1217 #define	MMU_INTERRUPT_STATUS_TTE_PRT_P	  7
1218 #define	MMU_INTERRUPT_STATUS_TTE_INV_P	  6
1219 #define	MMU_INTERRUPT_STATUS_TRN_OOR_P	  5
1220 #define	MMU_INTERRUPT_STATUS_TRN_ERR_P	  4
1221 #define	MMU_INTERRUPT_STATUS_SPARE1_P	  3
1222 #define	MMU_INTERRUPT_STATUS_SPARE0_P	  2
1223 #define	MMU_INTERRUPT_STATUS_BYP_OOR_P	  1
1224 #define	MMU_INTERRUPT_STATUS_BYP_ERR_P	  0
1225 #define	MMU_ERROR_STATUS_CLEAR	0x41018
1226 #define	MMU_ERROR_STATUS_CLEAR_TBW_DPE_S	  47
1227 #define	MMU_ERROR_STATUS_CLEAR_TBW_ERR_S	  46
1228 #define	MMU_ERROR_STATUS_CLEAR_TBW_UDE_S	  45
1229 #define	MMU_ERROR_STATUS_CLEAR_TBW_DME_S	  44
1230 #define	MMU_ERROR_STATUS_CLEAR_SPARE3_S	  43
1231 #define	MMU_ERROR_STATUS_CLEAR_SPARE2_S	  42
1232 #define	MMU_ERROR_STATUS_CLEAR_TTC_CAE_S	  41
1233 #define	MMU_ERROR_STATUS_CLEAR_TTC_DPE_S	  40
1234 #define	MMU_ERROR_STATUS_CLEAR_TTE_PRT_S	  39
1235 #define	MMU_ERROR_STATUS_CLEAR_TTE_INV_S	  38
1236 #define	MMU_ERROR_STATUS_CLEAR_TRN_OOR_S	  37
1237 #define	MMU_ERROR_STATUS_CLEAR_TRN_ERR_S	  36
1238 #define	MMU_ERROR_STATUS_CLEAR_SPARE1_S	  35
1239 #define	MMU_ERROR_STATUS_CLEAR_SPARE0_S	  34
1240 #define	MMU_ERROR_STATUS_CLEAR_BYP_OOR_S	  33
1241 #define	MMU_ERROR_STATUS_CLEAR_BYP_ERR_S	  32
1242 #define	MMU_ERROR_STATUS_CLEAR_TBW_DPE_P	  15
1243 #define	MMU_ERROR_STATUS_CLEAR_TBW_ERR_P	  14
1244 #define	MMU_ERROR_STATUS_CLEAR_TBW_UDE_P	  13
1245 #define	MMU_ERROR_STATUS_CLEAR_TBW_DME_P	  12
1246 #define	MMU_ERROR_STATUS_CLEAR_SPARE3_P	  11
1247 #define	MMU_ERROR_STATUS_CLEAR_SPARE2_P	  10
1248 #define	MMU_ERROR_STATUS_CLEAR_TTC_CAE_P	  9
1249 #define	MMU_ERROR_STATUS_CLEAR_TTC_DPE_P	  8
1250 #define	MMU_ERROR_STATUS_CLEAR_TTE_PRT_P	  7
1251 #define	MMU_ERROR_STATUS_CLEAR_TTE_INV_P	  6
1252 #define	MMU_ERROR_STATUS_CLEAR_TRN_OOR_P	  5
1253 #define	MMU_ERROR_STATUS_CLEAR_TRN_ERR_P	  4
1254 #define	MMU_ERROR_STATUS_CLEAR_SPARE1_P	  3
1255 #define	MMU_ERROR_STATUS_CLEAR_SPARE0_P	  2
1256 #define	MMU_ERROR_STATUS_CLEAR_BYP_OOR_P	  1
1257 #define	MMU_ERROR_STATUS_CLEAR_BYP_ERR_P	  0
1258 #define	MMU_ERROR_STATUS_SET	0x41020
1259 #define	MMU_ERROR_STATUS_SET_TBW_DPE_S	  47
1260 #define	MMU_ERROR_STATUS_SET_TBW_ERR_S	  46
1261 #define	MMU_ERROR_STATUS_SET_TBW_UDE_S	  45
1262 #define	MMU_ERROR_STATUS_SET_TBW_DME_S	  44
1263 #define	MMU_ERROR_STATUS_SET_SPARE3_S	  43
1264 #define	MMU_ERROR_STATUS_SET_SPARE2_S	  42
1265 #define	MMU_ERROR_STATUS_SET_TTC_CAE_S	  41
1266 #define	MMU_ERROR_STATUS_SET_TTC_DPE_S	  40
1267 #define	MMU_ERROR_STATUS_SET_TTE_PRT_S	  39
1268 #define	MMU_ERROR_STATUS_SET_TTE_INV_S	  38
1269 #define	MMU_ERROR_STATUS_SET_TRN_OOR_S	  37
1270 #define	MMU_ERROR_STATUS_SET_TRN_ERR_S	  36
1271 #define	MMU_ERROR_STATUS_SET_SPARE1_S	  35
1272 #define	MMU_ERROR_STATUS_SET_SPARE0_S	  34
1273 #define	MMU_ERROR_STATUS_SET_BYP_OOR_S	  33
1274 #define	MMU_ERROR_STATUS_SET_BYP_ERR_S	  32
1275 #define	MMU_ERROR_STATUS_SET_TBW_DPE_P	  15
1276 #define	MMU_ERROR_STATUS_SET_TBW_ERR_P	  14
1277 #define	MMU_ERROR_STATUS_SET_TBW_UDE_P	  13
1278 #define	MMU_ERROR_STATUS_SET_TBW_DME_P	  12
1279 #define	MMU_ERROR_STATUS_SET_SPARE3_P	  11
1280 #define	MMU_ERROR_STATUS_SET_SPARE2_P	  10
1281 #define	MMU_ERROR_STATUS_SET_TTC_CAE_P	  9
1282 #define	MMU_ERROR_STATUS_SET_TTC_DPE_P	  8
1283 #define	MMU_ERROR_STATUS_SET_TTE_PRT_P	  7
1284 #define	MMU_ERROR_STATUS_SET_TTE_INV_P	  6
1285 #define	MMU_ERROR_STATUS_SET_TRN_OOR_P	  5
1286 #define	MMU_ERROR_STATUS_SET_TRN_ERR_P	  4
1287 #define	MMU_ERROR_STATUS_SET_SPARE1_P	  3
1288 #define	MMU_ERROR_STATUS_SET_SPARE0_P	  2
1289 #define	MMU_ERROR_STATUS_SET_BYP_OOR_P	  1
1290 #define	MMU_ERROR_STATUS_SET_BYP_ERR_P	  0
1291 #define	MMU_TRANSLATION_FAULT_ADDRESS	0x41028
1292 #define	MMU_TRANSLATION_FAULT_ADDRESS_VA	2
1293 #define	MMU_TRANSLATION_FAULT_ADDRESS_VA_MASK	0x3fffffffffffffff
1294 #define	MMU_TRANSLATION_FAULT_STATUS	0x41030
1295 #define	MMU_TRANSLATION_FAULT_STATUS_ENTRY	32
1296 #define	MMU_TRANSLATION_FAULT_STATUS_ENTRY_MASK	0x1ff
1297 #define	MMU_TRANSLATION_FAULT_STATUS_TYPE	16
1298 #define	MMU_TRANSLATION_FAULT_STATUS_TYPE_MASK	0x7f
1299 #define	MMU_TRANSLATION_FAULT_STATUS_ID	0
1300 #define	MMU_TRANSLATION_FAULT_STATUS_ID_MASK	0xffff
1301 
1302 /* Reserved 0x41038 - 0x41ff8 */
1303 
1304 #define	MMU_PERFORMANCE_COUNTER_SELECT	0x42000
1305 #define	MMU_PERFORMANCE_COUNTER_SELECT_SEL1	8
1306 #define	MMU_PERFORMANCE_COUNTER_SELECT_SEL1_MASK	0xff
1307 #define	MMU_PERFORMANCE_COUNTER_SELECT_SEL0	0
1308 #define	MMU_PERFORMANCE_COUNTER_SELECT_SEL0_MASK	0xff
1309 #define	MMU_PERFORMANCE_COUNTER_ZERO	0x42008
1310 #define	MMU_PERFORMANCE_COUNTER_ZERO_CNT	0
1311 #define	MMU_PERFORMANCE_COUNTER_ZERO_CNT_MASK	0xffffffffffffffff
1312 #define	MMU_PERFORMANCE_COUNTER_ONE	0x42010
1313 #define	MMU_PERFORMANCE_COUNTER_ONE_CNT	0
1314 #define	MMU_PERFORMANCE_COUNTER_ONE_CNT_MASK	0xffffffffffffffff
1315 
1316 /* Reserved 0x42018 - 0x43ff8 */
1317 
1318 
1319 /* Reserved 0x44008 - 0x45ff8 */
1320 
1321 #define	MMU_TTE_CACHE_VIRTUAL_TAG	0x46000
1322 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES	64
1323 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_CNT	32
1324 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_CNT_MASK	0xfff
1325 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_TAG	16
1326 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_TAG_MASK	0xffff
1327 #define	MMU_TTE_CACHE_VIRTUAL_TAG_ENTRIES_VLD	  0
1328 
1329 /* Reserved 0x46200 - 0x46ff8 */
1330 
1331 #define	MMU_TTE_CACHE_PHYSICAL_TAG	0x47000
1332 #define	MMU_TTE_CACHE_PHYSICAL_TAG_ENTRIES	64
1333 #define	MMU_TTE_CACHE_PHYSICAL_TAG_ENTRIES_TAG	6
1334 #define	MMU_TTE_CACHE_PHYSICAL_TAG_ENTRIES_TAG_MASK	0x1fffffffff
1335 #define	MMU_TTE_CACHE_PHYSICAL_TAG_ENTRIES_VLD	  0
1336 
1337 /* Reserved 0x47200 - 0x47ff8 */
1338 
1339 #define	MMU_TTE_CACHE_DATA	0x48000
1340 #define	MMU_TTE_CACHE_DATA_ENTRIES	512
1341 #define	MMU_TTE_CACHE_DATA_ENTRIES_PAR	60
1342 #define	MMU_TTE_CACHE_DATA_ENTRIES_PAR_MASK	0xf
1343 #define	MMU_TTE_CACHE_DATA_ENTRIES_PPN	13
1344 #define	MMU_TTE_CACHE_DATA_ENTRIES_PPN_MASK	0x3fffffff
1345 #define	MMU_TTE_CACHE_DATA_ENTRIES_WRT	  1
1346 #define	MMU_TTE_CACHE_DATA_ENTRIES_VLD	  0
1347 
1348 /* cib.csr  CIB module defines */
1349 
1350 #define	CIB_CSR_BASE	0x600000
1351 
1352 /* Reserved 0x50008 - 0x50ff8 */
1353 
1354 #define	ILU_ERROR_LOG_ENABLE	0x51000
1355 #define	ILU_ERROR_LOG_ENABLE_SPARE3	  7
1356 #define	ILU_ERROR_LOG_ENABLE_SPARE2	  6
1357 #define	ILU_ERROR_LOG_ENABLE_SPARE1	  5
1358 #define	ILU_ERROR_LOG_ENABLE_IHB_PE	  4
1359 #define	ILU_INTERRUPT_ENABLE	0x51008
1360 #define	ILU_INTERRUPT_ENABLE_SPARE3_S	  39
1361 #define	ILU_INTERRUPT_ENABLE_SPARE2_S	  38
1362 #define	ILU_INTERRUPT_ENABLE_SPARE1_S	  37
1363 #define	ILU_INTERRUPT_ENABLE_IHB_PE_S	  36
1364 #define	ILU_INTERRUPT_ENABLE_SPARE3_P	  7
1365 #define	ILU_INTERRUPT_ENABLE_SPARE2_P	  6
1366 #define	ILU_INTERRUPT_ENABLE_SPARE1_P	  5
1367 #define	ILU_INTERRUPT_ENABLE_IHB_PE_P	  4
1368 #define	ILU_INTERRUPT_STATUS	0x51010
1369 #define	ILU_INTERRUPT_STATUS_SPARE3_S	  39
1370 #define	ILU_INTERRUPT_STATUS_SPARE2_S	  38
1371 #define	ILU_INTERRUPT_STATUS_SPARE1_S	  37
1372 #define	ILU_INTERRUPT_STATUS_IHB_PE_S	  36
1373 #define	ILU_INTERRUPT_STATUS_SPARE3_P	  7
1374 #define	ILU_INTERRUPT_STATUS_SPARE2_P	  6
1375 #define	ILU_INTERRUPT_STATUS_SPARE1_P	  5
1376 #define	ILU_INTERRUPT_STATUS_IHB_PE_P	  4
1377 #define	ILU_ERROR_STATUS_CLEAR	0x51018
1378 #define	ILU_ERROR_STATUS_CLEAR_SPARE3_S	  39
1379 #define	ILU_ERROR_STATUS_CLEAR_SPARE2_S	  38
1380 #define	ILU_ERROR_STATUS_CLEAR_SPARE1_S	  37
1381 #define	ILU_ERROR_STATUS_CLEAR_IHB_PE_S	  36
1382 #define	ILU_ERROR_STATUS_CLEAR_SPARE3_P	  7
1383 #define	ILU_ERROR_STATUS_CLEAR_SPARE2_P	  6
1384 #define	ILU_ERROR_STATUS_CLEAR_SPARE1_P	  5
1385 #define	ILU_ERROR_STATUS_CLEAR_IHB_PE_P	  4
1386 #define	ILU_ERROR_STATUS_SET	0x51020
1387 #define	ILU_ERROR_STATUS_SET_SPARE3_S	  39
1388 #define	ILU_ERROR_STATUS_SET_SPARE2_S	  38
1389 #define	ILU_ERROR_STATUS_SET_SPARE1_S	  37
1390 #define	ILU_ERROR_STATUS_SET_IHB_PE_S	  36
1391 #define	ILU_ERROR_STATUS_SET_SPARE3_P	  7
1392 #define	ILU_ERROR_STATUS_SET_SPARE2_P	  6
1393 #define	ILU_ERROR_STATUS_SET_SPARE1_P	  5
1394 #define	ILU_ERROR_STATUS_SET_IHB_PE_P	  4
1395 
1396 /* Reserved 0x51028 - 0x517f8 */
1397 
1398 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE	0x51800
1399 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE_PEC	  63
1400 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE_PEC_ILU	  3
1401 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE_PEC_UE	  2
1402 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE_PEC_CE	  1
1403 #define	PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE_PEC_OE	  0
1404 #define	PEC_CORE_AND_BLOCK_INTERRUPT_STATUS	0x51808
1405 #define	PEC_CORE_AND_BLOCK_INTERRUPT_STATUS_ILU	  3
1406 #define	PEC_CORE_AND_BLOCK_INTERRUPT_STATUS_UE	  2
1407 #define	PEC_CORE_AND_BLOCK_INTERRUPT_STATUS_CE	  1
1408 #define	PEC_CORE_AND_BLOCK_INTERRUPT_STATUS_OE	  0
1409 
1410 /* Reserved 0x51810 - 0x51ff8 */
1411 
1412 #define	ILU_DEVICE_CAPABILITIES	0x52000
1413 #define	ILU_DEVICE_CAPABILITIES_ESTAR	  0
1414 
1415 /* cru.csr  CRU module defines */
1416 
1417 #define	CRU_CSR_BASE	0x600000
1418 #define	DMC_DEBUG_SELECT_FOR_PORT_A	0x53000
1419 #define	DMC_DEBUG_SELECT_FOR_PORT_A_BLOCK_SEL	6
1420 #define	DMC_DEBUG_SELECT_FOR_PORT_A_BLOCK_SEL_MASK	0xf
1421 #define	DMC_DEBUG_SELECT_FOR_PORT_A_SUB_SEL	3
1422 #define	DMC_DEBUG_SELECT_FOR_PORT_A_SUB_SEL_MASK	0x7
1423 #define	DMC_DEBUG_SELECT_FOR_PORT_A_SIGNAL_SEL	0
1424 #define	DMC_DEBUG_SELECT_FOR_PORT_A_SIGNAL_SEL_MASK	0x7
1425 #define	DMC_DEBUG_SELECT_FOR_PORT_B	0x53008
1426 #define	DMC_DEBUG_SELECT_FOR_PORT_B_BLOCK_SEL	6
1427 #define	DMC_DEBUG_SELECT_FOR_PORT_B_BLOCK_SEL_MASK	0xf
1428 #define	DMC_DEBUG_SELECT_FOR_PORT_B_SUB_SEL	3
1429 #define	DMC_DEBUG_SELECT_FOR_PORT_B_SUB_SEL_MASK	0x7
1430 #define	DMC_DEBUG_SELECT_FOR_PORT_B_SIGNAL_SEL	0
1431 #define	DMC_DEBUG_SELECT_FOR_PORT_B_SIGNAL_SEL_MASK	0x7
1432 
1433 /* Reserved 0x53010 - 0x530f8 */
1434 
1435 #define	DMC_PCI_EXPRESS_CONFIGURATION	0x53100
1436 #define	DMC_PCI_EXPRESS_CONFIGURATION_BUS_NUM	24
1437 #define	DMC_PCI_EXPRESS_CONFIGURATION_BUS_NUM_MASK	0xff
1438 #define	DMC_PCI_EXPRESS_CONFIGURATION_REQ_ID	0
1439 #define	DMC_PCI_EXPRESS_CONFIGURATION_REQ_ID_MASK	0xffff
1440 
1441 /* psb.csr  PSB module defines */
1442 
1443 #define	PSB_CSR_BASE	0x600000
1444 #define	PACKET_SCOREBOARD_DMA_SET	0x60000
1445 #define	PACKET_SCOREBOARD_DMA_SET_ENTRIES	32
1446 #define	PACKET_SCOREBOARD_DMA_SET_ENTRIES_ENTRY	0
1447 #define	PACKET_SCOREBOARD_DMA_SET_ENTRIES_ENTRY_MASK	0x1ffffffffff
1448 
1449 /* Reserved 0x60100 - 0x63ff8 */
1450 
1451 #define	PACKET_SCOREBOARD_PIO_SET	0x64000
1452 #define	PACKET_SCOREBOARD_PIO_SET_ENTRIES	16
1453 #define	PACKET_SCOREBOARD_PIO_SET_ENTRIES_ENTRY	0
1454 #define	PACKET_SCOREBOARD_PIO_SET_ENTRIES_ENTRY_MASK	0x3f
1455 
1456 /* tsb.csr  TSB module defines */
1457 
1458 #define	TSB_CSR_BASE	0x600000
1459 #define	TRANSACTION_SCOREBOARD_SET	0x70000
1460 #define	TRANSACTION_SCOREBOARD_SET_ENTRIES	32
1461 #define	TRANSACTION_SCOREBOARD_SET_ENTRIES_ENTRY	0
1462 #define	TRANSACTION_SCOREBOARD_SET_ENTRIES_ENTRY_MASK	0xffffffffffff
1463 #define	TRANSACTION_SCOREBOARD_STATUS	0x70100
1464 #define	TRANSACTION_SCOREBOARD_STATUS_FULL	  7
1465 #define	TRANSACTION_SCOREBOARD_STATUS_NUM_PND_DMA	1
1466 #define	TRANSACTION_SCOREBOARD_STATUS_NUM_PND_DMA_MASK	0x3f
1467 #define	TRANSACTION_SCOREBOARD_STATUS_EMPTY	  0
1468 
1469 /* tlr.csr  TLR module defines */
1470 
1471 #define	TLR_CSR_BASE	0x600000
1472 #define	TLU_CONTROL	0x80000
1473 #define	TLU_CONTROL_L0S_TIM	24
1474 #define	TLU_CONTROL_L0S_TIM_MASK	0xff
1475 #define	TLU_CONTROL_NPWR_EN	  20
1476 #define	TLU_CONTROL_CTO_SEL	16
1477 #define	TLU_CONTROL_CTO_SEL_MASK	0x7
1478 #define	TLU_CONTROL_CONFIG	0
1479 #define	TLU_CONTROL_CONFIG_MASK	0xffff
1480 #define	TLU_STATUS	0x80008
1481 #define	TLU_STATUS_DRAIN	  8
1482 #define	TLU_STATUS_STATUS	0
1483 #define	TLU_STATUS_STATUS_MASK	0xff
1484 #define	TLU_PME_TURN_OFF_GENERATE	0x80010
1485 #define	TLU_PME_TURN_OFF_GENERATE_PTO	  0
1486 #define	TLU_INGRESS_CREDITS_INITIAL	0x80018
1487 #define	TLU_INGRESS_CREDITS_INITIAL_CHC	52
1488 #define	TLU_INGRESS_CREDITS_INITIAL_CHC_MASK	0xff
1489 #define	TLU_INGRESS_CREDITS_INITIAL_CDC	40
1490 #define	TLU_INGRESS_CREDITS_INITIAL_CDC_MASK	0xfff
1491 #define	TLU_INGRESS_CREDITS_INITIAL_NHC	32
1492 #define	TLU_INGRESS_CREDITS_INITIAL_NHC_MASK	0xff
1493 #define	TLU_INGRESS_CREDITS_INITIAL_NDC	20
1494 #define	TLU_INGRESS_CREDITS_INITIAL_NDC_MASK	0xfff
1495 #define	TLU_INGRESS_CREDITS_INITIAL_PHC	12
1496 #define	TLU_INGRESS_CREDITS_INITIAL_PHC_MASK	0xff
1497 #define	TLU_INGRESS_CREDITS_INITIAL_PDC	0
1498 #define	TLU_INGRESS_CREDITS_INITIAL_PDC_MASK	0xfff
1499 
1500 /* Reserved 0x80020 - 0x800f8 */
1501 
1502 #define	TLU_DIAGNOSTIC	0x80100
1503 #define	TLU_DIAGNOSTIC_LNK_MAX	48
1504 #define	TLU_DIAGNOSTIC_LNK_MAX_MASK	0x3f
1505 #define	TLU_DIAGNOSTIC_CHK_DIS	32
1506 #define	TLU_DIAGNOSTIC_CHK_DIS_MASK	0xffff
1507 #define	TLU_DIAGNOSTIC_EPI_PAR	16
1508 #define	TLU_DIAGNOSTIC_EPI_PAR_MASK	0xff
1509 #define	TLU_DIAGNOSTIC_IDI_PAR	12
1510 #define	TLU_DIAGNOSTIC_IDI_PAR_MASK	0xf
1511 #define	TLU_DIAGNOSTIC_IHI_PAR	8
1512 #define	TLU_DIAGNOSTIC_IHI_PAR_MASK	0xf
1513 #define	TLU_DIAGNOSTIC_EPI_TRG	  7
1514 #define	TLU_DIAGNOSTIC_IDI_TRG	  6
1515 #define	TLU_DIAGNOSTIC_IHI_TRG	  5
1516 #define	TLU_DIAGNOSTIC_MRC_TRG	  4
1517 #define	TLU_DIAGNOSTIC_EPP_DIS	  1
1518 #define	TLU_DIAGNOSTIC_IFC_DIS	  0
1519 
1520 /* Reserved 0x80108 - 0x801f8 */
1521 
1522 #define	TLU_EGRESS_CREDITS_CONSUMED	0x80200
1523 #define	TLU_EGRESS_CREDITS_CONSUMED_CHI	  62
1524 #define	TLU_EGRESS_CREDITS_CONSUMED_NHI	  61
1525 #define	TLU_EGRESS_CREDITS_CONSUMED_PHI	  60
1526 #define	TLU_EGRESS_CREDITS_CONSUMED_CHC	52
1527 #define	TLU_EGRESS_CREDITS_CONSUMED_CHC_MASK	0xff
1528 #define	TLU_EGRESS_CREDITS_CONSUMED_CDC	40
1529 #define	TLU_EGRESS_CREDITS_CONSUMED_CDC_MASK	0xfff
1530 #define	TLU_EGRESS_CREDITS_CONSUMED_NHC	32
1531 #define	TLU_EGRESS_CREDITS_CONSUMED_NHC_MASK	0xff
1532 #define	TLU_EGRESS_CREDITS_CONSUMED_NDC	20
1533 #define	TLU_EGRESS_CREDITS_CONSUMED_NDC_MASK	0xfff
1534 #define	TLU_EGRESS_CREDITS_CONSUMED_PHC	12
1535 #define	TLU_EGRESS_CREDITS_CONSUMED_PHC_MASK	0xff
1536 #define	TLU_EGRESS_CREDITS_CONSUMED_PDC	0
1537 #define	TLU_EGRESS_CREDITS_CONSUMED_PDC_MASK	0xfff
1538 #define	TLU_EGRESS_CREDIT_LIMIT	0x80208
1539 #define	TLU_EGRESS_CREDIT_LIMIT_CDI	  62
1540 #define	TLU_EGRESS_CREDIT_LIMIT_NDI	  61
1541 #define	TLU_EGRESS_CREDIT_LIMIT_PDI	  60
1542 #define	TLU_EGRESS_CREDIT_LIMIT_CHC	52
1543 #define	TLU_EGRESS_CREDIT_LIMIT_CHC_MASK	0xff
1544 #define	TLU_EGRESS_CREDIT_LIMIT_CDC	40
1545 #define	TLU_EGRESS_CREDIT_LIMIT_CDC_MASK	0xfff
1546 #define	TLU_EGRESS_CREDIT_LIMIT_NHC	32
1547 #define	TLU_EGRESS_CREDIT_LIMIT_NHC_MASK	0xff
1548 #define	TLU_EGRESS_CREDIT_LIMIT_NDC	20
1549 #define	TLU_EGRESS_CREDIT_LIMIT_NDC_MASK	0xfff
1550 #define	TLU_EGRESS_CREDIT_LIMIT_PHC	12
1551 #define	TLU_EGRESS_CREDIT_LIMIT_PHC_MASK	0xff
1552 #define	TLU_EGRESS_CREDIT_LIMIT_PDC	0
1553 #define	TLU_EGRESS_CREDIT_LIMIT_PDC_MASK	0xfff
1554 #define	TLU_EGRESS_RETRY_BUFFER	0x80210
1555 #define	TLU_EGRESS_RETRY_BUFFER_CC	32
1556 #define	TLU_EGRESS_RETRY_BUFFER_CC_MASK	0xffff
1557 #define	TLU_EGRESS_RETRY_BUFFER_CL	0
1558 #define	TLU_EGRESS_RETRY_BUFFER_CL_MASK	0xffff
1559 #define	TLU_INGRESS_CREDITS_ALLOCATED	0x80218
1560 #define	TLU_INGRESS_CREDITS_ALLOCATED_CHC	52
1561 #define	TLU_INGRESS_CREDITS_ALLOCATED_CHC_MASK	0xff
1562 #define	TLU_INGRESS_CREDITS_ALLOCATED_CDC	40
1563 #define	TLU_INGRESS_CREDITS_ALLOCATED_CDC_MASK	0xfff
1564 #define	TLU_INGRESS_CREDITS_ALLOCATED_NHC	32
1565 #define	TLU_INGRESS_CREDITS_ALLOCATED_NHC_MASK	0xff
1566 #define	TLU_INGRESS_CREDITS_ALLOCATED_NDC	20
1567 #define	TLU_INGRESS_CREDITS_ALLOCATED_NDC_MASK	0xfff
1568 #define	TLU_INGRESS_CREDITS_ALLOCATED_PHC	12
1569 #define	TLU_INGRESS_CREDITS_ALLOCATED_PHC_MASK	0xff
1570 #define	TLU_INGRESS_CREDITS_ALLOCATED_PDC	0
1571 #define	TLU_INGRESS_CREDITS_ALLOCATED_PDC_MASK	0xfff
1572 #define	TLU_INGRESS_CREDITS_RECEIVED	0x80220
1573 #define	TLU_INGRESS_CREDITS_RECEIVED_CHC	52
1574 #define	TLU_INGRESS_CREDITS_RECEIVED_CHC_MASK	0xff
1575 #define	TLU_INGRESS_CREDITS_RECEIVED_CDC	40
1576 #define	TLU_INGRESS_CREDITS_RECEIVED_CDC_MASK	0xfff
1577 #define	TLU_INGRESS_CREDITS_RECEIVED_NHC	32
1578 #define	TLU_INGRESS_CREDITS_RECEIVED_NHC_MASK	0xff
1579 #define	TLU_INGRESS_CREDITS_RECEIVED_NDC	20
1580 #define	TLU_INGRESS_CREDITS_RECEIVED_NDC_MASK	0xfff
1581 #define	TLU_INGRESS_CREDITS_RECEIVED_PHC	12
1582 #define	TLU_INGRESS_CREDITS_RECEIVED_PHC_MASK	0xff
1583 #define	TLU_INGRESS_CREDITS_RECEIVED_PDC	0
1584 #define	TLU_INGRESS_CREDITS_RECEIVED_PDC_MASK	0xfff
1585 
1586 /* Reserved 0x80228 - 0x80ff8 */
1587 
1588 #define	TLU_OTHER_EVENT_LOG_ENABLE	0x81000
1589 #define	TLU_OTHER_EVENT_LOG_ENABLE_EN	0
1590 #define	TLU_OTHER_EVENT_LOG_ENABLE_EN_MASK	0xffffff
1591 #define	TLU_OTHER_EVENT_INTERRUPT_ENABLE	0x81008
1592 #define	TLU_OTHER_EVENT_INTERRUPT_ENABLE_EN_S	32
1593 #define	TLU_OTHER_EVENT_INTERRUPT_ENABLE_EN_S_MASK	0xffffff
1594 #define	TLU_OTHER_EVENT_INTERRUPT_ENABLE_EN_P	0
1595 #define	TLU_OTHER_EVENT_INTERRUPT_ENABLE_EN_P_MASK	0xffffff
1596 #define	TLU_OTHER_EVENT_INTERRUPT_STATUS	0x81010
1597 #define	TLU_OTHER_EVENT_INTERRUPT_STATUS_ERR_S	32
1598 #define	TLU_OTHER_EVENT_INTERRUPT_STATUS_ERR_S_MASK	0xffffff
1599 #define	TLU_OTHER_EVENT_INTERRUPT_STATUS_ERR_P	0
1600 #define	TLU_OTHER_EVENT_INTERRUPT_STATUS_ERR_P_MASK	0xffffff
1601 #define	TLU_OTHER_EVENT_STATUS_CLEAR	0x81018
1602 #define	TLU_OTHER_EVENT_STATUS_CLEAR_SPARE_S	  55
1603 #define	TLU_OTHER_EVENT_STATUS_CLEAR_MFC_S	  54
1604 #define	TLU_OTHER_EVENT_STATUS_CLEAR_CTO_S	  53
1605 #define	TLU_OTHER_EVENT_STATUS_CLEAR_NFP_S	  52
1606 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LWC_S	  51
1607 #define	TLU_OTHER_EVENT_STATUS_CLEAR_MRC_S	  50
1608 #define	TLU_OTHER_EVENT_STATUS_CLEAR_WUC_S	  49
1609 #define	TLU_OTHER_EVENT_STATUS_CLEAR_RUC_S	  48
1610 #define	TLU_OTHER_EVENT_STATUS_CLEAR_CRS_S	  47
1611 #define	TLU_OTHER_EVENT_STATUS_CLEAR_IIP_S	  46
1612 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EDP_S	  45
1613 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EHP_S	  44
1614 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LIN_S	  43
1615 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LRS_S	  42
1616 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LDN_S	  41
1617 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LUP_S	  40
1618 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LPU_S	38
1619 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LPU_S_MASK	0x3
1620 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERU_S	  37
1621 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERO_S	  36
1622 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EMP_S	  35
1623 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EPE_S	  34
1624 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERP_S	  33
1625 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EIP_S	  32
1626 #define	TLU_OTHER_EVENT_STATUS_CLEAR_SPARE_P	  23
1627 #define	TLU_OTHER_EVENT_STATUS_CLEAR_MFC_P	  22
1628 #define	TLU_OTHER_EVENT_STATUS_CLEAR_CTO_P	  21
1629 #define	TLU_OTHER_EVENT_STATUS_CLEAR_NFP_P	  20
1630 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LWC_P	  19
1631 #define	TLU_OTHER_EVENT_STATUS_CLEAR_MRC_P	  18
1632 #define	TLU_OTHER_EVENT_STATUS_CLEAR_WUC_P	  17
1633 #define	TLU_OTHER_EVENT_STATUS_CLEAR_RUC_P	  16
1634 #define	TLU_OTHER_EVENT_STATUS_CLEAR_CRS_P	  15
1635 #define	TLU_OTHER_EVENT_STATUS_CLEAR_IIP_P	  14
1636 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EDP_P	  13
1637 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EHP_P	  12
1638 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LIN_P	  11
1639 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LRS_P	  10
1640 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LDN_P	  9
1641 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LUP_P	  8
1642 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LPU_P	6
1643 #define	TLU_OTHER_EVENT_STATUS_CLEAR_LPU_P_MASK	0x3
1644 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERU_P	  5
1645 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERO_P	  4
1646 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EMP_P	  3
1647 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EPE_P	  2
1648 #define	TLU_OTHER_EVENT_STATUS_CLEAR_ERP_P	  1
1649 #define	TLU_OTHER_EVENT_STATUS_CLEAR_EIP_P	  0
1650 #define	TLU_OTHER_EVENT_STATUS_SET	0x81020
1651 #define	TLU_OTHER_EVENT_STATUS_SET_SPARE_S	  55
1652 #define	TLU_OTHER_EVENT_STATUS_SET_MFC_S	  54
1653 #define	TLU_OTHER_EVENT_STATUS_SET_CTO_S	  53
1654 #define	TLU_OTHER_EVENT_STATUS_SET_NFP_S	  52
1655 #define	TLU_OTHER_EVENT_STATUS_SET_LWC_S	  51
1656 #define	TLU_OTHER_EVENT_STATUS_SET_MRC_S	  50
1657 #define	TLU_OTHER_EVENT_STATUS_SET_WUC_S	  49
1658 #define	TLU_OTHER_EVENT_STATUS_SET_RUC_S	  48
1659 #define	TLU_OTHER_EVENT_STATUS_SET_CRS_S	  47
1660 #define	TLU_OTHER_EVENT_STATUS_SET_IIP_S	  46
1661 #define	TLU_OTHER_EVENT_STATUS_SET_EDP_S	  45
1662 #define	TLU_OTHER_EVENT_STATUS_SET_EHP_S	  44
1663 #define	TLU_OTHER_EVENT_STATUS_SET_LIN_S	  43
1664 #define	TLU_OTHER_EVENT_STATUS_SET_LRS_S	  42
1665 #define	TLU_OTHER_EVENT_STATUS_SET_LDN_S	  41
1666 #define	TLU_OTHER_EVENT_STATUS_SET_LUP_S	  40
1667 #define	TLU_OTHER_EVENT_STATUS_SET_LPU_S	38
1668 #define	TLU_OTHER_EVENT_STATUS_SET_LPU_S_MASK	0xfd
1669 #define	TLU_OTHER_EVENT_STATUS_SET_ERU_S	  37
1670 #define	TLU_OTHER_EVENT_STATUS_SET_ERO_S	  36
1671 #define	TLU_OTHER_EVENT_STATUS_SET_EMP_S	  35
1672 #define	TLU_OTHER_EVENT_STATUS_SET_EPE_S	  34
1673 #define	TLU_OTHER_EVENT_STATUS_SET_ERP_S	  33
1674 #define	TLU_OTHER_EVENT_STATUS_SET_EIP_S	  32
1675 #define	TLU_OTHER_EVENT_STATUS_SET_SPARE_P	  23
1676 #define	TLU_OTHER_EVENT_STATUS_SET_MFC_P	  22
1677 #define	TLU_OTHER_EVENT_STATUS_SET_CTO_P	  21
1678 #define	TLU_OTHER_EVENT_STATUS_SET_NFP_P	  20
1679 #define	TLU_OTHER_EVENT_STATUS_SET_LWC_P	  19
1680 #define	TLU_OTHER_EVENT_STATUS_SET_MRC_P	  18
1681 #define	TLU_OTHER_EVENT_STATUS_SET_WUC_P	  17
1682 #define	TLU_OTHER_EVENT_STATUS_SET_RUC_P	  16
1683 #define	TLU_OTHER_EVENT_STATUS_SET_CRS_P	  15
1684 #define	TLU_OTHER_EVENT_STATUS_SET_IIP_P	  14
1685 #define	TLU_OTHER_EVENT_STATUS_SET_EDP_P	  13
1686 #define	TLU_OTHER_EVENT_STATUS_SET_EHP_P	  12
1687 #define	TLU_OTHER_EVENT_STATUS_SET_LIN_P	  11
1688 #define	TLU_OTHER_EVENT_STATUS_SET_LRS_P	  10
1689 #define	TLU_OTHER_EVENT_STATUS_SET_LDN_P	  9
1690 #define	TLU_OTHER_EVENT_STATUS_SET_LUP_P	  8
1691 #define	TLU_OTHER_EVENT_STATUS_SET_LPU_P	6
1692 #define	TLU_OTHER_EVENT_STATUS_SET_LPU_P_MASK	0xfd
1693 #define	TLU_OTHER_EVENT_STATUS_SET_ERU_P	  5
1694 #define	TLU_OTHER_EVENT_STATUS_SET_ERO_P	  4
1695 #define	TLU_OTHER_EVENT_STATUS_SET_EMP_P	  3
1696 #define	TLU_OTHER_EVENT_STATUS_SET_EPE_P	  2
1697 #define	TLU_OTHER_EVENT_STATUS_SET_ERP_P	  1
1698 #define	TLU_OTHER_EVENT_STATUS_SET_EIP_P	  0
1699 #define	TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG	0x81028
1700 #define	TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG_HDR	0
1701 #define	TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG_HDR_MASK	0xffffffffffffffff
1702 #define	TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG	0x81030
1703 #define	TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG_HDR	0
1704 #define	TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG_HDR_MASK	0xffffffffffffffff
1705 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG	0x81038
1706 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG_HDR	0
1707 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG_HDR_MASK	0xffffffffffffffff
1708 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG	0x81040
1709 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG_HDR	0
1710 #define	TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG_HDR_MASK	0xffffffffffffffff
1711 
1712 /* Reserved 0x81048 - 0x81ff8 */
1713 
1714 #define	TLU_PERFORMANCE_COUNTER_SELECT	0x82000
1715 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL2	16
1716 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL2_MASK	0x3
1717 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL1	8
1718 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL1_MASK	0xff
1719 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL0	0
1720 #define	TLU_PERFORMANCE_COUNTER_SELECT_SEL0_MASK	0xff
1721 #define	TLU_PERFORMANCE_COUNTER_ZERO	0x82008
1722 #define	TLU_PERFORMANCE_COUNTER_ZERO_CNT	0
1723 #define	TLU_PERFORMANCE_COUNTER_ZERO_CNT_MASK	0xffffffffffffffff
1724 #define	TLU_PERFORMANCE_COUNTER_ONE	0x82010
1725 #define	TLU_PERFORMANCE_COUNTER_ONE_CNT	0
1726 #define	TLU_PERFORMANCE_COUNTER_ONE_CNT_MASK	0xffffffffffffffff
1727 #define	TLU_PERFORMANCE_COUNTER_TWO	0x82018
1728 #define	TLU_PERFORMANCE_COUNTER_TWO_CNT	0
1729 #define	TLU_PERFORMANCE_COUNTER_TWO_CNT_MASK	0xffffffff
1730 
1731 /* Reserved 0x82020 - 0x82ff8 */
1732 
1733 #define	TLU_DEBUG_SELECT_A	0x83000
1734 #define	TLU_DEBUG_SELECT_A_BLOCK	6
1735 #define	TLU_DEBUG_SELECT_A_BLOCK_MASK	0x7
1736 #define	TLU_DEBUG_SELECT_A_MODULE	3
1737 #define	TLU_DEBUG_SELECT_A_MODULE_MASK	0x7
1738 #define	TLU_DEBUG_SELECT_A_SIGNAL	0
1739 #define	TLU_DEBUG_SELECT_A_SIGNAL_MASK	0x7
1740 #define	TLU_DEBUG_SELECT_B	0x83008
1741 #define	TLU_DEBUG_SELECT_B_BLOCK	6
1742 #define	TLU_DEBUG_SELECT_B_BLOCK_MASK	0x7
1743 #define	TLU_DEBUG_SELECT_B_MODULE	3
1744 #define	TLU_DEBUG_SELECT_B_MODULE_MASK	0x7
1745 #define	TLU_DEBUG_SELECT_B_SIGNAL	0
1746 #define	TLU_DEBUG_SELECT_B_SIGNAL_MASK	0x7
1747 
1748 /* Reserved 0x83010 - 0x8fff8 */
1749 
1750 #define	TLU_DEVICE_CAPABILITIES	0x90000
1751 #define	TLU_DEVICE_CAPABILITIES_L1	9
1752 #define	TLU_DEVICE_CAPABILITIES_L1_MASK	0x7
1753 #define	TLU_DEVICE_CAPABILITIES_L0S	6
1754 #define	TLU_DEVICE_CAPABILITIES_L0S_MASK	0x7
1755 #define	TLU_DEVICE_CAPABILITIES_MPS	0
1756 #define	TLU_DEVICE_CAPABILITIES_MPS_MASK	0x7
1757 #define	TLU_DEVICE_CONTROL	0x90008
1758 #define	TLU_DEVICE_CONTROL_MRRS	12
1759 #define	TLU_DEVICE_CONTROL_MRRS_MASK	0x7
1760 #define	TLU_DEVICE_CONTROL_MPS	5
1761 #define	TLU_DEVICE_CONTROL_MPS_MASK	0x7
1762 #define	TLU_DEVICE_STATUS	0x90010
1763 #define	TLU_DEVICE_STATUS_TP	  5
1764 #define	TLU_LINK_CAPABILITIES	0x90018
1765 #define	TLU_LINK_CAPABILITIES_PORT	24
1766 #define	TLU_LINK_CAPABILITIES_PORT_MASK	0xff
1767 #define	TLU_LINK_CAPABILITIES_L1	15
1768 #define	TLU_LINK_CAPABILITIES_L1_MASK	0x7
1769 #define	TLU_LINK_CAPABILITIES_L0S	12
1770 #define	TLU_LINK_CAPABILITIES_L0S_MASK	0x7
1771 #define	TLU_LINK_CAPABILITIES_ASPM	10
1772 #define	TLU_LINK_CAPABILITIES_ASPM_MASK	0x3
1773 #define	TLU_LINK_CAPABILITIES_WIDTH	4
1774 #define	TLU_LINK_CAPABILITIES_WIDTH_MASK	0x3f
1775 #define	TLU_LINK_CAPABILITIES_SPEED	0
1776 #define	TLU_LINK_CAPABILITIES_SPEED_MASK	0xf
1777 #define	TLU_LINK_CONTROL	0x90020
1778 #define	TLU_LINK_CONTROL_EXTSYNC	  7
1779 #define	TLU_LINK_CONTROL_CLOCK	  6
1780 #define	TLU_LINK_CONTROL_RETRAIN	  5
1781 #define	TLU_LINK_CONTROL_DISABLE	  4
1782 #define	TLU_LINK_CONTROL_RCB	  3
1783 #define	TLU_LINK_CONTROL_ASPM	0
1784 #define	TLU_LINK_CONTROL_ASPM_MASK	0x3
1785 #define	TLU_LINK_STATUS	0x90028
1786 #define	TLU_LINK_STATUS_CLOCK	  12
1787 #define	TLU_LINK_STATUS_TRAIN	  11
1788 #define	TLU_LINK_STATUS_ERROR	  10
1789 #define	TLU_LINK_STATUS_WIDTH	4
1790 #define	TLU_LINK_STATUS_WIDTH_MASK	0x3f
1791 #define	TLU_LINK_STATUS_SPEED	0
1792 #define	TLU_LINK_STATUS_SPEED_MASK	0xf
1793 #define	TLU_SLOT_CAPABILITIES	0x90030
1794 #define	TLU_SLOT_CAPABILITIES_SPLS	15
1795 #define	TLU_SLOT_CAPABILITIES_SPLS_MASK	0x3
1796 #define	TLU_SLOT_CAPABILITIES_SPLV	7
1797 #define	TLU_SLOT_CAPABILITIES_SPLV_MASK	0xff
1798 
1799 /* Reserved 0x90038 - 0x90ff8 */
1800 
1801 #define	TLU_UNCORRECTABLE_ERROR_LOG_ENABLE	0x91000
1802 #define	TLU_UNCORRECTABLE_ERROR_LOG_ENABLE_EN	0
1803 #define	TLU_UNCORRECTABLE_ERROR_LOG_ENABLE_EN_MASK	0x1fffff
1804 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE	0x91008
1805 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_S	32
1806 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_S_MASK	0x1fffff
1807 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_P	0
1808 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_P_MASK	0x1fffff
1809 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS	0x91010
1810 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_S	32
1811 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_S_MASK	0x1fffff
1812 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_P	0
1813 #define	TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_P_MASK	0x1fffff
1814 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_UR_S		  52
1815 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_MFP_S	  50
1816 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_ROF_S	  49
1817 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_UC_S		  48
1818 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_CA_S		  47
1819 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_CTO_S	  46
1820 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_FCP_S	  45
1821 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_PP_S		  44
1822 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_DLP_S	  36
1823 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_TE_S		  32
1824 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_UR_P		  20
1825 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_MFP_P	  18
1826 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_ROF_P	  17
1827 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_UC_P		  16
1828 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_CA_P		  15
1829 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_CTO_P	  14
1830 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_FCP_P	  13
1831 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_PP_P		  12
1832 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_DLP_P	  4
1833 #define	TLU_UNCORRECTABLE_INTERRUPT_STATUS_TE_P		  0
1834 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR	0x91018
1835 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_UR_S	  52
1836 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_MFP_S	  50
1837 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ROF_S	  49
1838 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_UC_S	  48
1839 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_CA_S	  47
1840 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_CTO_S	  46
1841 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_FCP_S	  45
1842 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_PP_S	  44
1843 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_DLP_S	  36
1844 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_TE_S	  32
1845 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_UR_P	  20
1846 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_MFP_P	  18
1847 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ROF_P	  17
1848 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_UC_P	  16
1849 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_CA_P	  15
1850 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_CTO_P	  14
1851 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_FCP_P	  13
1852 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_PP_P	  12
1853 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_DLP_P	  4
1854 #define	TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_TE_P	  0
1855 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET	0x91020
1856 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_UR_S	  52
1857 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_MFP_S	  50
1858 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_ROF_S	  49
1859 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_UC_S	  48
1860 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_CA_S	  47
1861 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_CTO_S	  46
1862 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_FCP_S	  45
1863 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_PP_S	  44
1864 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_DLP_S	  36
1865 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_TE_S	  32
1866 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_UR_P	  20
1867 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_MFP_P	  18
1868 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_ROF_P	  17
1869 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_UC_P	  16
1870 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_CA_P	  15
1871 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_CTO_P	  14
1872 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_FCP_P	  13
1873 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_PP_P	  12
1874 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_DLP_P	  4
1875 #define	TLU_UNCORRECTABLE_ERROR_STATUS_SET_TE_P	  0
1876 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG	0x91028
1877 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG_HDR	0
1878 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG_HDR_MASK \
1879 	0xffffffffffffffff
1880 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG	0x91030
1881 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG_HDR	0
1882 #define	TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG_HDR_MASK \
1883 	0xffffffffffffffff
1884 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG	0x91038
1885 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG_HDR	0
1886 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG_HDR_MASK \
1887 	0xffffffffffffffff
1888 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG	0x91040
1889 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG_HDR	0
1890 #define	TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG_HDR_MASK \
1891 	0xffffffffffffffff
1892 
1893 /* Reserved 0x91048 - 0x9fff8 */
1894 
1895 
1896 /* Reserved 0xa0008 - 0xa0ff8 */
1897 
1898 #define	TLU_CORRECTABLE_ERROR_LOG_ENABLE	0xa1000
1899 #define	TLU_CORRECTABLE_ERROR_LOG_ENABLE_EN	0
1900 #define	TLU_CORRECTABLE_ERROR_LOG_ENABLE_EN_MASK	0x1fff
1901 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE	0xa1008
1902 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_S	32
1903 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_S_MASK	0x1fff
1904 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_P	0
1905 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE_EN_P_MASK	0x1fff
1906 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS	0xa1010
1907 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_S	32
1908 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_S_MASK	0x1fff
1909 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_P	0
1910 #define	TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS_ERR_P_MASK	0x1fff
1911 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR	0xa1018
1912 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RTO_S	  44
1913 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RNR_S	  40
1914 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_BDP_S	  39
1915 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_BTP_S	  38
1916 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RE_S	  32
1917 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RTO_P	  12
1918 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RNR_P	  8
1919 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_BDP_P	  7
1920 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_BTP_P	  6
1921 #define	TLU_CORRECTABLE_ERROR_STATUS_CLEAR_RE_P	  0
1922 #define	TLU_CORRECTABLE_ERROR_STATUS_SET	0xa1020
1923 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RTO_S	  44
1924 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RNR_S	  40
1925 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_BDP_S	  39
1926 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_BTP_S	  38
1927 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RE_S	  32
1928 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RTO_P	  12
1929 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RNR_P	  8
1930 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_BDP_P	  7
1931 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_BTP_P	  6
1932 #define	TLU_CORRECTABLE_ERROR_STATUS_SET_RE_P	  0
1933 
1934 /* lpr.csr  LPR module defines */
1935 
1936 #define	LPR_CSR_BASE	0x600000
1937 
1938 /* Reserved 0xe0008 - 0xe1ff8 */
1939 
1940 #define	LPU_ID	0xe2000
1941 #define	LPU_ID_LTBWDTH	20
1942 #define	LPU_ID_LTBWDTH_MASK	0xf
1943 #define	LPU_ID_PTLWDTH	16
1944 #define	LPU_ID_PTLWDTH_MASK	0xf
1945 #define	LPU_ID_TRID	12
1946 #define	LPU_ID_TRID_MASK	0xf
1947 #define	LPU_ID_LNKID	8
1948 #define	LPU_ID_LNKID_MASK	0xf
1949 #define	LPU_ID_PHYID	4
1950 #define	LPU_ID_PHYID_MASK	0xf
1951 #define	LPU_ID_GBID	0
1952 #define	LPU_ID_GBID_MASK	0xf
1953 #define	LPU_RESET	0xe2008
1954 #define	LPU_RESET_RSTWE	  31
1955 #define	LPU_RESET_RSTUNUSED	9
1956 #define	LPU_RESET_RSTUNUSED_MASK	0x7
1957 #define	LPU_RESET_RSTERROR	  8
1958 #define	LPU_RESET_RSTTXLINK	  7
1959 #define	LPU_RESET_RSTRXLINK	  6
1960 #define	LPU_RESET_RSTSMLINK	  5
1961 #define	LPU_RESET_RSTLTSSM	  4
1962 #define	LPU_RESET_RSTTXPHY	  3
1963 #define	LPU_RESET_RSTRXPHY	  2
1964 #define	LPU_RESET_RSTTXPCS	  1
1965 #define	LPU_RESET_RSTRXPCS	  0
1966 #define	LPU_DEBUG_STATUS	0xe2010
1967 #define	LPU_DEBUG_STATUS_DEBUGB	8
1968 #define	LPU_DEBUG_STATUS_DEBUGB_MASK	0xff
1969 #define	LPU_DEBUG_STATUS_DEBUGA	0
1970 #define	LPU_DEBUG_STATUS_DEBUGA_MASK	0xff
1971 #define	LPU_DEBUG_CONFIG	0xe2018
1972 #define	LPU_DEBUG_CONFIG_DBUGB_BLK_SEL	24
1973 #define	LPU_DEBUG_CONFIG_DBUGB_BLK_SEL_MASK	0xff
1974 #define	LPU_DEBUG_CONFIG_DBUGB_SIG_SEL	16
1975 #define	LPU_DEBUG_CONFIG_DBUGB_SIG_SEL_MASK	0xff
1976 #define	LPU_DEBUG_CONFIG_DBUGA_BLK_SEL	8
1977 #define	LPU_DEBUG_CONFIG_DBUGA_BLK_SEL_MASK	0xff
1978 #define	LPU_DEBUG_CONFIG_DBUGA_SIG_SEL	0
1979 #define	LPU_DEBUG_CONFIG_DBUGA_SIG_SEL_MASK	0xff
1980 #define	LPU_LTSSM_CONTROL	0xe2020
1981 #define	LPU_LTSSM_CONTROL_WR_ENABLE	  31
1982 #define	LPU_LTSSM_CONTROL_RCOVER_TO_CONFIG	  11
1983 #define	LPU_LTSSM_CONTROL_L0_TO_RECOVER	  10
1984 #define	LPU_LTSSM_CONTROL_UNUSED_0	  9
1985 #define	LPU_LTSSM_CONTROL_GO_TO_DETECT	  8
1986 #define	LPU_LTSSM_CONTROL_UNUSED_1	4
1987 #define	LPU_LTSSM_CONTROL_UNUSED_1_MASK	0xf
1988 #define	LPU_LTSSM_CONTROL_DISABLE_SCRAMBLING	  3
1989 #define	LPU_LTSSM_CONTROL_LINK_LOOPBK_REQ	  2
1990 #define	LPU_LTSSM_CONTROL_LINK_DISABLE_REQ	  1
1991 #define	LPU_LTSSM_CONTROL_HOT_RESET	  0
1992 #define	LPU_LINK_STATUS	0xe2028
1993 #define	LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN	  12
1994 #define	LPU_LINK_STATUS_LINK_TRAINING	  11
1995 #define	LPU_LINK_STATUS_LINK_TRAINING_ERR	  10
1996 #define	LPU_LINK_STATUS_NEGOTIATED_WIDTH	4
1997 #define	LPU_LINK_STATUS_NEGOTIATED_WIDTH_MASK	0x3f
1998 #define	LPU_LINK_STATUS_LINK_SPEED	0
1999 #define	LPU_LINK_STATUS_LINK_SPEED_MASK	0xf
2000 
2001 /* Reserved 0xe2030 - 0xe2038 */
2002 
2003 #define	LPU_INTERRUPT_STATUS	0xe2040
2004 #define	LPU_INTERRUPT_STATUS_INTERRUPT	  31
2005 #define	LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW	  7
2006 #define	LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW	  6
2007 #define	LPU_INTERRUPT_STATUS_INT_LINK_LAYER	  5
2008 #define	LPU_INTERRUPT_STATUS_INT_PHY_ERROR	  4
2009 #define	LPU_INTERRUPT_STATUS_INT_LTSSM	  3
2010 #define	LPU_INTERRUPT_STATUS_INT_PHY_TX	  2
2011 #define	LPU_INTERRUPT_STATUS_INT_PHY_RX	  1
2012 #define	LPU_INTERRUPT_STATUS_INT_PHY_GB	  0
2013 #define	LPU_INTERRUPT_MASK	0xe2048
2014 #define	LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN	  31
2015 #define	LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW	  7
2016 #define	LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW	  6
2017 #define	LPU_INTERRUPT_MASK_MSK_LINK_LAYER	  5
2018 #define	LPU_INTERRUPT_MASK_MSK_PHY_ERROR	  4
2019 #define	LPU_INTERRUPT_MASK_MSK_LTSSM	  3
2020 #define	LPU_INTERRUPT_MASK_MSK_PHY_TX	  2
2021 #define	LPU_INTERRUPT_MASK_MSK_PHY_RX	  1
2022 #define	LPU_INTERRUPT_MASK_MSK_PHY_GB	  0
2023 
2024 /* Reserved 0xe2050 - 0xe20f8 */
2025 
2026 #define	LPU_LINK_PERFORMANCE_COUNTER_SELECT	0xe2100
2027 #define	LPU_LINK_PERFORMANCE_COUNTER_SELECT_PERF_CNTR2_SELECT	16
2028 #define	LPU_LINK_PERFORMANCE_COUNTER_SELECT_PERF_CNTR2_SELECT_MASK	0xffff
2029 #define	LPU_LINK_PERFORMANCE_COUNTER_SELECT_PERF_CNTR1_SELECT	0
2030 #define	LPU_LINK_PERFORMANCE_COUNTER_SELECT_PERF_CNTR1_SELECT_MASK	0xffff
2031 
2032 /* Reserved 0xe2108 - 0xe2108 */
2033 
2034 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL	0xe2110
2035 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_SET_PERF_CNTR2_OVERFLOW	  6
2036 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_SET_PERF_CNTR1_OVERFLOW	  5
2037 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_RST_PERF_CNTR2_OVERFLOW	  3
2038 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_RST_PERF_CNTR2	  2
2039 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_RST_PERF_CNTR1_OVERFLOW	  1
2040 #define	LPU_LINK_PERFORMANCE_COUNTER_CONTROL_RST_PERF_CNTR1	  0
2041 
2042 /* Reserved 0xe2118 - 0xe2118 */
2043 
2044 #define	LPU_LINK_PERFORMANCE_COUNTER1	0xe2120
2045 #define	LPU_LINK_PERFORMANCE_COUNTER1_PERF_CNTR1	0
2046 #define	LPU_LINK_PERFORMANCE_COUNTER1_PERF_CNTR1_MASK	0xffffffff
2047 #define	LPU_LINK_PERFORMANCE_COUNTER1_TEST	0xe2128
2048 #define	LPU_LINK_PERFORMANCE_COUNTER1_TEST_PERF_CNTR1_TEST	0
2049 #define	LPU_LINK_PERFORMANCE_COUNTER1_TEST_PERF_CNTR1_TEST_MASK	0xffffffff
2050 #define	LPU_LINK_PERFORMANCE_COUNTER2	0xe2130
2051 #define	LPU_LINK_PERFORMANCE_COUNTER2_PERF_CNTR2	0
2052 #define	LPU_LINK_PERFORMANCE_COUNTER2_PERF_CNTR2_MASK	0xffffffff
2053 #define	LPU_LINK_PERFORMANCE_COUNTER2_TEST	0xe2138
2054 #define	LPU_LINK_PERFORMANCE_COUNTER2_TEST_PERF_CNTR2_TEST	0
2055 #define	LPU_LINK_PERFORMANCE_COUNTER2_TEST_PERF_CNTR2_TEST_MASK	0xffffffff
2056 
2057 /* Reserved 0xe2140 - 0xe21f8 */
2058 
2059 #define	LPU_LINK_LAYER_CONFIG	0xe2200
2060 #define	LPU_LINK_LAYER_CONFIG_AUTO_UPDATE_DIS	  19
2061 #define	LPU_LINK_LAYER_CONFIG_FREQ_NAK_EN	  18
2062 #define	LPU_LINK_LAYER_CONFIG_REPLAY_AFTER_REC	  17
2063 #define	LPU_LINK_LAYER_CONFIG_LAT_THRES_WR_EN	  16
2064 #define	LPU_LINK_LAYER_CONFIG_VC0_EN	  8
2065 #define	LPU_LINK_LAYER_CONFIG_UNUSED	5
2066 #define	LPU_LINK_LAYER_CONFIG_UNUSED_MASK	0x7
2067 #define	LPU_LINK_LAYER_CONFIG_L0S_ADJ_FAC_EN	  4
2068 #define	LPU_LINK_LAYER_CONFIG_TLP_XMIT_FC_EN	  3
2069 #define	LPU_LINK_LAYER_CONFIG_FREQ_ACK_ENABLE	  2
2070 #define	LPU_LINK_LAYER_CONFIG_RETRY_DISABLE	  1
2071 #define	LPU_LINK_LAYER_STATUS	0xe2208
2072 #define	LPU_LINK_LAYER_STATUS_INIT_FC_SM_WE	  9
2073 #define	LPU_LINK_LAYER_STATUS_LNK_ST_DLUP_WE	  8
2074 #define	LPU_LINK_LAYER_STATUS_INIT_FC_SM_STS	4
2075 #define	LPU_LINK_LAYER_STATUS_INIT_FC_SM_STS_MASK	0x3
2076 #define	LPU_LINK_LAYER_STATUS_DLUP_STS	  3
2077 #define	LPU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS	0
2078 #define	LPU_LINK_LAYER_STATUS_LNK_STATE_MACH_STS_MASK	0x7
2079 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS	0xe2210
2080 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_LINK_ERR_ACT	  31
2081 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_UNSPRTD_DLLP	  22
2082 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_DLLP_RCV_ERR	  21
2083 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_BAD_DLLP	  20
2084 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_TLP_RCV_ERR	  18
2085 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_SRC_ERR_TLP	  17
2086 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_BAD_TLP	  16
2087 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_RTRY_BUF_UDF_ERR	  9
2088 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_RTRY_BUF_OVF_ERR	  8
2089 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_EG_TLP_MIN_ERR	  7
2090 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_EG_TRNC_FRM_ERR	  6
2091 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_RTRY_BUF_PE	  5
2092 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_EGRESS_PE	  4
2093 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_RPLAY_TMR_TO	  2
2094 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_RPLAY_NUM_RO	  1
2095 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_DLNK_PES	  0
2096 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST	0xe2218
2097 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_UNSPRTD_DLLP	  22
2098 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_DLLP_RCV_ERR	  21
2099 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_BAD_DLLP	  20
2100 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_TLP_RCV_ERR	  18
2101 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_SRC_ERR_TLP	  17
2102 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_BAD_TLP	  16
2103 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_RTRY_BUF_UDF_ERR	  9
2104 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_RTRY_BUF_OVF	  8
2105 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_EG_TLP_MIN_ERR	  7
2106 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_EG_TRNC_FRM_ERR	  6
2107 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_RTRY_BUF_PE	  5
2108 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_EGRESS_PE	  4
2109 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_RPLAY_TMR_TO	  2
2110 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_RPLAY_NUM_RO	  1
2111 #define	LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST_TST_DLNK_PES	  0
2112 #define	LPU_LINK_LAYER_INTERRUPT_MASK	0xe2220
2113 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_LINK_ERR_ACT	  31
2114 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_UNSPRTD_DLLP	  22
2115 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_DLLP_RCV_ERR	  21
2116 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_BAD_DLLP	  20
2117 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_UNUSED_2	  19
2118 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_TLP_RCV_ERR	  18
2119 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_SRC_ERR_TLP	  17
2120 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_BAD_TLP	  16
2121 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_UNUSED_1	10
2122 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_UNUSED_1_MASK	0x3f
2123 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_RTRY_UNF_OVF	  9
2124 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_RTRY_BUF_OVF	  8
2125 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_EG_TLP_MIN_ERR	  7
2126 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_EG_TRNC_FRM_ERR	  6
2127 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_RTRY_BUF_PE	  5
2128 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_EGRESS_PE	  4
2129 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_UNUSED_0	  3
2130 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_RPLAY_TMR_TO	  2
2131 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_RPLAY_NUM_RO	  1
2132 #define	LPU_LINK_LAYER_INTERRUPT_MASK_MSK_DLNK_PES	  0
2133 
2134 /* Reserved 0xe2228 - 0xe2238 */
2135 
2136 #define	LPU_FLOW_CONTROL_UPDATE_CONTROL	0xe2240
2137 #define	LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_C_EN	  2
2138 #define	LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN	  1
2139 #define	LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN	  0
2140 
2141 /* Reserved 0xe2248 - 0xe2258 */
2142 
2143 #define	LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE	0xe2260
2144 #define	LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE_FC_UPDATE_TO	0
2145 #define	LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE_FC_UPDATE_TO_MASK \
2146 	0x7fff
2147 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0	0xe2268
2148 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0_VC0_FC_UP_TMR_NP	16
2149 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0_VC0_FC_UP_TMR_NP_MASK \
2150 	0x7fff
2151 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0_VC0_FC_UP_TMR_P	0
2152 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0_VC0_FC_UP_TMR_P_MASK \
2153 	0x7fff
2154 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1	0xe2270
2155 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1_VC0_FC_UP_TMR_CPL	0
2156 #define	LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1_VC0_FC_UP_TMR_CPL_MASK \
2157 	0x7fff
2158 
2159 /* Reserved 0xe2278 - 0xe23f8 */
2160 
2161 #define	LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD	0xe2400
2162 #define	LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD_ACK_NAK_THR	0
2163 #define	LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD_ACK_NAK_THR_MASK \
2164 	0xffff
2165 #define	LPU_TXLINK_ACKNAK_LATENCY_TIMER	0xe2408
2166 #define	LPU_TXLINK_ACKNAK_LATENCY_TIMER_ACK_NAK_TMR	0
2167 #define	LPU_TXLINK_ACKNAK_LATENCY_TIMER_ACK_NAK_TMR_MASK	0xffff
2168 #define	LPU_TXLINK_REPLAY_TIMER_THRESHOLD	0xe2410
2169 #define	LPU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR	0
2170 #define	LPU_TXLINK_REPLAY_TIMER_THRESHOLD_RPLAY_TMR_THR_MASK	0xfffff
2171 #define	LPU_TXLINK_REPLAY_TIMER	0xe2418
2172 #define	LPU_TXLINK_REPLAY_TIMER_RPLAY_TMR	0
2173 #define	LPU_TXLINK_REPLAY_TIMER_RPLAY_TMR_MASK	0xfffff
2174 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS	0xe2420
2175 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_WE	  31
2176 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_CNTR	0
2177 #define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_CNTR_MASK	0x3
2178 #define	LPU_REPLAY_BUFFER_MAX_ADDRESS	0xe2428
2179 #define	LPU_REPLAY_BUFFER_MAX_ADDRESS_RTRY_BUFF_MAX_ADDR	0
2180 #define	LPU_REPLAY_BUFFER_MAX_ADDRESS_RTRY_BUFF_MAX_ADDR_MASK	0xffff
2181 #define	LPU_TXLINK_RETRY_FIFO_POINTER	0xe2430
2182 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR	16
2183 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_MASK	0xffff
2184 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR	0
2185 #define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_MASK	0xffff
2186 #define	LPU_TXLINK_RETRY_FIFO_R_W_POINTER	0xe2438
2187 #define	LPU_TXLINK_RETRY_FIFO_R_W_POINTER_RTRY_BFFR_WRPTR	16
2188 #define	LPU_TXLINK_RETRY_FIFO_R_W_POINTER_RTRY_BFFR_WRPTR_MASK	0xffff
2189 #define	LPU_TXLINK_RETRY_FIFO_R_W_POINTER_RTRY_BFFR_RDPTR	0
2190 #define	LPU_TXLINK_RETRY_FIFO_R_W_POINTER_RTRY_BFFR_RDPTR_MASK	0xffff
2191 #define	LPU_TXLINK_RETRY_FIFO_CREDIT	0xe2440
2192 #define	LPU_TXLINK_RETRY_FIFO_CREDIT_RTRY_FIFO_CRDT	0
2193 #define	LPU_TXLINK_RETRY_FIFO_CREDIT_RTRY_FIFO_CRDT_MASK	0xffff
2194 #define	LPU_TXLINK_SEQUENCE_COUNTER	0xe2448
2195 #define	LPU_TXLINK_SEQUENCE_COUNTER_WE	  31
2196 #define	LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_WE	  30
2197 #define	LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR	16
2198 #define	LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_MASK	0xfff
2199 #define	LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR	0
2200 #define	LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_MASK	0xfff
2201 #define	LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER	0xe2450
2202 #define	LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER_SEQ_NUM	0
2203 #define	LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER_SEQ_NUM_MASK	0xfff
2204 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR	0xe2458
2205 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR	0
2206 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_MASK	0xfff
2207 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS	0xe2460
2208 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR	16
2209 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_MASK	0xfff
2210 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR	0
2211 #define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_MASK	0xfff
2212 #define	LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS	0xe2468
2213 #define	LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS_SEQ_CNT_WRPTR	16
2214 #define	LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS_SEQ_CNT_WRPTR_MASK	0xfff
2215 #define	LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS_SEQ_CNT_RDPTR	0
2216 #define	LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS_SEQ_CNT_RDPTR_MASK	0xfff
2217 #define	LPU_TXLINK_TEST_CONTROL	0xe2470
2218 #define	LPU_TXLINK_TEST_CONTROL_DIS_ACK	  3
2219 #define	LPU_TXLINK_TEST_CONTROL_FORCE_NAK	  2
2220 #define	LPU_TXLINK_TEST_CONTROL_FORCE_BAD_TLP_CRC	  1
2221 #define	LPU_TXLINK_TEST_CONTROL_FORCE_RTX_TLP	  0
2222 
2223 /* Reserved 0xe2478 - 0xe2478 */
2224 
2225 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL	0xe2480
2226 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_DONE	  31
2227 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_GO_BIT	  30
2228 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_RD_WR_SEL	  29
2229 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_FIFO_SEL	  28
2230 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_MEM_ADDR	0
2231 #define	LPU_TXLINK_MEMORY_ADDRESS_CONTROL_MEM_ADDR_MASK	0xffff
2232 #define	LPU_TXLINK_MEMORY_DATA_LOAD0	0xe2488
2233 #define	LPU_TXLINK_MEMORY_DATA_LOAD0_MEM_RD_WR_DATA0	0
2234 #define	LPU_TXLINK_MEMORY_DATA_LOAD0_MEM_RD_WR_DATA0_MASK	0xffffffff
2235 #define	LPU_TXLINK_MEMORY_DATA_LOAD1	0xe2490
2236 #define	LPU_TXLINK_MEMORY_DATA_LOAD1_MEM_RD_WR_DATA1	0
2237 #define	LPU_TXLINK_MEMORY_DATA_LOAD1_MEM_RD_WR_DATA1_MASK	0xffffffff
2238 #define	LPU_TXLINK_MEMORY_DATA_LOAD2	0xe2498
2239 #define	LPU_TXLINK_MEMORY_DATA_LOAD3	0xe24a0
2240 #define	LPU_TXLINK_MEMORY_DATA_LOAD4	0xe24a8
2241 #define	LPU_TXLINK_MEMORY_DATA_LOAD4_MEM_RD_WR_DATA4	0
2242 #define	LPU_TXLINK_MEMORY_DATA_LOAD4_MEM_RD_WR_DATA4_MASK	0xff
2243 
2244 /* Reserved 0xe24b0 - 0xe24b8 */
2245 
2246 #define	LPU_TXLINK_RETRY_DATA_COUNT	0xe24c0
2247 #define	LPU_TXLINK_RETRY_DATA_COUNT_RTRY_DATA_CNT	0
2248 #define	LPU_TXLINK_RETRY_DATA_COUNT_RTRY_DATA_CNT_MASK	0xffff
2249 #define	LPU_TXLINK_SEQUENCE_BUFFER_COUNT	0xe24c8
2250 #define	LPU_TXLINK_SEQUENCE_BUFFER_COUNT_SEQ_BUFF_CNT	0
2251 #define	LPU_TXLINK_SEQUENCE_BUFFER_COUNT_SEQ_BUFF_CNT_MASK	0xfff
2252 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA	0xe24d0
2253 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBUF_BDATA_PAR	  30
2254 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_SEQ_NUM	18
2255 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_SEQ_NUM_MASK	0xfff
2256 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_RTRY_PTR	2
2257 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_RTRY_PTR_MASK	0xffff
2258 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_EOP_POS	0
2259 #define	LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA_SBDATA_EOP_POS_MASK	0x3
2260 
2261 /* Reserved 0xe24d8 - 0xe24d8 */
2262 
2263 #define	LPU_TXLINK_ACK_LATENCY_TIMER_THRESHOLD	0xe24e0
2264 #define	LPU_TXLINK_ACK_LATENCY_TIMER_THRESHOLD_ACK_LAT_THHOLD	0
2265 #define	LPU_TXLINK_ACK_LATENCY_TIMER_THRESHOLD_ACK_LAT_THHOLD_MASK	0xffff
2266 
2267 /* Reserved 0xe24e8 - 0xe24f8 */
2268 
2269 #define	LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER	0xe2500
2270 #define	LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER_NXT_RX_SEQ_CNTR	0
2271 #define	LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER_NXT_RX_SEQ_CNTR_MASK \
2272 	0xfff
2273 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED	0xe2508
2274 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE3	24
2275 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE3_MASK	0xff
2276 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE2	16
2277 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE2_MASK	0xff
2278 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE1	8
2279 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE1_MASK	0xff
2280 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE0	0
2281 #define	LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED_BYTE0_MASK	0xff
2282 #define	LPU_RXLINK_TEST_CONTROL	0xe2510
2283 #define	LPU_RXLINK_TEST_CONTROL_FORCE_SEND_INIT_FC_DLLP	  1
2284 #define	LPU_RXLINK_TEST_CONTROL_FORCE_PAR_ERR_DLLP	  0
2285 
2286 /* Reserved 0xe2518 - 0xe25f8 */
2287 
2288 #define	LPU_PHYSICAL_LAYER_CONFIGURATION	0xe2600
2289 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_PHY_TST_EN	  31
2290 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_FAST_SIM	  30
2291 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_UNUSED	  29
2292 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_FRCE_EXTEN_SYNC	  28
2293 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_EIDLE_POST_EN	  11
2294 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_POST_VAL	8
2295 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_POST_VAL_MASK	0x7
2296 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_BYTE_SEL	  7
2297 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_PREAM_VAL	4
2298 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_OS_PREAM_VAL_MASK	0x7
2299 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_RDET_BYP_MODE	  3
2300 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_RDET_SAFE_MODE	  2
2301 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_UNUSED	  1
2302 #define	LPU_PHYSICAL_LAYER_CONFIGURATION_TX_PAR_ERR	  0
2303 #define	LPU_PHY_LAYER_STATUS	0xe2608
2304 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS	0xe2610
2305 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_PHY_LAYER_ERR	  31
2306 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_KCHAR_DLLP_ERR	  11
2307 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ILL_END_POS_ERR	  10
2308 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_LNK_ERR	  9
2309 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_TRN_ERR	  8
2310 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_EDB_DET	  7
2311 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_SDP_END	  6
2312 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_STP_END_EDB	  5
2313 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_INVLD_CHAR_ERR	  4
2314 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_MULTI_SDP	  3
2315 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_MULTI_STP	  2
2316 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ILL_SDP_POS	  1
2317 #define	LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ILL_STP_POS	  0
2318 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST	0xe2618
2319 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_KCHAR_DLLP_ERR	  11
2320 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_ILL_END_POS_ERR	  10
2321 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_LNK_ERR	  9
2322 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_TRN_ERR	  8
2323 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_EDB_DET	  7
2324 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_SDP_END	  6
2325 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_STP_END_EDB	  5
2326 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_INVLD_CHAR_ERR	  4
2327 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_MULTI_SDP	  3
2328 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_MULTI_STP	  2
2329 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_ILL_SDP_POS	  1
2330 #define	LPU_PHY_INTERRUPT_AND_STATUS_TEST_TST_ILL_STP_POS	  0
2331 #define	LPU_PHY_INTERRUPT_MASK	0xe2620
2332 #define	LPU_PHY_INTERRUPT_MASK_MSK_PHY_LAYER_ERR	  31
2333 #define	LPU_PHY_INTERRUPT_MASK_MSK_KCHAR_DLLP_ERR	  11
2334 #define	LPU_PHY_INTERRUPT_MASK_MSK_ILL_END_POS_ERR	  10
2335 #define	LPU_PHY_INTERRUPT_MASK_MSK_LNK_ERR	  9
2336 #define	LPU_PHY_INTERRUPT_MASK_MSK_TRN_ERR	  8
2337 #define	LPU_PHY_INTERRUPT_MASK_MSK_EDB_DET	  7
2338 #define	LPU_PHY_INTERRUPT_MASK_MSK_SDP_END	  6
2339 #define	LPU_PHY_INTERRUPT_MASK_MSK_STP_END_EDB	  5
2340 #define	LPU_PHY_INTERRUPT_MASK_MSK_INVLD_CHAR_ERR	  4
2341 #define	LPU_PHY_INTERRUPT_MASK_MSK_MULTI_SDP	  3
2342 #define	LPU_PHY_INTERRUPT_MASK_MSK_MULTI_STP	  2
2343 #define	LPU_PHY_INTERRUPT_MASK_MSK_ILL_SDP_POS	  1
2344 #define	LPU_PHY_INTERRUPT_MASK_MSK_ILL_STP_POS	  0
2345 
2346 /* Reserved 0xe2628 - 0xe2678 */
2347 
2348 #define	LPU_RECEIVE_PHY_CONFIG	0xe2680
2349 #define	LPU_RECEIVE_PHY_CONFIG_RX_PHY_TST	  31
2350 #define	LPU_RECEIVE_PHY_CONFIG_UNUSED_0	18
2351 #define	LPU_RECEIVE_PHY_CONFIG_UNUSED_0_MASK	0x1fff
2352 #define	LPU_RECEIVE_PHY_CONFIG_WM_SEL_FIFO	16
2353 #define	LPU_RECEIVE_PHY_CONFIG_WM_SEL_FIFO_MASK	0x3
2354 #define	LPU_RECEIVE_PHY_CONFIG_UNUSED_1	8
2355 #define	LPU_RECEIVE_PHY_CONFIG_UNUSED_1_MASK	0xff
2356 #define	LPU_RECEIVE_PHY_CONFIG_RST_RCV_LANE	0
2357 #define	LPU_RECEIVE_PHY_CONFIG_RST_RCV_LANE_MASK	0xff
2358 #define	LPU_RECEIVE_PHY_STATUS1	0xe2688
2359 #define	LPU_RECEIVE_PHY_STATUS1_ALIGN_STS	  16
2360 #define	LPU_RECEIVE_PHY_STATUS1_RX_PHY_STS	0
2361 #define	LPU_RECEIVE_PHY_STATUS1_RX_PHY_STS_MASK	0xffff
2362 #define	LPU_RECEIVE_PHY_STATUS2	0xe2690
2363 #define	LPU_RECEIVE_PHY_STATUS2_RCV_DIS_SCRAM	  27
2364 #define	LPU_RECEIVE_PHY_STATUS2_RCV_EN_LOOPBACK	  26
2365 #define	LPU_RECEIVE_PHY_STATUS2_RCV_DIS_LINK	  25
2366 #define	LPU_RECEIVE_PHY_STATUS2_RCV_HOT_RST	  24
2367 #define	LPU_RECEIVE_PHY_STATUS2_RCV_DATA_RATE	16
2368 #define	LPU_RECEIVE_PHY_STATUS2_RCV_DATA_RATE_MASK	0xff
2369 #define	LPU_RECEIVE_PHY_STATUS2_RCV_FTS_NUM	8
2370 #define	LPU_RECEIVE_PHY_STATUS2_RCV_FTS_NUM_MASK	0xff
2371 #define	LPU_RECEIVE_PHY_STATUS2_RCV_LINK_NUM	0
2372 #define	LPU_RECEIVE_PHY_STATUS2_RCV_LINK_NUM_MASK	0xff
2373 #define	LPU_RECEIVE_PHY_STATUS3	0xe2698
2374 #define	LPU_RECEIVE_PHY_STATUS3_POL_REV_STS	16
2375 #define	LPU_RECEIVE_PHY_STATUS3_POL_REV_STS_MASK	0xff
2376 #define	LPU_RECEIVE_PHY_STATUS3_BYTE_SYNC_STS	0
2377 #define	LPU_RECEIVE_PHY_STATUS3_BYTE_SYNC_STS_MASK	0xff
2378 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS	0xe26a0
2379 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_RCV_PHY	  31
2380 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_UNUSED	3
2381 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_UNUSED_MASK	0x1ff
2382 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ALIGN_ERR	  2
2383 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ELSTC_FIFO_OVRFLW	  1
2384 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ELSTC_FIFO_UNDRFLW	  0
2385 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST	0xe26a8
2386 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST_TST_UNUSED	3
2387 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST_TST_UNUSED_MASK	0x1ff
2388 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST_TST_ALIGN_ERR	  2
2389 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST_TST_ELSTC_FIFO_OVRFLW	  1
2390 #define	LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST_TST_ELSTC_FIFO_UNDRFLW  0
2391 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK	0xe26b0
2392 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_RCV_PHY_INT	  31
2393 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_UNUSED	3
2394 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_UNUSED_MASK	0x1ff
2395 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_ALIGN_ERR	  2
2396 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_ELSTC_FIFO_OVRFLW	  1
2397 #define	LPU_RECEIVE_PHY_INTERRUPT_MASK_MSK_ELSTC_FIFO_UNDRFLW	  0
2398 
2399 /* Reserved 0xe26b8 - 0xe26f8 */
2400 
2401 #define	LPU_TRANSMIT_PHY_CONFIG	0xe2700
2402 #define	LPU_TRANSMIT_PHY_CONFIG_FRCE_RCVR_DET	16
2403 #define	LPU_TRANSMIT_PHY_CONFIG_FRCE_RCVR_DET_MASK	0xffff
2404 #define	LPU_TRANSMIT_PHY_CONFIG_FRCE_ELEC_IDLE	0
2405 #define	LPU_TRANSMIT_PHY_CONFIG_FRCE_ELEC_IDLE_MASK	0xffff
2406 #define	LPU_TRANSMIT_PHY_STATUS	0xe2708
2407 #define	LPU_TRANSMIT_PHY_STATUS_NEG_LANE_WDTH	28
2408 #define	LPU_TRANSMIT_PHY_STATUS_NEG_LANE_WDTH_MASK	0xf
2409 #define	LPU_TRANSMIT_PHY_STATUS_TXPHY_SCRAM_EN	  27
2410 #define	LPU_TRANSMIT_PHY_STATUS_TX_LANE_REV	  26
2411 #define	LPU_TRANSMIT_PHY_STATUS_TX_LANE_PAD	  25
2412 #define	LPU_TRANSMIT_PHY_STATUS_TX_LINK_PAD	  24
2413 #define	LPU_TRANSMIT_PHY_STATUS_TX_PHY_SMS	0
2414 #define	LPU_TRANSMIT_PHY_STATUS_TX_PHY_SMS_MASK	0x7fffff
2415 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS	0xe2710
2416 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_UNMSK	  31
2417 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_RCV_IDLE	  11
2418 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_RCV_TS2	  10
2419 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_RCV_TS1	  9
2420 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_SKP_ERR	  8
2421 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_SKP_DONE_BK2BK	  7
2422 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_SKP_ACK_DECR	  6
2423 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_SKP_DONE_DECR	  5
2424 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_SKP_TRIG	  4
2425 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_UNUSED_2	2
2426 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_UNUSED_2_MASK	0x3
2427 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_RCVR_DET_VALID	  1
2428 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_TX_PAR_ERR	  0
2429 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST	0xe2718
2430 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST_TST_TX_PHY_INT	0
2431 #define	LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST_TST_TX_PHY_INT_MASK	0xfff
2432 #define	LPU_TRANSMIT_PHY_INTERRUPT_MASK	0xe2720
2433 #define	LPU_TRANSMIT_PHY_INTERRUPT_MASK_MSK_GLOBL_INT	  31
2434 #define	LPU_TRANSMIT_PHY_INTERRUPT_MASK_MSK_IMPLEM_INT	0
2435 #define	LPU_TRANSMIT_PHY_INTERRUPT_MASK_MSK_IMPLEM_INT_MASK	0xfff
2436 #define	LPU_TRANSMIT_PHY_STATUS_2	0xe2728
2437 #define	LPU_TRANSMIT_PHY_STATUS_2_RECV_DET_STS	16
2438 #define	LPU_TRANSMIT_PHY_STATUS_2_RECV_DET_STS_MASK	0xffff
2439 #define	LPU_TRANSMIT_PHY_STATUS_2_RECV_DET_RAW_STS	0
2440 #define	LPU_TRANSMIT_PHY_STATUS_2_RECV_DET_RAW_STS_MASK	0xffff
2441 
2442 /* Reserved 0xe2730 - 0xe2778 */
2443 
2444 #define	LPU_LTSSM_CONFIG1	0xe2780
2445 #define	LPU_LTSSM_CONFIG1_LTSSM_TST	  31
2446 #define	LPU_LTSSM_CONFIG1_CFG_UNUSED	18
2447 #define	LPU_LTSSM_CONFIG1_CFG_UNUSED_MASK	0x1fff
2448 #define	LPU_LTSSM_CONFIG1_LPBK_MSTR	  17
2449 #define	LPU_LTSSM_CONFIG1_HI_DATA_SUP	  16
2450 #define	LPU_LTSSM_CONFIG1_LTSSM_8_TO	8
2451 #define	LPU_LTSSM_CONFIG1_LTSSM_8_TO_MASK	0xff
2452 #define	LPU_LTSSM_CONFIG1_LTSSM_20_TO	0
2453 #define	LPU_LTSSM_CONFIG1_LTSSM_20_TO_MASK	0xff
2454 #define	LPU_LTSSM_CONFIG2	0xe2788
2455 #define	LPU_LTSSM_CONFIG2_LTSSM_12_TO	0
2456 #define	LPU_LTSSM_CONFIG2_LTSSM_12_TO_MASK	0xffffffff
2457 #define	LPU_LTSSM_CONFIG3	0xe2790
2458 #define	LPU_LTSSM_CONFIG3_LTSSM_2_TO	0
2459 #define	LPU_LTSSM_CONFIG3_LTSSM_2_TO_MASK	0xffffffff
2460 #define	LPU_LTSSM_CONFIG4	0xe2798
2461 #define	LPU_LTSSM_CONFIG4_TRN_CNTRL	24
2462 #define	LPU_LTSSM_CONFIG4_TRN_CNTRL_MASK	0xff
2463 #define	LPU_LTSSM_CONFIG4_DATA_RATE	16
2464 #define	LPU_LTSSM_CONFIG4_DATA_RATE_MASK	0xff
2465 #define	LPU_LTSSM_CONFIG4_N_FTS	8
2466 #define	LPU_LTSSM_CONFIG4_N_FTS_MASK	0xff
2467 #define	LPU_LTSSM_CONFIG4_LNK_NUM	0
2468 #define	LPU_LTSSM_CONFIG4_LNK_NUM_MASK	0xff
2469 #define	LPU_LTSSM_CONFIG5	0xe27a0
2470 #define	LPU_LTSSM_CONFIG5_CFG_UNUSED_0	13
2471 #define	LPU_LTSSM_CONFIG5_CFG_UNUSED_0_MASK	0x7ffff
2472 #define	LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE	  12
2473 #define	LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS	  11
2474 #define	LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS	  10
2475 #define	LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK	  9
2476 #define	LPU_LTSSM_CONFIG5_CFG_UNUSED_1	7
2477 #define	LPU_LTSSM_CONFIG5_CFG_UNUSED_1_MASK	0x3
2478 #define	LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE	  6
2479 #define	LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT	  5
2480 #define	LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT	  4
2481 #define	LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK	  3
2482 #define	LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST	  2
2483 #define	LPU_LTSSM_CONFIG5_L0_LPBK	  1
2484 #define	LPU_LTSSM_CONFIG5_CFG_UNUSED_2	  0
2485 #define	LPU_LTSSM_STATUS1	0xe27a8
2486 #define	LPU_LTSSM_STATUS1_RX_LN_EN_MSK	16
2487 #define	LPU_LTSSM_STATUS1_RX_LN_EN_MSK_MASK	0xffff
2488 #define	LPU_LTSSM_STATUS1_RX_ALGN_CMD	  15
2489 #define	LPU_LTSSM_STATUS1_MSTR_LN_SEL	  14
2490 #define	LPU_LTSSM_STATUS1_LNK_OT_RX	  13
2491 #define	LPU_LTSSM_STATUS1_LNK_OT_TX	  12
2492 #define	LPU_LTSSM_STATUS1_LN_RVRSD	  11
2493 #define	LPU_LTSSM_STATUS1_LNK_UP_DWN_STS	  10
2494 #define	LPU_LTSSM_STATUS1_LTSSM_STATE	4
2495 #define	LPU_LTSSM_STATUS1_LTSSM_STATE_MASK	0x3f
2496 #define	LPU_LTSSM_STATUS1_CNFG_LNK_WDTH	0
2497 #define	LPU_LTSSM_STATUS1_CNFG_LNK_WDTH_MASK	0xf
2498 #define	LPU_LTSSM_STATUS2	0xe27b0
2499 #define	LPU_LTSSM_STATUS2_TX_CMD_TX_PHY	16
2500 #define	LPU_LTSSM_STATUS2_TX_CMD_TX_PHY_MASK	0xffff
2501 #define	LPU_LTSSM_STATUS2_RX_CMD_RX_PHY	0
2502 #define	LPU_LTSSM_STATUS2_RX_CMD_RX_PHY_MASK	0xffff
2503 #define	LPU_LTSSM_INTERRUPT_AND_STATUS	0xe27b8
2504 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ANY	  31
2505 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_SKIP_OS	  15
2506 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_FTS	  14
2507 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TS2_RECOV	  13
2508 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_8IDLE_DATA	  12
2509 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_IDLE_DATA	  11
2510 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_POLL	  10
2511 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_INV	  9
2512 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_EIDLE_EXIT	  8
2513 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_COMP	  7
2514 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_LB	  6
2515 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_DIS	  5
2516 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TSX_RST	  4
2517 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_EIDLE	  3
2518 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TS2	  2
2519 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_TS1	  1
2520 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_INT_NONE	  0
2521 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST	0xe27c0
2522 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_SKIP_OS	  15
2523 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_FTS	  14
2524 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TS2_RECOV	  13
2525 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_8IDLE_DATA	  12
2526 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_IDLE_DATA	  11
2527 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_POLL	  10
2528 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_INV	  9
2529 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_EIDLE_EXIT	  8
2530 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_COMP	  7
2531 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_LB	  6
2532 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_DIS	  5
2533 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TSX_RST	  4
2534 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_EIDLE	  3
2535 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TS2	  2
2536 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_TS1	  1
2537 #define	LPU_LTSSM_INTERRUPT_AND_STATUS_TEST_TST_NONE	  0
2538 #define	LPU_LTSSM_INTERRUPT_MASK	0xe27c8
2539 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_GLB	  31
2540 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_SKIP_OS	  15
2541 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_FTS	  14
2542 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TS2_RECOV	  13
2543 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_8IDLE_DATA	  12
2544 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_IDLE_DATA	  11
2545 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_POLL	  10
2546 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_INV	  9
2547 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_EIDLE_EXIT	  8
2548 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_COMP	  7
2549 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_LB	  6
2550 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_DIS	  5
2551 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TSX_RST	  4
2552 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_EIDLE	  3
2553 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TS2	  2
2554 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_TS1	  1
2555 #define	LPU_LTSSM_INTERRUPT_MASK_MSK_NONE	  0
2556 #define	LPU_LTSSM_STATUS_WRITE_ENABLE	0xe27d0
2557 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE_UNUSED	11
2558 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE_UNUSED_MASK	0x1fffff
2559 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE1_LTSSM_STS2	  10
2560 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE2_LTSSM_STS2	  9
2561 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE1_LTSSM_STS1	  8
2562 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE2_LTSSM_STS1	  7
2563 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE3_LTSSM_STS1	  6
2564 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE4_LTSSM_STS1	  5
2565 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE5_LTSSM_STS1	  4
2566 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE6_LTSSM_STS1	  3
2567 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE7_LTSSM_STS1	  2
2568 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE8_LTSSM_STS1	  1
2569 #define	LPU_LTSSM_STATUS_WRITE_ENABLE_WE9_LTSSM_STS1	  0
2570 
2571 /* Reserved 0xe27d8 - 0xe27f8 */
2572 
2573 #define	LPU_GIGABLAZE_GLUE_CONFIG1	0xe2800
2574 #define	LPU_GIGABLAZE_GLUE_CONFIG1_UNUSED_CNTL1	28
2575 #define	LPU_GIGABLAZE_GLUE_CONFIG1_UNUSED_CNTL1_MASK	0xf
2576 #define	LPU_GIGABLAZE_GLUE_CONFIG1_STM_SEL	24
2577 #define	LPU_GIGABLAZE_GLUE_CONFIG1_STM_SEL_MASK	0xf
2578 #define	LPU_GIGABLAZE_GLUE_CONFIG1_UNUSED_CNTL2	22
2579 #define	LPU_GIGABLAZE_GLUE_CONFIG1_UNUSED_CNTL2_MASK	0x3
2580 #define	LPU_GIGABLAZE_GLUE_CONFIG1_REV_LPBK_SEL	20
2581 #define	LPU_GIGABLAZE_GLUE_CONFIG1_REV_LPBK_SEL_MASK	0x3
2582 #define	LPU_GIGABLAZE_GLUE_CONFIG1_REV_LPBK_MODE	  19
2583 #define	LPU_GIGABLAZE_GLUE_CONFIG1_LPBK_ENB	  18
2584 #define	LPU_GIGABLAZE_GLUE_CONFIG1_LPBK_MODE_SEL	16
2585 #define	LPU_GIGABLAZE_GLUE_CONFIG1_LPBK_MODE_SEL_MASK	0x3
2586 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_FLTR_EN	  15
2587 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_ADJUST	12
2588 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_ADJUST_MASK	0x7
2589 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_SMPL_RT	8
2590 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_SMPL_RT_MASK	0xf
2591 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_THRSH_CN	0
2592 #define	LPU_GIGABLAZE_GLUE_CONFIG1_RXLOS_THRSH_CN_MASK	0xff
2593 #define	LPU_GIGABLAZE_GLUE_CONFIG2	0xe2808
2594 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VPULSE_CTL	30
2595 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VPULSE_CTL_MASK	0x3
2596 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VMUX_CTL	28
2597 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VMUX_CTL_MASK	0x3
2598 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_RISE_FALL	25
2599 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_RISE_FALL_MASK	0x7
2600 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PRE_EMPH	22
2601 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PRE_EMPH_MASK	0x7
2602 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VSWNG_CTL	18
2603 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_VSWNG_CTL_MASK	0xf
2604 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PLL_ZERO_CTL	16
2605 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PLL_ZERO_CTL_MASK	0x3
2606 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PLL_POLE_CTL	14
2607 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_PLL_POLE_CTL_MASK	0x3
2608 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_PLL_ZERO_CTL	12
2609 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_PLL_ZERO_CTL_MASK	0x3
2610 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_PLL_POLE_CTL	10
2611 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_PLL_POLE_CTL_MASK	0x3
2612 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_EQLIZR_CTL	6
2613 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_EQLIZR_CTL_MASK	0xf
2614 #define	LPU_GIGABLAZE_GLUE_CONFIG2_OHM_SEL	  5
2615 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RTRIMEN	  4
2616 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_TERM	2
2617 #define	LPU_GIGABLAZE_GLUE_CONFIG2_TX_TERM_MASK	0x3
2618 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_TERM	0
2619 #define	LPU_GIGABLAZE_GLUE_CONFIG2_RX_TERM_MASK	0x3
2620 #define	LPU_GIGABLAZE_GLUE_CONFIG3	0xe2810
2621 #define	LPU_GIGABLAZE_GLUE_CONFIG3_UNUSED_CNTL3	27
2622 #define	LPU_GIGABLAZE_GLUE_CONFIG3_UNUSED_CNTL3_MASK	0x1f
2623 #define	LPU_GIGABLAZE_GLUE_CONFIG3_OUT_BIAS_CTL	  26
2624 #define	LPU_GIGABLAZE_GLUE_CONFIG3_TX_RCV_DET	24
2625 #define	LPU_GIGABLAZE_GLUE_CONFIG3_TX_RCV_DET_MASK	0x3
2626 #define	LPU_GIGABLAZE_GLUE_CONFIG3_TX_PLL_HLF_RT_CTL	  23
2627 #define	LPU_GIGABLAZE_GLUE_CONFIG3_TX_PLL_FDBK_DIV	20
2628 #define	LPU_GIGABLAZE_GLUE_CONFIG3_TX_PLL_FDBK_DIV_MASK	0x7
2629 #define	LPU_GIGABLAZE_GLUE_CONFIG3_RX_PLL_HLF_RT_CTL	  19
2630 #define	LPU_GIGABLAZE_GLUE_CONFIG3_RX_PLL_FDBK_DIV	16
2631 #define	LPU_GIGABLAZE_GLUE_CONFIG3_RX_PLL_FDBK_DIV_MASK	0x7
2632 #define	LPU_GIGABLAZE_GLUE_CONFIG3_BIT_LCK_TM	0
2633 #define	LPU_GIGABLAZE_GLUE_CONFIG3_BIT_LCK_TM_MASK	0xffff
2634 #define	LPU_GIGABLAZE_GLUE_CONFIG4	0xe2818
2635 #define	LPU_GIGABLAZE_GLUE_CONFIG4_CFG_UNUSED	20
2636 #define	LPU_GIGABLAZE_GLUE_CONFIG4_CFG_UNUSED_MASK	0xfff
2637 #define	LPU_GIGABLAZE_GLUE_CONFIG4_INIT_TIME	0
2638 #define	LPU_GIGABLAZE_GLUE_CONFIG4_INIT_TIME_MASK	0xfffff
2639 #define	LPU_GIGABLAZE_GLUE_STATUS	0xe2820
2640 #define	LPU_GIGABLAZE_GLUE_STATUS_RCV_ELECT_IDLE	16
2641 #define	LPU_GIGABLAZE_GLUE_STATUS_RCV_ELECT_IDLE_MASK	0xffff
2642 #define	LPU_GIGABLAZE_GLUE_STATUS_BIT_SYNC_DN	0
2643 #define	LPU_GIGABLAZE_GLUE_STATUS_BIT_SYNC_DN_MASK	0xffff
2644 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS	0xe2828
2645 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_GLOBL_UNMSK	  31
2646 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_UNUSED	16
2647 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_UNUSED_MASK	0xff
2648 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_BYTE_SYNC_STS	0
2649 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_BYTE_SYNC_STS_MASK	0xffff
2650 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST	0xe2830
2651 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST_TST_W1S_INT	16
2652 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST_TST_W1S_INT_MASK	0xff
2653 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST_TST_BSSS_INT	0
2654 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST_TST_BSSS_INT_MASK	0xffff
2655 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_MASK	0xe2838
2656 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_MASK_MSK_GLOBL_INT	  31
2657 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_MASK_MSK_INT	0
2658 #define	LPU_GIGABLAZE_GLUE_INTERRUPT_MASK_MSK_INT_MASK	0xffffff
2659 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1	0xe2840
2660 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_TX_PWR_DN	16
2661 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_TX_PWR_DN_MASK	0xffff
2662 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_THE	0
2663 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_THE_MASK	0x1
2664 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_RX_PWR_DN	0
2665 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN1_RX_PWR_DN_MASK	0xffff
2666 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2	0xe2848
2667 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_PD_UNUSED	22
2668 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_PD_UNUSED_MASK	0x3ff
2669 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_PWR_DN_CLK_BUF	  21
2670 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_PWR_DN_RES_TRIM	  20
2671 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_TX_PLL_PWR_D	16
2672 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_TX_PLL_PWR_D_MASK	0xf
2673 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_RXLOS_PWR_DN	0
2674 #define	LPU_GIGABLAZE_GLUE_POWER_DOWN2_RXLOS_PWR_DN_MASK	0xffff
2675 #define	LPU_GIGABLAZE_GLUE_CONFIG5	0xe2850
2676 
2677 #ifdef	__cplusplus
2678 }
2679 #endif
2680 
2681 #endif	/* _SYS_PX_REGS_H */
2682