1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 /* Please note that modifications to all structs defined here are 37 * subject to backwards-compatibility constraints. 38 */ 39 40 /** 41 * DOC: uevents generated by i915 on it's device node 42 * 43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 44 * event from the gpu l3 cache. Additional information supplied is ROW, 45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 46 * track of these events and if a specific cache-line seems to have a 47 * persistent error remap it with the l3 remapping tool supplied in 48 * intel-gpu-tools. The value supplied with the event is always 1. 49 * 50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 51 * hangcheck. The error detection event is a good indicator of when things 52 * began to go badly. The value supplied with the event is a 1 upon error 53 * detection, and a 0 upon reset completion, signifying no more error 54 * exists. NOTE: Disabling hangcheck or reset via module parameter will 55 * cause the related events to not be seen. 56 * 57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 58 * the GPU. The value supplied with the event is always 1. NOTE: Disable 59 * reset via module parameter will cause this event to not be seen. 60 */ 61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 62 #define I915_ERROR_UEVENT "ERROR" 63 #define I915_RESET_UEVENT "RESET" 64 65 /* 66 * MOCS indexes used for GPU surfaces, defining the cacheability of the 67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses. 68 */ 69 enum i915_mocs_table_index { 70 /* 71 * Not cached anywhere, coherency between CPU and GPU accesses is 72 * guaranteed. 73 */ 74 I915_MOCS_UNCACHED, 75 /* 76 * Cacheability and coherency controlled by the kernel automatically 77 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current 78 * usage of the surface (used for display scanout or not). 79 */ 80 I915_MOCS_PTE, 81 /* 82 * Cached in all GPU caches available on the platform. 83 * Coherency between CPU and GPU accesses to the surface is not 84 * guaranteed without extra synchronization. 85 */ 86 I915_MOCS_CACHED, 87 }; 88 89 /* Each region is a minimum of 16k, and there are at most 255 of them. 90 */ 91 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 92 * of chars for next/prev indices */ 93 #define I915_LOG_MIN_TEX_REGION_SIZE 14 94 95 typedef struct _drm_i915_init { 96 enum { 97 I915_INIT_DMA = 0x01, 98 I915_CLEANUP_DMA = 0x02, 99 I915_RESUME_DMA = 0x03 100 } func; 101 unsigned int mmio_offset; 102 int sarea_priv_offset; 103 unsigned int ring_start; 104 unsigned int ring_end; 105 unsigned int ring_size; 106 unsigned int front_offset; 107 unsigned int back_offset; 108 unsigned int depth_offset; 109 unsigned int w; 110 unsigned int h; 111 unsigned int pitch; 112 unsigned int pitch_bits; 113 unsigned int back_pitch; 114 unsigned int depth_pitch; 115 unsigned int cpp; 116 unsigned int chipset; 117 } drm_i915_init_t; 118 119 typedef struct _drm_i915_sarea { 120 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 121 int last_upload; /* last time texture was uploaded */ 122 int last_enqueue; /* last time a buffer was enqueued */ 123 int last_dispatch; /* age of the most recently dispatched buffer */ 124 int ctxOwner; /* last context to upload state */ 125 int texAge; 126 int pf_enabled; /* is pageflipping allowed? */ 127 int pf_active; 128 int pf_current_page; /* which buffer is being displayed? */ 129 int perf_boxes; /* performance boxes to be displayed */ 130 int width, height; /* screen size in pixels */ 131 int pad0; 132 133 drm_handle_t front_handle; 134 int front_offset; 135 int front_size; 136 137 drm_handle_t back_handle; 138 int back_offset; 139 int back_size; 140 141 drm_handle_t depth_handle; 142 int depth_offset; 143 int depth_size; 144 145 drm_handle_t tex_handle; 146 int tex_offset; 147 int tex_size; 148 int log_tex_granularity; 149 int pitch; 150 int rotation; /* 0, 90, 180 or 270 */ 151 int rotated_offset; 152 int rotated_size; 153 int rotated_pitch; 154 int virtualX, virtualY; 155 156 unsigned int front_tiled; 157 unsigned int back_tiled; 158 unsigned int depth_tiled; 159 unsigned int rotated_tiled; 160 unsigned int rotated2_tiled; 161 162 int pipeA_x; 163 int pipeA_y; 164 int pipeA_w; 165 int pipeA_h; 166 int pipeB_x; 167 int pipeB_y; 168 int pipeB_w; 169 int pipeB_h; 170 171 int pad1; 172 173 /* fill out some space for old userspace triple buffer */ 174 drm_handle_t unused_handle; 175 __u32 unused1, unused2, unused3; 176 177 /* buffer object handles for static buffers. May change 178 * over the lifetime of the client. 179 */ 180 __u32 front_bo_handle; 181 __u32 back_bo_handle; 182 __u32 unused_bo_handle; 183 __u32 depth_bo_handle; 184 185 } drm_i915_sarea_t; 186 187 /* due to userspace building against these headers we need some compat here */ 188 #define planeA_x pipeA_x 189 #define planeA_y pipeA_y 190 #define planeA_w pipeA_w 191 #define planeA_h pipeA_h 192 #define planeB_x pipeB_x 193 #define planeB_y pipeB_y 194 #define planeB_w pipeB_w 195 #define planeB_h pipeB_h 196 197 /* Flags for perf_boxes 198 */ 199 #define I915_BOX_RING_EMPTY 0x1 200 #define I915_BOX_FLIP 0x2 201 #define I915_BOX_WAIT 0x4 202 #define I915_BOX_TEXTURE_LOAD 0x8 203 #define I915_BOX_LOST_CONTEXT 0x10 204 205 /* 206 * i915 specific ioctls. 207 * 208 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 209 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 210 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 211 */ 212 #define DRM_I915_INIT 0x00 213 #define DRM_I915_FLUSH 0x01 214 #define DRM_I915_FLIP 0x02 215 #define DRM_I915_BATCHBUFFER 0x03 216 #define DRM_I915_IRQ_EMIT 0x04 217 #define DRM_I915_IRQ_WAIT 0x05 218 #define DRM_I915_GETPARAM 0x06 219 #define DRM_I915_SETPARAM 0x07 220 #define DRM_I915_ALLOC 0x08 221 #define DRM_I915_FREE 0x09 222 #define DRM_I915_INIT_HEAP 0x0a 223 #define DRM_I915_CMDBUFFER 0x0b 224 #define DRM_I915_DESTROY_HEAP 0x0c 225 #define DRM_I915_SET_VBLANK_PIPE 0x0d 226 #define DRM_I915_GET_VBLANK_PIPE 0x0e 227 #define DRM_I915_VBLANK_SWAP 0x0f 228 #define DRM_I915_HWS_ADDR 0x11 229 #define DRM_I915_GEM_INIT 0x13 230 #define DRM_I915_GEM_EXECBUFFER 0x14 231 #define DRM_I915_GEM_PIN 0x15 232 #define DRM_I915_GEM_UNPIN 0x16 233 #define DRM_I915_GEM_BUSY 0x17 234 #define DRM_I915_GEM_THROTTLE 0x18 235 #define DRM_I915_GEM_ENTERVT 0x19 236 #define DRM_I915_GEM_LEAVEVT 0x1a 237 #define DRM_I915_GEM_CREATE 0x1b 238 #define DRM_I915_GEM_PREAD 0x1c 239 #define DRM_I915_GEM_PWRITE 0x1d 240 #define DRM_I915_GEM_MMAP 0x1e 241 #define DRM_I915_GEM_SET_DOMAIN 0x1f 242 #define DRM_I915_GEM_SW_FINISH 0x20 243 #define DRM_I915_GEM_SET_TILING 0x21 244 #define DRM_I915_GEM_GET_TILING 0x22 245 #define DRM_I915_GEM_GET_APERTURE 0x23 246 #define DRM_I915_GEM_MMAP_GTT 0x24 247 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 248 #define DRM_I915_GEM_MADVISE 0x26 249 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 250 #define DRM_I915_OVERLAY_ATTRS 0x28 251 #define DRM_I915_GEM_EXECBUFFER2 0x29 252 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 253 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 254 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 255 #define DRM_I915_GEM_WAIT 0x2c 256 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 257 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 258 #define DRM_I915_GEM_SET_CACHING 0x2f 259 #define DRM_I915_GEM_GET_CACHING 0x30 260 #define DRM_I915_REG_READ 0x31 261 #define DRM_I915_GET_RESET_STATS 0x32 262 #define DRM_I915_GEM_USERPTR 0x33 263 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 264 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 265 #define DRM_I915_PERF_OPEN 0x36 266 267 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 268 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 269 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 270 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 271 /* I915_IRQ_EMIT is IOW not IOWR because it does its own copyout. */ 272 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 273 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 274 /* I915_GETPARAM is IOW not IOWR because it does its own copyout. */ 275 #define DRM_IOCTL_I915_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 276 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 277 /* I915_ALLOC is IOW not IOWR because it's a noop */ 278 #define DRM_IOCTL_I915_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 279 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 280 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 281 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 282 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 283 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 284 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 285 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 286 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 287 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 288 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 289 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 290 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 291 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 292 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 293 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 294 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 295 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 296 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 297 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 298 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 299 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 300 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 301 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 302 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 303 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 304 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 305 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 306 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 307 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 308 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 309 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 310 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 311 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 312 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 313 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 314 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 315 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 316 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 317 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 318 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 319 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 320 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 321 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 322 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 323 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 324 325 /* Allow drivers to submit batchbuffers directly to hardware, relying 326 * on the security mechanisms provided by hardware. 327 */ 328 typedef struct drm_i915_batchbuffer { 329 int start; /* agp offset */ 330 int used; /* nr bytes in use */ 331 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 332 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 333 int num_cliprects; /* mulitpass with multiple cliprects? */ 334 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 335 } drm_i915_batchbuffer_t; 336 337 typedef struct drm_i915_batchbuffer32 { 338 int start; /* agp offset */ 339 int used; /* nr bytes in use */ 340 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 341 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 342 int num_cliprects; /* mulitpass with multiple cliprects? */ 343 caddr32_t cliprects; /* pointer to userspace cliprects */ 344 } drm_i915_batchbuffer32_t; 345 346 /* As above, but pass a pointer to userspace buffer which can be 347 * validated by the kernel prior to sending to hardware. 348 */ 349 typedef struct _drm_i915_cmdbuffer { 350 char *buf; /* pointer to userspace command buffer */ 351 int sz; /* nr bytes in buf */ 352 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 353 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 354 int num_cliprects; /* mulitpass with multiple cliprects? */ 355 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ 356 } drm_i915_cmdbuffer_t; 357 358 typedef struct drm_i915_cmdbuffer32 { 359 caddr32_t buf; /* pointer to userspace command buffer */ 360 int sz; /* nr bytes in buf */ 361 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 362 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 363 int num_cliprects; /* mulitpass with multiple cliprects? */ 364 caddr32_t cliprects; /* pointer to userspace cliprects */ 365 } drm_i915_cmdbuffer32_t; 366 367 /* Userspace can request & wait on irq's: 368 */ 369 typedef struct drm_i915_irq_emit { 370 int *irq_seq; 371 } drm_i915_irq_emit_t; 372 373 typedef struct drm_i915_irq_emit32 { 374 caddr32_t irq_seq; 375 } drm_i915_irq_emit32_t; 376 377 typedef struct drm_i915_irq_wait { 378 int irq_seq; 379 } drm_i915_irq_wait_t; 380 381 /* Ioctl to query kernel params: 382 */ 383 #define I915_PARAM_IRQ_ACTIVE 1 384 #define I915_PARAM_ALLOW_BATCHBUFFER 2 385 #define I915_PARAM_LAST_DISPATCH 3 386 #define I915_PARAM_CHIPSET_ID 4 387 #define I915_PARAM_HAS_GEM 5 388 #define I915_PARAM_NUM_FENCES_AVAIL 6 389 #define I915_PARAM_HAS_OVERLAY 7 390 #define I915_PARAM_HAS_PAGEFLIPPING 8 391 #define I915_PARAM_HAS_EXECBUF2 9 392 #define I915_PARAM_HAS_BSD 10 393 #define I915_PARAM_HAS_BLT 11 394 #define I915_PARAM_HAS_RELAXED_FENCING 12 395 #define I915_PARAM_HAS_COHERENT_RINGS 13 396 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 397 #define I915_PARAM_HAS_RELAXED_DELTA 15 398 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 399 #define I915_PARAM_HAS_LLC 17 400 #define I915_PARAM_HAS_ALIASING_PPGTT 18 401 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 402 #define I915_PARAM_HAS_SEMAPHORES 20 403 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 404 #define I915_PARAM_HAS_VEBOX 22 405 #define I915_PARAM_HAS_SECURE_BATCHES 23 406 #define I915_PARAM_HAS_PINNED_BATCHES 24 407 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 408 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 409 #define I915_PARAM_HAS_WT 27 410 #define I915_PARAM_CMD_PARSER_VERSION 28 411 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 412 #define I915_PARAM_MMAP_VERSION 30 413 #define I915_PARAM_HAS_BSD2 31 414 #define I915_PARAM_REVISION 32 415 #define I915_PARAM_SUBSLICE_TOTAL 33 416 #define I915_PARAM_EU_TOTAL 34 417 #define I915_PARAM_HAS_GPU_RESET 35 418 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 419 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 420 #define I915_PARAM_HAS_POOLED_EU 38 421 #define I915_PARAM_MIN_EU_IN_POOL 39 422 #define I915_PARAM_MMAP_GTT_VERSION 40 423 424 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution 425 * priorities and the driver will attempt to execute batches in priority order. 426 */ 427 #define I915_PARAM_HAS_SCHEDULER 41 428 #define I915_PARAM_HUC_STATUS 42 429 430 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of 431 * synchronisation with implicit fencing on individual objects. 432 * See EXEC_OBJECT_ASYNC. 433 */ 434 #define I915_PARAM_HAS_EXEC_ASYNC 43 435 436 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - 437 * both being able to pass in a sync_file fd to wait upon before executing, 438 * and being able to return a new sync_file fd that is signaled when the 439 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. 440 */ 441 #define I915_PARAM_HAS_EXEC_FENCE 44 442 443 typedef struct drm_i915_getparam { 444 __s32 param; 445 /* 446 * WARNING: Using pointers instead of fixed-size u64 means we need to write 447 * compat32 code. Don't repeat this mistake. 448 */ 449 int *value; 450 } drm_i915_getparam_t; 451 452 typedef struct drm_i915_getparam32 { 453 int param; 454 caddr32_t value; 455 } drm_i915_getparam32_t; 456 457 /* Ioctl to set kernel params: 458 */ 459 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 460 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 461 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 462 #define I915_SETPARAM_NUM_USED_FENCES 4 463 464 typedef struct drm_i915_setparam { 465 int param; 466 int value; 467 } drm_i915_setparam_t; 468 469 /* A memory manager for regions of shared memory: 470 */ 471 #define I915_MEM_REGION_AGP 1 472 473 typedef struct drm_i915_mem_alloc { 474 int region; 475 int alignment; 476 int size; 477 int *region_offset; /* offset from start of fb or agp */ 478 } drm_i915_mem_alloc_t; 479 480 typedef struct drm_i915_mem_alloc32 { 481 int region; 482 int alignment; 483 int size; 484 caddr32_t region_offset; /* offset from start of fb or agp */ 485 } drm_i915_mem_alloc32_t; 486 487 typedef struct drm_i915_mem_free { 488 int region; 489 int region_offset; 490 } drm_i915_mem_free_t; 491 492 typedef struct drm_i915_mem_init_heap { 493 int region; 494 int size; 495 int start; 496 } drm_i915_mem_init_heap_t; 497 498 /* Allow memory manager to be torn down and re-initialized (eg on 499 * rotate): 500 */ 501 typedef struct drm_i915_mem_destroy_heap { 502 int region; 503 } drm_i915_mem_destroy_heap_t; 504 505 /* Allow X server to configure which pipes to monitor for vblank signals 506 */ 507 #define DRM_I915_VBLANK_PIPE_A 1 508 #define DRM_I915_VBLANK_PIPE_B 2 509 510 typedef struct drm_i915_vblank_pipe { 511 int pipe; 512 } drm_i915_vblank_pipe_t; 513 514 /* Schedule buffer swap at given vertical blank: 515 */ 516 typedef struct drm_i915_vblank_swap { 517 drm_drawable_t drawable; 518 enum drm_vblank_seq_type seqtype; 519 unsigned int sequence; 520 } drm_i915_vblank_swap_t; 521 522 typedef struct drm_i915_hws_addr { 523 __u64 addr; 524 } drm_i915_hws_addr_t; 525 526 struct drm_i915_gem_init { 527 /** 528 * Beginning offset in the GTT to be managed by the DRM memory 529 * manager. 530 */ 531 __u64 gtt_start; 532 /** 533 * Ending offset in the GTT to be managed by the DRM memory 534 * manager. 535 */ 536 __u64 gtt_end; 537 }; 538 539 struct drm_i915_gem_create { 540 /** 541 * Requested size for the object. 542 * 543 * The (page-aligned) allocated size for the object will be returned. 544 */ 545 __u64 size; 546 /** 547 * Returned handle for the object. 548 * 549 * Object handles are nonzero. 550 */ 551 __u32 handle; 552 __u32 pad; 553 }; 554 555 struct drm_i915_gem_pread { 556 /** Handle for the object being read. */ 557 __u32 handle; 558 __u32 pad; 559 /** Offset into the object to read from */ 560 __u64 offset; 561 /** Length of data to read */ 562 __u64 size; 563 /** 564 * Pointer to write the data into. 565 * 566 * This is a fixed-size type for 32/64 compatibility. 567 */ 568 __u64 data_ptr; 569 }; 570 571 struct drm_i915_gem_pwrite { 572 /** Handle for the object being written to. */ 573 __u32 handle; 574 __u32 pad; 575 /** Offset into the object to write to */ 576 __u64 offset; 577 /** Length of data to write */ 578 __u64 size; 579 /** 580 * Pointer to read the data from. 581 * 582 * This is a fixed-size type for 32/64 compatibility. 583 */ 584 __u64 data_ptr; 585 }; 586 587 struct drm_i915_gem_mmap { 588 /** Handle for the object being mapped. */ 589 __u32 handle; 590 __u32 pad; 591 /** Offset in the object to map. */ 592 __u64 offset; 593 /** 594 * Length of data to map. 595 * 596 * The value will be page-aligned. 597 */ 598 __u64 size; 599 /** 600 * Returned pointer the data was mapped at. 601 * 602 * This is a fixed-size type for 32/64 compatibility. 603 */ 604 __u64 addr_ptr; 605 606 /** 607 * Flags for extended behaviour. 608 * 609 * Added in version 2. 610 */ 611 __u64 flags; 612 #define I915_MMAP_WC 0x1 613 }; 614 615 struct drm_i915_gem_mmap_gtt { 616 /** Handle for the object being mapped. */ 617 __u32 handle; 618 __u32 pad; 619 /** 620 * Fake offset to use for subsequent mmap call 621 * 622 * This is a fixed-size type for 32/64 compatibility. 623 */ 624 __u64 offset; 625 }; 626 627 struct drm_i915_gem_set_domain { 628 /** Handle for the object */ 629 __u32 handle; 630 631 /** New read domains */ 632 __u32 read_domains; 633 634 /** New write domain */ 635 __u32 write_domain; 636 }; 637 638 struct drm_i915_gem_sw_finish { 639 /** Handle for the object */ 640 __u32 handle; 641 }; 642 643 struct drm_i915_gem_relocation_entry { 644 /** 645 * Handle of the buffer being pointed to by this relocation entry. 646 * 647 * It's appealing to make this be an index into the mm_validate_entry 648 * list to refer to the buffer, but this allows the driver to create 649 * a relocation list for state buffers and not re-write it per 650 * exec using the buffer. 651 */ 652 __u32 target_handle; 653 654 /** 655 * Value to be added to the offset of the target buffer to make up 656 * the relocation entry. 657 */ 658 __u32 delta; 659 660 /** Offset in the buffer the relocation entry will be written into */ 661 __u64 offset; 662 663 /** 664 * Offset value of the target buffer that the relocation entry was last 665 * written as. 666 * 667 * If the buffer has the same offset as last time, we can skip syncing 668 * and writing the relocation. This value is written back out by 669 * the execbuffer ioctl when the relocation is written. 670 */ 671 __u64 presumed_offset; 672 673 /** 674 * Target memory domains read by this operation. 675 */ 676 __u32 read_domains; 677 678 /** 679 * Target memory domains written by this operation. 680 * 681 * Note that only one domain may be written by the whole 682 * execbuffer operation, so that where there are conflicts, 683 * the application will get -EINVAL back. 684 */ 685 __u32 write_domain; 686 }; 687 688 /** @{ 689 * Intel memory domains 690 * 691 * Most of these just align with the various caches in 692 * the system and are used to flush and invalidate as 693 * objects end up cached in different domains. 694 */ 695 /** CPU cache */ 696 #define I915_GEM_DOMAIN_CPU 0x00000001 697 /** Render cache, used by 2D and 3D drawing */ 698 #define I915_GEM_DOMAIN_RENDER 0x00000002 699 /** Sampler cache, used by texture engine */ 700 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 701 /** Command queue, used to load batch buffers */ 702 #define I915_GEM_DOMAIN_COMMAND 0x00000008 703 /** Instruction cache, used by shader programs */ 704 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 705 /** Vertex address cache */ 706 #define I915_GEM_DOMAIN_VERTEX 0x00000020 707 /** GTT domain - aperture and scanout */ 708 #define I915_GEM_DOMAIN_GTT 0x00000040 709 /** @} */ 710 711 struct drm_i915_gem_exec_object { 712 /** 713 * User's handle for a buffer to be bound into the GTT for this 714 * operation. 715 */ 716 __u32 handle; 717 718 /** Number of relocations to be performed on this buffer */ 719 __u32 relocation_count; 720 /** 721 * Pointer to array of struct drm_i915_gem_relocation_entry containing 722 * the relocations to be performed in this buffer. 723 */ 724 __u64 relocs_ptr; 725 726 /** Required alignment in graphics aperture */ 727 __u64 alignment; 728 729 /** 730 * Returned value of the updated offset of the object, for future 731 * presumed_offset writes. 732 */ 733 __u64 offset; 734 }; 735 736 struct drm_i915_gem_execbuffer { 737 /** 738 * List of buffers to be validated with their relocations to be 739 * performend on them. 740 * 741 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 742 * 743 * These buffers must be listed in an order such that all relocations 744 * a buffer is performing refer to buffers that have already appeared 745 * in the validate list. 746 */ 747 __u64 buffers_ptr; 748 __u32 buffer_count; 749 750 /** Offset in the batchbuffer to start execution from. */ 751 __u32 batch_start_offset; 752 /** Bytes used in batchbuffer from batch_start_offset */ 753 __u32 batch_len; 754 __u32 DR1; 755 __u32 DR4; 756 __u32 num_cliprects; 757 /** This is a struct drm_clip_rect *cliprects */ 758 __u64 cliprects_ptr; 759 }; 760 761 struct drm_i915_gem_exec_object2 { 762 /** 763 * User's handle for a buffer to be bound into the GTT for this 764 * operation. 765 */ 766 __u32 handle; 767 768 /** Number of relocations to be performed on this buffer */ 769 __u32 relocation_count; 770 /** 771 * Pointer to array of struct drm_i915_gem_relocation_entry containing 772 * the relocations to be performed in this buffer. 773 */ 774 __u64 relocs_ptr; 775 776 /** Required alignment in graphics aperture */ 777 __u64 alignment; 778 779 /** 780 * When the EXEC_OBJECT_PINNED flag is specified this is populated by 781 * the user with the GTT offset at which this object will be pinned. 782 * When the I915_EXEC_NO_RELOC flag is specified this must contain the 783 * presumed_offset of the object. 784 * During execbuffer2 the kernel populates it with the value of the 785 * current GTT offset of the object, for future presumed_offset writes. 786 */ 787 __u64 offset; 788 789 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 790 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 791 #define EXEC_OBJECT_WRITE (1<<2) 792 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) 793 #define EXEC_OBJECT_PINNED (1<<4) 794 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) 795 /* The kernel implicitly tracks GPU activity on all GEM objects, and 796 * synchronises operations with outstanding rendering. This includes 797 * rendering on other devices if exported via dma-buf. However, sometimes 798 * this tracking is too coarse and the user knows better. For example, 799 * if the object is split into non-overlapping ranges shared between different 800 * clients or engines (i.e. suballocating objects), the implicit tracking 801 * by kernel assumes that each operation affects the whole object rather 802 * than an individual range, causing needless synchronisation between clients. 803 * The kernel will also forgo any CPU cache flushes prior to rendering from 804 * the object as the client is expected to be also handling such domain 805 * tracking. 806 * 807 * The kernel maintains the implicit tracking in order to manage resources 808 * used by the GPU - this flag only disables the synchronisation prior to 809 * rendering with this object in this execbuf. 810 * 811 * Opting out of implicit synhronisation requires the user to do its own 812 * explicit tracking to avoid rendering corruption. See, for example, 813 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. 814 */ 815 #define EXEC_OBJECT_ASYNC (1<<6) 816 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ 817 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1) 818 __u64 flags; 819 820 union { 821 __u64 rsvd1; 822 __u64 pad_to_size; 823 }; 824 __u64 rsvd2; 825 }; 826 827 struct drm_i915_gem_execbuffer2 { 828 /** 829 * List of gem_exec_object2 structs 830 */ 831 __u64 buffers_ptr; 832 __u32 buffer_count; 833 834 /** Offset in the batchbuffer to start execution from. */ 835 __u32 batch_start_offset; 836 /** Bytes used in batchbuffer from batch_start_offset */ 837 __u32 batch_len; 838 __u32 DR1; 839 __u32 DR4; 840 __u32 num_cliprects; 841 /** This is a struct drm_clip_rect *cliprects */ 842 __u64 cliprects_ptr; 843 #define I915_EXEC_RING_MASK (7<<0) 844 #define I915_EXEC_DEFAULT (0<<0) 845 #define I915_EXEC_RENDER (1<<0) 846 #define I915_EXEC_BSD (2<<0) 847 #define I915_EXEC_BLT (3<<0) 848 #define I915_EXEC_VEBOX (4<<0) 849 850 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 851 * Gen6+ only supports relative addressing to dynamic state (default) and 852 * absolute addressing. 853 * 854 * These flags are ignored for the BSD and BLT rings. 855 */ 856 #define I915_EXEC_CONSTANTS_MASK (3<<6) 857 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 858 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 859 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 860 __u64 flags; 861 __u64 rsvd1; /* now used for context info */ 862 __u64 rsvd2; 863 }; 864 865 /** Resets the SO write offset registers for transform feedback on gen7. */ 866 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 867 868 /** Request a privileged ("secure") batch buffer. Note only available for 869 * DRM_ROOT_ONLY | DRM_MASTER processes. 870 */ 871 #define I915_EXEC_SECURE (1<<9) 872 873 /** Inform the kernel that the batch is and will always be pinned. This 874 * negates the requirement for a workaround to be performed to avoid 875 * an incoherent CS (such as can be found on 830/845). If this flag is 876 * not passed, the kernel will endeavour to make sure the batch is 877 * coherent with the CS before execution. If this flag is passed, 878 * userspace assumes the responsibility for ensuring the same. 879 */ 880 #define I915_EXEC_IS_PINNED (1<<10) 881 882 /** Provide a hint to the kernel that the command stream and auxiliary 883 * state buffers already holds the correct presumed addresses and so the 884 * relocation process may be skipped if no buffers need to be moved in 885 * preparation for the execbuffer. 886 */ 887 #define I915_EXEC_NO_RELOC (1<<11) 888 889 /** Use the reloc.handle as an index into the exec object array rather 890 * than as the per-file handle. 891 */ 892 #define I915_EXEC_HANDLE_LUT (1<<12) 893 894 /** Used for switching BSD rings on the platforms with two BSD rings */ 895 #define I915_EXEC_BSD_SHIFT (13) 896 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 897 /* default ping-pong mode */ 898 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 899 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 900 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 901 902 /** Tell the kernel that the batchbuffer is processed by 903 * the resource streamer. 904 */ 905 #define I915_EXEC_RESOURCE_STREAMER (1<<15) 906 907 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent 908 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing 909 * the batch. 910 * 911 * Returns -EINVAL if the sync_file fd cannot be found. 912 */ 913 #define I915_EXEC_FENCE_IN (1<<16) 914 915 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd 916 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given 917 * to the caller, and it should be close() after use. (The fd is a regular 918 * file descriptor and will be cleaned up on process termination. It holds 919 * a reference to the request, but nothing else.) 920 * 921 * The sync_file fd can be combined with other sync_file and passed either 922 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip 923 * will only occur after this request completes), or to other devices. 924 * 925 * Using I915_EXEC_FENCE_OUT requires use of 926 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written 927 * back to userspace. Failure to do so will cause the out-fence to always 928 * be reported as zero, and the real fence fd to be leaked. 929 */ 930 #define I915_EXEC_FENCE_OUT (1<<17) 931 932 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1)) 933 934 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 935 #define i915_execbuffer2_set_context_id(eb2, context) \ 936 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 937 #define i915_execbuffer2_get_context_id(eb2) \ 938 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 939 940 struct drm_i915_gem_pin { 941 /** Handle of the buffer to be pinned. */ 942 __u32 handle; 943 __u32 pad; 944 945 /** alignment required within the aperture */ 946 __u64 alignment; 947 948 /** Returned GTT offset of the buffer. */ 949 __u64 offset; 950 }; 951 952 struct drm_i915_gem_unpin { 953 /** Handle of the buffer to be unpinned. */ 954 __u32 handle; 955 __u32 pad; 956 }; 957 958 struct drm_i915_gem_busy { 959 /** Handle of the buffer to check for busy */ 960 __u32 handle; 961 962 /** Return busy status 963 * 964 * A return of 0 implies that the object is idle (after 965 * having flushed any pending activity), and a non-zero return that 966 * the object is still in-flight on the GPU. (The GPU has not yet 967 * signaled completion for all pending requests that reference the 968 * object.) An object is guaranteed to become idle eventually (so 969 * long as no new GPU commands are executed upon it). Due to the 970 * asynchronous nature of the hardware, an object reported 971 * as busy may become idle before the ioctl is completed. 972 * 973 * Furthermore, if the object is busy, which engine is busy is only 974 * provided as a guide. There are race conditions which prevent the 975 * report of which engines are busy from being always accurate. 976 * However, the converse is not true. If the object is idle, the 977 * result of the ioctl, that all engines are idle, is accurate. 978 * 979 * The returned dword is split into two fields to indicate both 980 * the engines on which the object is being read, and the 981 * engine on which it is currently being written (if any). 982 * 983 * The low word (bits 0:15) indicate if the object is being written 984 * to by any engine (there can only be one, as the GEM implicit 985 * synchronisation rules force writes to be serialised). Only the 986 * engine for the last write is reported. 987 * 988 * The high word (bits 16:31) are a bitmask of which engines are 989 * currently reading from the object. Multiple engines may be 990 * reading from the object simultaneously. 991 * 992 * The value of each engine is the same as specified in the 993 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. 994 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to 995 * the I915_EXEC_RENDER engine for execution, and so it is never 996 * reported as active itself. Some hardware may have parallel 997 * execution engines, e.g. multiple media engines, which are 998 * mapped to the same identifier in the EXECBUFFER2 ioctl and 999 * so are not separately reported for busyness. 1000 * 1001 * Caveat emptor: 1002 * Only the boolean result of this query is reliable; that is whether 1003 * the object is idle or busy. The report of which engines are busy 1004 * should be only used as a heuristic. 1005 */ 1006 __u32 busy; 1007 }; 1008 1009 /** 1010 * I915_CACHING_NONE 1011 * 1012 * GPU access is not coherent with cpu caches. Default for machines without an 1013 * LLC. 1014 */ 1015 #define I915_CACHING_NONE 0 1016 /** 1017 * I915_CACHING_CACHED 1018 * 1019 * GPU access is coherent with cpu caches and furthermore the data is cached in 1020 * last-level caches shared between cpu cores and the gpu GT. Default on 1021 * machines with HAS_LLC. 1022 */ 1023 #define I915_CACHING_CACHED 1 1024 /** 1025 * I915_CACHING_DISPLAY 1026 * 1027 * Special GPU caching mode which is coherent with the scanout engines. 1028 * Transparently falls back to I915_CACHING_NONE on platforms where no special 1029 * cache mode (like write-through or gfdt flushing) is available. The kernel 1030 * automatically sets this mode when using a buffer as a scanout target. 1031 * Userspace can manually set this mode to avoid a costly stall and clflush in 1032 * the hotpath of drawing the first frame. 1033 */ 1034 #define I915_CACHING_DISPLAY 2 1035 1036 struct drm_i915_gem_caching { 1037 /** 1038 * Handle of the buffer to set/get the caching level of. */ 1039 __u32 handle; 1040 1041 /** 1042 * Cacheing level to apply or return value 1043 * 1044 * bits0-15 are for generic caching control (i.e. the above defined 1045 * values). bits16-31 are reserved for platform-specific variations 1046 * (e.g. l3$ caching on gen7). */ 1047 __u32 caching; 1048 }; 1049 1050 #define I915_TILING_NONE 0 1051 #define I915_TILING_X 1 1052 #define I915_TILING_Y 2 1053 #define I915_TILING_LAST I915_TILING_Y 1054 1055 #define I915_BIT_6_SWIZZLE_NONE 0 1056 #define I915_BIT_6_SWIZZLE_9 1 1057 #define I915_BIT_6_SWIZZLE_9_10 2 1058 #define I915_BIT_6_SWIZZLE_9_11 3 1059 #define I915_BIT_6_SWIZZLE_9_10_11 4 1060 /* Not seen by userland */ 1061 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 1062 /* Seen by userland. */ 1063 #define I915_BIT_6_SWIZZLE_9_17 6 1064 #define I915_BIT_6_SWIZZLE_9_10_17 7 1065 1066 struct drm_i915_gem_set_tiling { 1067 /** Handle of the buffer to have its tiling state updated */ 1068 __u32 handle; 1069 1070 /** 1071 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1072 * I915_TILING_Y). 1073 * 1074 * This value is to be set on request, and will be updated by the 1075 * kernel on successful return with the actual chosen tiling layout. 1076 * 1077 * The tiling mode may be demoted to I915_TILING_NONE when the system 1078 * has bit 6 swizzling that can't be managed correctly by GEM. 1079 * 1080 * Buffer contents become undefined when changing tiling_mode. 1081 */ 1082 __u32 tiling_mode; 1083 1084 /** 1085 * Stride in bytes for the object when in I915_TILING_X or 1086 * I915_TILING_Y. 1087 */ 1088 __u32 stride; 1089 1090 /** 1091 * Returned address bit 6 swizzling required for CPU access through 1092 * mmap mapping. 1093 */ 1094 __u32 swizzle_mode; 1095 }; 1096 1097 struct drm_i915_gem_get_tiling { 1098 /** Handle of the buffer to get tiling state for. */ 1099 __u32 handle; 1100 1101 /** 1102 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 1103 * I915_TILING_Y). 1104 */ 1105 __u32 tiling_mode; 1106 1107 /** 1108 * Returned address bit 6 swizzling required for CPU access through 1109 * mmap mapping. 1110 */ 1111 __u32 swizzle_mode; 1112 1113 /** 1114 * Returned address bit 6 swizzling required for CPU access through 1115 * mmap mapping whilst bound. 1116 */ 1117 __u32 phys_swizzle_mode; 1118 }; 1119 1120 struct drm_i915_gem_get_aperture { 1121 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 1122 __u64 aper_size; 1123 1124 /** 1125 * Available space in the aperture used by i915_gem_execbuffer, in 1126 * bytes 1127 */ 1128 __u64 aper_available_size; 1129 }; 1130 1131 struct drm_i915_get_pipe_from_crtc_id { 1132 /** ID of CRTC being requested **/ 1133 __u32 crtc_id; 1134 1135 /** pipe of requested CRTC **/ 1136 __u32 pipe; 1137 }; 1138 1139 #define I915_MADV_WILLNEED 0 1140 #define I915_MADV_DONTNEED 1 1141 #define __I915_MADV_PURGED 2 /* internal state */ 1142 1143 struct drm_i915_gem_madvise { 1144 /** Handle of the buffer to change the backing store advice */ 1145 __u32 handle; 1146 1147 /* Advice: either the buffer will be needed again in the near future, 1148 * or wont be and could be discarded under memory pressure. 1149 */ 1150 __u32 madv; 1151 1152 /** Whether the backing store still exists. */ 1153 __u32 retained; 1154 }; 1155 1156 /* flags */ 1157 #define I915_OVERLAY_TYPE_MASK 0xff 1158 #define I915_OVERLAY_YUV_PLANAR 0x01 1159 #define I915_OVERLAY_YUV_PACKED 0x02 1160 #define I915_OVERLAY_RGB 0x03 1161 1162 #define I915_OVERLAY_DEPTH_MASK 0xff00 1163 #define I915_OVERLAY_RGB24 0x1000 1164 #define I915_OVERLAY_RGB16 0x2000 1165 #define I915_OVERLAY_RGB15 0x3000 1166 #define I915_OVERLAY_YUV422 0x0100 1167 #define I915_OVERLAY_YUV411 0x0200 1168 #define I915_OVERLAY_YUV420 0x0300 1169 #define I915_OVERLAY_YUV410 0x0400 1170 1171 #define I915_OVERLAY_SWAP_MASK 0xff0000 1172 #define I915_OVERLAY_NO_SWAP 0x000000 1173 #define I915_OVERLAY_UV_SWAP 0x010000 1174 #define I915_OVERLAY_Y_SWAP 0x020000 1175 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 1176 1177 #define I915_OVERLAY_FLAGS_MASK 0xff000000 1178 #define I915_OVERLAY_ENABLE 0x01000000 1179 1180 struct drm_intel_overlay_put_image { 1181 /* various flags and src format description */ 1182 __u32 flags; 1183 /* source picture description */ 1184 __u32 bo_handle; 1185 /* stride values and offsets are in bytes, buffer relative */ 1186 __u16 stride_Y; /* stride for packed formats */ 1187 __u16 stride_UV; 1188 __u32 offset_Y; /* offset for packet formats */ 1189 __u32 offset_U; 1190 __u32 offset_V; 1191 /* in pixels */ 1192 __u16 src_width; 1193 __u16 src_height; 1194 /* to compensate the scaling factors for partially covered surfaces */ 1195 __u16 src_scan_width; 1196 __u16 src_scan_height; 1197 /* output crtc description */ 1198 __u32 crtc_id; 1199 __u16 dst_x; 1200 __u16 dst_y; 1201 __u16 dst_width; 1202 __u16 dst_height; 1203 }; 1204 1205 /* flags */ 1206 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1207 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1208 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1209 struct drm_intel_overlay_attrs { 1210 __u32 flags; 1211 __u32 color_key; 1212 __s32 brightness; 1213 __u32 contrast; 1214 __u32 saturation; 1215 __u32 gamma0; 1216 __u32 gamma1; 1217 __u32 gamma2; 1218 __u32 gamma3; 1219 __u32 gamma4; 1220 __u32 gamma5; 1221 }; 1222 1223 /* 1224 * Intel sprite handling 1225 * 1226 * Color keying works with a min/mask/max tuple. Both source and destination 1227 * color keying is allowed. 1228 * 1229 * Source keying: 1230 * Sprite pixels within the min & max values, masked against the color channels 1231 * specified in the mask field, will be transparent. All other pixels will 1232 * be displayed on top of the primary plane. For RGB surfaces, only the min 1233 * and mask fields will be used; ranged compares are not allowed. 1234 * 1235 * Destination keying: 1236 * Primary plane pixels that match the min value, masked against the color 1237 * channels specified in the mask field, will be replaced by corresponding 1238 * pixels from the sprite plane. 1239 * 1240 * Note that source & destination keying are exclusive; only one can be 1241 * active on a given plane. 1242 */ 1243 1244 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1245 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1246 #define I915_SET_COLORKEY_SOURCE (1<<2) 1247 struct drm_intel_sprite_colorkey { 1248 __u32 plane_id; 1249 __u32 min_value; 1250 __u32 channel_mask; 1251 __u32 max_value; 1252 __u32 flags; 1253 }; 1254 1255 struct drm_i915_gem_wait { 1256 /** Handle of BO we shall wait on */ 1257 __u32 bo_handle; 1258 __u32 flags; 1259 /** Number of nanoseconds to wait, Returns time remaining. */ 1260 __s64 timeout_ns; 1261 }; 1262 1263 struct drm_i915_gem_context_create { 1264 /* output: id of new context*/ 1265 __u32 ctx_id; 1266 __u32 pad; 1267 }; 1268 1269 struct drm_i915_gem_context_destroy { 1270 __u32 ctx_id; 1271 __u32 pad; 1272 }; 1273 1274 struct drm_i915_reg_read { 1275 /* 1276 * Register offset. 1277 * For 64bit wide registers where the upper 32bits don't immediately 1278 * follow the lower 32bits, the offset of the lower 32bits must 1279 * be specified 1280 */ 1281 __u64 offset; 1282 __u64 val; /* Return value */ 1283 }; 1284 /* Known registers: 1285 * 1286 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1287 * - Note this register returns an invalid value if using the default 1288 * single instruction 8byte read, in order to workaround that use 1289 * offset (0x2538 | 1) instead. 1290 * 1291 */ 1292 1293 struct drm_i915_reset_stats { 1294 __u32 ctx_id; 1295 __u32 flags; 1296 1297 /* All resets since boot/module reload, for all contexts */ 1298 __u32 reset_count; 1299 1300 /* Number of batches lost when active in GPU, for this context */ 1301 __u32 batch_active; 1302 1303 /* Number of batches lost pending for execution, for this context */ 1304 __u32 batch_pending; 1305 1306 __u32 pad; 1307 }; 1308 1309 struct drm_i915_gem_userptr { 1310 __u64 user_ptr; 1311 __u64 user_size; 1312 __u32 flags; 1313 #define I915_USERPTR_READ_ONLY 0x1 1314 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1315 /** 1316 * Returned handle for the object. 1317 * 1318 * Object handles are nonzero. 1319 */ 1320 __u32 handle; 1321 }; 1322 1323 struct drm_i915_gem_context_param { 1324 __u32 ctx_id; 1325 __u32 size; 1326 __u64 param; 1327 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1328 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 1329 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 1330 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 1331 #define I915_CONTEXT_PARAM_BANNABLE 0x5 1332 __u64 value; 1333 }; 1334 1335 enum drm_i915_oa_format { 1336 I915_OA_FORMAT_A13 = 1, 1337 I915_OA_FORMAT_A29, 1338 I915_OA_FORMAT_A13_B8_C8, 1339 I915_OA_FORMAT_B4_C8, 1340 I915_OA_FORMAT_A45_B8_C8, 1341 I915_OA_FORMAT_B4_C8_A16, 1342 I915_OA_FORMAT_C4_B8, 1343 1344 I915_OA_FORMAT_MAX /* non-ABI */ 1345 }; 1346 1347 enum drm_i915_perf_property_id { 1348 /** 1349 * Open the stream for a specific context handle (as used with 1350 * execbuffer2). A stream opened for a specific context this way 1351 * won't typically require root privileges. 1352 */ 1353 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 1354 1355 /** 1356 * A value of 1 requests the inclusion of raw OA unit reports as 1357 * part of stream samples. 1358 */ 1359 DRM_I915_PERF_PROP_SAMPLE_OA, 1360 1361 /** 1362 * The value specifies which set of OA unit metrics should be 1363 * be configured, defining the contents of any OA unit reports. 1364 */ 1365 DRM_I915_PERF_PROP_OA_METRICS_SET, 1366 1367 /** 1368 * The value specifies the size and layout of OA unit reports. 1369 */ 1370 DRM_I915_PERF_PROP_OA_FORMAT, 1371 1372 /** 1373 * Specifying this property implicitly requests periodic OA unit 1374 * sampling and (at least on Haswell) the sampling frequency is derived 1375 * from this exponent as follows: 1376 * 1377 * 80ns * 2^(period_exponent + 1) 1378 */ 1379 DRM_I915_PERF_PROP_OA_EXPONENT, 1380 1381 DRM_I915_PERF_PROP_MAX /* non-ABI */ 1382 }; 1383 1384 struct drm_i915_perf_open_param { 1385 __u32 flags; 1386 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) 1387 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) 1388 #define I915_PERF_FLAG_DISABLED (1<<2) 1389 1390 /** The number of u64 (id, value) pairs */ 1391 __u32 num_properties; 1392 1393 /** 1394 * Pointer to array of u64 (id, value) pairs configuring the stream 1395 * to open. 1396 */ 1397 __u64 properties_ptr; 1398 }; 1399 1400 /** 1401 * Enable data capture for a stream that was either opened in a disabled state 1402 * via I915_PERF_FLAG_DISABLED or was later disabled via 1403 * I915_PERF_IOCTL_DISABLE. 1404 * 1405 * It is intended to be cheaper to disable and enable a stream than it may be 1406 * to close and re-open a stream with the same configuration. 1407 * 1408 * It's undefined whether any pending data for the stream will be lost. 1409 */ 1410 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 1411 1412 /** 1413 * Disable data capture for a stream. 1414 * 1415 * It is an error to try and read a stream that is disabled. 1416 */ 1417 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 1418 1419 /** 1420 * Common to all i915 perf records 1421 */ 1422 struct drm_i915_perf_record_header { 1423 __u32 type; 1424 __u16 pad; 1425 __u16 size; 1426 }; 1427 1428 enum drm_i915_perf_record_type { 1429 1430 /** 1431 * Samples are the work horse record type whose contents are extensible 1432 * and defined when opening an i915 perf stream based on the given 1433 * properties. 1434 * 1435 * Boolean properties following the naming convention 1436 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in 1437 * every sample. 1438 * 1439 * The order of these sample properties given by userspace has no 1440 * affect on the ordering of data within a sample. The order is 1441 * documented here. 1442 * 1443 * struct { 1444 * struct drm_i915_perf_record_header header; 1445 * 1446 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA 1447 * }; 1448 */ 1449 DRM_I915_PERF_RECORD_SAMPLE = 1, 1450 1451 /* 1452 * Indicates that one or more OA reports were not written by the 1453 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT 1454 * command collides with periodic sampling - which would be more likely 1455 * at higher sampling frequencies. 1456 */ 1457 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 1458 1459 /** 1460 * An error occurred that resulted in all pending OA reports being lost. 1461 */ 1462 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 1463 1464 DRM_I915_PERF_RECORD_MAX /* non-ABI */ 1465 }; 1466 1467 #if defined(__cplusplus) 1468 } 1469 #endif 1470 1471 #endif /* _I915_DRM_H_ */ 1472