1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_HXGE_HXGE_COMMON_IMPL_H
27 #define	_SYS_HXGE_HXGE_COMMON_IMPL_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #define	HPI_REGH(hpi_handle)		(hpi_handle.regh)
34 #define	HPI_REGP(hpi_handle)		(hpi_handle.regp)
35 
36 #define		NO_DEBUG	0x0000000000000000ULL
37 #define		RX_CTL		0x0000000000000001ULL
38 #define		TX_CTL		0x0000000000000002ULL
39 #define		OBP_CTL		0x0000000000000004ULL
40 #define		VPD_CTL		0x0000000000000008ULL
41 #define		DDI_CTL		0x0000000000000010ULL
42 #define		MEM_CTL		0x0000000000000020ULL
43 #define		IOC_CTL		0x0000000000000040ULL
44 #define		MOD_CTL		0x0000000000000080ULL
45 #define		DMA_CTL		0x0000000000000100ULL
46 #define		STR_CTL		0x0000000000000200ULL
47 #define		INT_CTL		0x0000000000000400ULL
48 #define		SYSERR_CTL	0x0000000000000800ULL
49 #define		KST_CTL		0x0000000000001000ULL
50 #define		FCRAM_CTL	0x0000000000002000ULL
51 #define		MAC_CTL		0x0000000000004000ULL
52 #define		DMA2_CTL	0x0000000000008000ULL
53 #define		RX2_CTL		0x0000000000010000ULL
54 #define		TX2_CTL		0x0000000000020000ULL
55 #define		MEM2_CTL	0x0000000000040000ULL
56 #define		MEM3_CTL	0x0000000000080000ULL
57 #define		NEMO_CTL	0x0000000000100000ULL
58 #define		NDD_CTL		0x0000000000200000ULL
59 #define		NDD2_CTL	0x0000000000400000ULL
60 #define		PFC_CTL		0x0000000000800000ULL
61 #define		CFG_CTL		0x0000000001000000ULL
62 #define		CFG2_CTL	0x0000000002000000ULL
63 #define		VIR_CTL		0x0000000004000000ULL
64 #define		VIR2_CTL	0x0000000008000000ULL
65 #define		HXGE_NOTE	0x0000000010000000ULL
66 #define		HXGE_ERR_CTL	0x0000000020000000ULL
67 #define		MAC_INT_CTL	0x0000000040000000ULL
68 #define		RX_INT_CTL	0x0000000080000000ULL
69 #define		TX_ERR_CTL	0x0000000100000000ULL
70 #define		DDI_INT_CTL	0x0000000200000000ULL
71 #define		DLADM_CTL	0x0000000400000000ULL
72 #define		DUMP_ALWAYS	0x2000000000000000ULL
73 
74 /* HPI Debug and Error defines */
75 #define		HPI_RDC_CTL	0x0000000000000001ULL
76 #define		HPI_TDC_CTL	0x0000000000000002ULL
77 #define		HPI_VMAC_CTL	0x0000000000000004ULL
78 #define		HPI_PFC_CTL	0x0000000000000008ULL
79 #define		HPI_VIR_CTL	0x0000000000000010ULL
80 #define		HPI_PIO_CTL	0x0000000000000020ULL
81 #define		HPI_VIO_CTL	0x0000000000000040ULL
82 #define		HPI_REG_CTL	0x0000000000000080ULL
83 #define		HPI_ERR_CTL	0x0000000000000100ULL
84 
85 #include <sys/types.h>
86 #include <sys/ddi.h>
87 #include <sys/sunddi.h>
88 #include <sys/dditypes.h>
89 #include <sys/ethernet.h>
90 
91 #ifdef HXGE_DEBUG
92 #define	HXGE_DEBUG_MSG(params) hxge_debug_msg params
93 #else
94 #define	HXGE_DEBUG_MSG(params)
95 #endif
96 
97 #define	HXGE_ERROR_MSG(params)	hxge_debug_msg params
98 
99 typedef kmutex_t			hxge_os_mutex_t;
100 typedef	krwlock_t			hxge_os_rwlock_t;
101 
102 typedef	dev_info_t			hxge_dev_info_t;
103 typedef	ddi_iblock_cookie_t 		hxge_intr_cookie_t;
104 
105 typedef ddi_acc_handle_t		hxge_os_acc_handle_t;
106 typedef	hxge_os_acc_handle_t		hpi_reg_handle_t;
107 #if defined(__i386)
108 typedef	uint32_t			hpi_reg_ptr_t;
109 #else
110 typedef	uint64_t			hpi_reg_ptr_t;
111 #endif
112 
113 typedef ddi_dma_handle_t		hxge_os_dma_handle_t;
114 typedef struct _hxge_dma_common_t	hxge_os_dma_common_t;
115 typedef struct _hxge_block_mv_t		hxge_os_block_mv_t;
116 typedef frtn_t				hxge_os_frtn_t;
117 
118 #define	HXGE_MUTEX_DRIVER		MUTEX_DRIVER
119 #define	MUTEX_INIT(lock, name, type, arg)	\
120 					mutex_init(lock, name, type, arg)
121 #define	MUTEX_ENTER(lock)		mutex_enter(lock)
122 #define	MUTEX_TRY_ENTER(lock)		mutex_tryenter(lock)
123 #define	MUTEX_EXIT(lock)		mutex_exit(lock)
124 #define	MUTEX_DESTROY(lock)		mutex_destroy(lock)
125 
126 #define	RW_INIT(lock, name, type, arg)	rw_init(lock, name, type, arg)
127 #define	RW_ENTER_WRITER(lock)		rw_enter(lock, RW_WRITER)
128 #define	RW_ENTER_READER(lock)		rw_enter(lock, RW_READER)
129 #define	RW_TRY_ENTER(lock, type)	rw_tryenter(lock, type)
130 #define	RW_EXIT(lock)			rw_exit(lock)
131 #define	RW_DESTROY(lock)		rw_destroy(lock)
132 #define	KMEM_ALLOC(size, flag)		kmem_alloc(size, flag)
133 #define	KMEM_ZALLOC(size, flag)		kmem_zalloc(size, flag)
134 #define	KMEM_FREE(buf, size)		kmem_free(buf, size)
135 
136 #define	HXGE_DELAY(microseconds)	 (drv_usecwait(microseconds))
137 
138 /*
139  * HXGE_HPI_PIO_READ32 and HXGE_HPI_PIO_READ64 should not be called directly
140  * on 32 bit platforms
141  */
142 #define	HXGE_HPI_PIO_READ32(hpi_handle, offset)		\
143 	(ddi_get32(HPI_REGH(hpi_handle),		\
144 	(uint32_t *)(HPI_REGP(hpi_handle) + offset)))
145 
146 #if defined(__i386)
147 #define	HXGE_HPI_PIO_READ64(hpi_handle, offset)		\
148 	(ddi_get64(HPI_REGH(hpi_handle),		\
149 	(uint64_t *)(HPI_REGP(hpi_handle) + (uint32_t)offset)))
150 #else
151 #define	HXGE_HPI_PIO_READ64(hpi_handle, offset)		\
152 	(ddi_get64(HPI_REGH(hpi_handle),		\
153 	(uint64_t *)(HPI_REGP(hpi_handle) + offset)))
154 #endif
155 
156 #if defined(__i386)
157 
158 #define	HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data) {	\
159 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
160 	ddi_put32(HPI_REGH(hpi_handle),				\
161 	    (uint32_t *)(HPI_REGP(hpi_handle) +			\
162 	    (uint32_t)offset), data);				\
163 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
164 }
165 #define	HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data) {	\
166 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
167 	ddi_put64(HPI_REGH(hpi_handle),				\
168 	    (uint64_t *)(HPI_REGP(hpi_handle) +			\
169 	    (uint32_t)offset), data);				\
170 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
171 }
172 #define	HXGE_MEM_PIO_READ64(hpi_handle, val_p) {		\
173 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
174 	*(val_p) = ddi_get64(HPI_REGH(hpi_handle),		\
175 	    (uint64_t *)HPI_REGP(hpi_handle));			\
176 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
177 }
178 #define	HXGE_MEM_PIO_WRITE64(hpi_handle, data) {		\
179 	MUTEX_ENTER(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
180 	ddi_put64(HPI_REGH(hpi_handle),				\
181 	    (uint64_t *)HPI_REGP(hpi_handle), data);		\
182 	MUTEX_EXIT(&((hxge_t *)hpi_handle.hxgep)->pio_lock);	\
183 }
184 #define	HXGE_REG_RD64(handle, offset, val_p) {			\
185 	MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock);	\
186 	*(val_p) = HXGE_HPI_PIO_READ64(handle, offset);		\
187 	MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock);	\
188 }
189 #define	HXGE_REG_RD32(handle, offset, val_p) {			\
190 	MUTEX_ENTER(&((hxge_t *)handle.hxgep)->pio_lock);	\
191 	*(val_p) = HXGE_HPI_PIO_READ32(handle, offset);		\
192 	MUTEX_EXIT(&((hxge_t *)handle.hxgep)->pio_lock);	\
193 }
194 
195 #else
196 
197 #define	HXGE_HPI_PIO_WRITE32(hpi_handle, offset, data)		\
198 	(ddi_put32(HPI_REGH(hpi_handle),			\
199 	(uint32_t *)(HPI_REGP(hpi_handle) + offset), data))
200 #define	HXGE_HPI_PIO_WRITE64(hpi_handle, offset, data)		\
201 	(ddi_put64(HPI_REGH(hpi_handle),			\
202 	(uint64_t *)(HPI_REGP(hpi_handle) + offset), data))
203 #define	HXGE_MEM_PIO_READ64(hpi_handle, val_p) {		\
204 	*(val_p) = ddi_get64(HPI_REGH(hpi_handle),		\
205 		(uint64_t *)HPI_REGP(hpi_handle));		\
206 }
207 #define	HXGE_MEM_PIO_WRITE64(hpi_handle, data)			\
208 	(ddi_put64(HPI_REGH(hpi_handle),			\
209 		(uint64_t *)HPI_REGP(hpi_handle), data))
210 #define	HXGE_REG_RD64(handle, offset, val_p) {			\
211 	*(val_p) = HXGE_HPI_PIO_READ64(handle, offset);		\
212 }
213 #define	HXGE_REG_RD32(handle, offset, val_p) {			\
214 	*(val_p) = HXGE_HPI_PIO_READ32(handle, offset);		\
215 }
216 
217 #endif
218 
219 #define	HXGE_REG_WR64(handle, offset, val) {			\
220 	HXGE_HPI_PIO_WRITE64(handle, (offset), (val));		\
221 }
222 #define	HXGE_REG_WR32(handle, offset, val) {			\
223 	HXGE_HPI_PIO_WRITE32(handle, (offset), (val));		\
224 }
225 
226 #define	FM_SERVICE_RESTORED(hxgep)				\
227 	if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities))		\
228 		ddi_fm_service_impact(hxgep->dip, DDI_SERVICE_RESTORED)
229 #define	HXGE_FM_REPORT_ERROR(hxgep, chan, ereport_id)		\
230 	if (DDI_FM_EREPORT_CAP(hxgep->fm_capabilities))		\
231 		hxge_fm_report_error(hxgep, chan, ereport_id)
232 
233 #ifdef	__cplusplus
234 }
235 #endif
236 
237 #endif	/* _SYS_HXGE_HXGE_COMMON_IMPL_H */
238