1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #ifndef _SYS_NIAGARA2REGS_H
26 #define	_SYS_NIAGARA2REGS_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define	MB(n)	((n) * 1024 * 1024)
33 
34 #define	L2CACHE_SIZE		MB(4)
35 #define	L2CACHE_LINESIZE	64
36 #define	L2CACHE_ASSOCIATIVITY	16
37 
38 #define	NIAGARA2_HSVC_MAJOR	1
39 #define	NIAGARA2_HSVC_MINOR	0
40 
41 #define	VFALLS_HSVC_MAJOR	1
42 #define	VFALLS_HSVC_MINOR	0
43 
44 #define	KT_HSVC_MAJOR		1
45 #define	KT_HSVC_MINOR		0
46 
47 #ifdef KT_IMPL
48 
49 /* Sample PIC overflow range is -2 to -1 */
50 #define	SAMPLE_PIC_IN_OV_RANGE(x)	(((uint32_t)x >= 0xfffffffe) ? 1 : 0)
51 
52 #endif
53 
54 /* PIC overflow range is -16 to -1 */
55 #define	PIC_IN_OV_RANGE(x)	(((uint32_t)x >= 0xfffffff0) ? 1 : 0)
56 
57 /*
58  * SPARC Performance Instrumentation Counter
59  */
60 #define	PIC0_MASK	(((uint64_t)1 << 32) - 1)	/* pic0 in bits 31:0 */
61 #define	PIC1_SHIFT	32				/* pic1 in bits 64:32 */
62 
63 /*
64  * SPARC Performance Control Register
65  */
66 #define	CPC_PCR_PRIV_SHIFT	0
67 #define	CPC_PCR_ST_SHIFT	1
68 #define	CPC_PCR_UT_SHIFT	2
69 
70 #define	CPC_PCR_HT_SHIFT	3
71 #define	CPC_PCR_HT		(1ull << CPC_PCR_HT_SHIFT)
72 
73 #define	CPC_PCR_TOE0_SHIFT	4
74 #define	CPC_PCR_TOE1_SHIFT	5
75 #define	CPC_PCR_TOE0		(1ull << CPC_PCR_TOE0_SHIFT)
76 #define	CPC_PCR_TOE1		(1ull << CPC_PCR_TOE1_SHIFT)
77 
78 #define	CPC_PCR_PIC0_SHIFT	6
79 #define	CPC_PCR_PIC1_SHIFT	19
80 #define	CPC_PCR_PIC0_MASK	UINT64_C(0xfff)
81 #define	CPC_PCR_PIC1_MASK	UINT64_C(0xfff)
82 
83 #define	CPC_PCR_OV0_SHIFT	18
84 #define	CPC_PCR_OV1_SHIFT	30
85 #define	CPC_PCR_OV0_MASK	UINT64_C(0x40000)
86 #define	CPC_PCR_OV1_MASK	UINT64_C(0x80000000)
87 
88 #if defined(KT_IMPL)
89 
90 #define	CPC_PCR_SAMPLE_MODE_SHIFT	32
91 #define	CPC_PCR_SAMPLE_MODE_MASK	(1ull << CPC_PCR_SAMPLE_MODE_SHIFT)
92 
93 #endif
94 
95 #define	CPC_PCR_HOLDOV0_SHIFT	62
96 #define	CPC_PCR_HOLDOV1_SHIFT	63
97 #define	CPC_PCR_HOLDOV0		(1ull << CPC_PCR_HOLDOV0_SHIFT)
98 #define	CPC_PCR_HOLDOV1		(1ull << CPC_PCR_HOLDOV1_SHIFT)
99 
100 /*
101  * Hypervisor FAST_TRAP API function numbers to get/set DRAM
102  * performance counters for Niagara2
103  */
104 #define	HV_NIAGARA2_GETPERF		0x104
105 #define	HV_NIAGARA2_SETPERF		0x105
106 
107 /*
108  * Hypervisor FAST_TRAP API function numbers to get/set DRAM
109  * performance counters for Victoria Falls
110  */
111 #define	HV_VFALLS_GETPERF		0x106
112 #define	HV_VFALLS_SETPERF		0x107
113 
114 /*
115  * Hypervisor FAST_TRAP API function numbers to get/set DRAM
116  * performance counters for KT
117  */
118 #define	HV_KT_GETPERF			0x122
119 #define	HV_KT_SETPERF			0x123
120 
121 #if defined(KT_IMPL)
122 
123 /*
124  * KT DRAM performance counters
125  */
126 #define	DRAM_PIC0_SEL_SHIFT	0x0
127 #define	DRAM_PIC1_SEL_SHIFT	0x4
128 
129 #define	DRAM_PIC0_SHIFT		0x0
130 #define	DRAM_PIC0_MASK		0x7fffffff
131 #define	DRAM_PIC1_SHIFT		0x20
132 #define	DRAM_PIC1_MASK		0x7fffffff
133 
134 #else
135 
136 /*
137  * Niagara2 and VF DRAM performance counters
138  */
139 #define	DRAM_PIC0_SEL_SHIFT	0x4
140 #define	DRAM_PIC1_SEL_SHIFT	0x0
141 
142 #define	DRAM_PIC0_SHIFT		0x20
143 #define	DRAM_PIC0_MASK		0x7fffffff
144 #define	DRAM_PIC1_SHIFT		0x0
145 #define	DRAM_PIC1_MASK		0x7fffffff
146 
147 #endif
148 
149 #if defined(NIAGARA2_IMPL)
150 /*
151  * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF
152  * and HV_NIAGARA2_SETPERF for Niagara2
153  */
154 #define	DRAM_BANKS		0x4
155 
156 #define	HV_SPARC_CTL		0x0
157 #define	HV_DRAM_CTL0		0x1
158 #define	HV_DRAM_COUNT0		0x2
159 #define	HV_DRAM_CTL1		0x3
160 #define	HV_DRAM_COUNT1		0x4
161 #define	HV_DRAM_CTL2		0x5
162 #define	HV_DRAM_COUNT2		0x6
163 #define	HV_DRAM_CTL3		0x7
164 #define	HV_DRAM_COUNT3		0x8
165 
166 #elif defined(VFALLS_IMPL)
167 /*
168  * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF
169  * and HV_VFALLS_SETPERF for Victoria Falls
170  * Support for 4-node configuration
171  */
172 #define	DRAM_BANKS		0x8
173 
174 #define	HV_SPARC_CTL		0x0
175 #define	HV_L2_CTL		0x1
176 #define	HV_DRAM_CTL0		0x2
177 #define	HV_DRAM_COUNT0		0x3
178 #define	HV_DRAM_CTL1		0x4
179 #define	HV_DRAM_COUNT1		0x5
180 #define	HV_DRAM_CTL2		0x6
181 #define	HV_DRAM_COUNT2		0x7
182 #define	HV_DRAM_CTL3		0x8
183 #define	HV_DRAM_COUNT3		0x9
184 #define	HV_DRAM_CTL4		0xa
185 #define	HV_DRAM_COUNT4		0xb
186 #define	HV_DRAM_CTL5		0xc
187 #define	HV_DRAM_COUNT5		0xd
188 #define	HV_DRAM_CTL6		0xe
189 #define	HV_DRAM_COUNT6		0xf
190 #define	HV_DRAM_CTL7		0x10
191 #define	HV_DRAM_COUNT7		0x11
192 
193 #define	L2_CTL_MASK		0x3
194 #define	SL3_MASK		0x300
195 #define	SL_MASK			0xf00
196 
197 #elif defined(KT_IMPL)
198 /*
199  * SPARC/DRAM performance counter register numbers for HV_KT_GETPERF
200  * and HV_KT_SETPERF for KT
201  * Support for 4-node configuration
202  */
203 
204 #define	DRAM_BANKS		0x8
205 
206 #define	HV_SPARC_CTL		0x0
207 #define	HV_L2_CTL		0x1
208 #define	HV_DRAM_CTL0		0x2
209 #define	HV_DRAM_COUNT0		0x3
210 #define	HV_DRAM_CTL1		0x5
211 #define	HV_DRAM_COUNT1		0x6
212 #define	HV_DRAM_CTL2		0x8
213 #define	HV_DRAM_COUNT2		0x9
214 #define	HV_DRAM_CTL3		0xb
215 #define	HV_DRAM_COUNT3		0xc
216 #define	HV_DRAM_CTL4		0xe
217 #define	HV_DRAM_COUNT4		0xf
218 #define	HV_DRAM_CTL5		0x11
219 #define	HV_DRAM_COUNT5		0x12
220 #define	HV_DRAM_CTL6		0x14
221 #define	HV_DRAM_COUNT6		0x15
222 #define	HV_DRAM_CTL7		0x17
223 #define	HV_DRAM_COUNT7		0x18
224 
225 #define	L2_CTL_MASK		0x3
226 #define	SL3_MASK		0x300
227 #define	SL_MASK			0xf00
228 
229 #endif
230 
231 #ifdef VFALLS_IMPL
232 /*
233  * Performance counters for Zambezi.  Zambezi is only supported with
234  * Victoria Falls (UltraSPARC-T2+).
235  */
236 
237 #define	ZAMBEZI_PIC0_SEL_SHIFT		0x0
238 #define	ZAMBEZI_PIC1_SEL_SHIFT		0x8
239 
240 #define	ZAMBEZI_LPU_COUNTERS		0x10
241 #define	ZAMBEZI_GPD_COUNTERS		0x4
242 #define	ZAMBEZI_ASU_COUNTERS		0x4
243 
244 #define	HV_ZAM0_LPU_A_PCR		0x12
245 #define	HV_ZAM0_LPU_A_PIC0		0x13
246 #define	HV_ZAM0_LPU_A_PIC1		0x14
247 #define	HV_ZAM0_LPU_B_PCR		0x15
248 #define	HV_ZAM0_LPU_B_PIC0		0x16
249 #define	HV_ZAM0_LPU_B_PIC1		0x17
250 #define	HV_ZAM0_LPU_C_PCR		0x18
251 #define	HV_ZAM0_LPU_C_PIC0		0x19
252 #define	HV_ZAM0_LPU_C_PIC1		0x1a
253 #define	HV_ZAM0_LPU_D_PCR		0x1b
254 #define	HV_ZAM0_LPU_D_PIC0		0x1c
255 #define	HV_ZAM0_LPU_D_PIC1		0x1d
256 #define	HV_ZAM0_GPD_PCR			0x1e
257 #define	HV_ZAM0_GPD_PIC0		0x1f
258 #define	HV_ZAM0_GPD_PIC1		0x20
259 #define	HV_ZAM0_ASU_PCR			0x21
260 #define	HV_ZAM0_ASU_PIC0		0x22
261 #define	HV_ZAM0_ASU_PIC1		0x23
262 
263 #define	HV_ZAM1_LPU_A_PCR		0x24
264 #define	HV_ZAM1_LPU_A_PIC0		0x25
265 #define	HV_ZAM1_LPU_A_PIC1		0x26
266 #define	HV_ZAM1_LPU_B_PCR		0x27
267 #define	HV_ZAM1_LPU_B_PIC0		0x28
268 #define	HV_ZAM1_LPU_B_PIC1		0x29
269 #define	HV_ZAM1_LPU_C_PCR		0x2a
270 #define	HV_ZAM1_LPU_C_PIC0		0x2b
271 #define	HV_ZAM1_LPU_C_PIC1		0x2c
272 #define	HV_ZAM1_LPU_D_PCR		0x2d
273 #define	HV_ZAM1_LPU_D_PIC0		0x2e
274 #define	HV_ZAM1_LPU_D_PIC1		0x2f
275 #define	HV_ZAM1_GPD_PCR			0x30
276 #define	HV_ZAM1_GPD_PIC0		0x31
277 #define	HV_ZAM1_GPD_PIC1		0x32
278 #define	HV_ZAM1_ASU_PCR			0x33
279 #define	HV_ZAM1_ASU_PIC0		0x34
280 #define	HV_ZAM1_ASU_PIC1		0x35
281 
282 #define	HV_ZAM2_LPU_A_PCR		0x36
283 #define	HV_ZAM2_LPU_A_PIC0		0x37
284 #define	HV_ZAM2_LPU_A_PIC1		0x38
285 #define	HV_ZAM2_LPU_B_PCR		0x39
286 #define	HV_ZAM2_LPU_B_PIC0		0x3a
287 #define	HV_ZAM2_LPU_B_PIC1		0x3b
288 #define	HV_ZAM2_LPU_C_PCR		0x3c
289 #define	HV_ZAM2_LPU_C_PIC0		0x3d
290 #define	HV_ZAM2_LPU_C_PIC1		0x3e
291 #define	HV_ZAM2_LPU_D_PCR		0x3f
292 #define	HV_ZAM2_LPU_D_PIC0		0x40
293 #define	HV_ZAM2_LPU_D_PIC1		0x41
294 #define	HV_ZAM2_GPD_PCR			0x42
295 #define	HV_ZAM2_GPD_PIC0		0x43
296 #define	HV_ZAM2_GPD_PIC1		0x44
297 #define	HV_ZAM2_ASU_PCR			0x45
298 #define	HV_ZAM2_ASU_PIC0		0x46
299 #define	HV_ZAM2_ASU_PIC1		0x47
300 
301 #define	HV_ZAM3_LPU_A_PCR		0x48
302 #define	HV_ZAM3_LPU_A_PIC0		0x49
303 #define	HV_ZAM3_LPU_A_PIC1		0x4a
304 #define	HV_ZAM3_LPU_B_PCR		0x4b
305 #define	HV_ZAM3_LPU_B_PIC0		0x4c
306 #define	HV_ZAM3_LPU_B_PIC1		0x4d
307 #define	HV_ZAM3_LPU_C_PCR		0x4e
308 #define	HV_ZAM3_LPU_C_PIC0		0x4f
309 #define	HV_ZAM3_LPU_C_PIC1		0x50
310 #define	HV_ZAM3_LPU_D_PCR		0x51
311 #define	HV_ZAM3_LPU_D_PIC0		0x52
312 #define	HV_ZAM3_LPU_D_PIC1		0x53
313 #define	HV_ZAM3_GPD_PCR			0x54
314 #define	HV_ZAM3_GPD_PIC0		0x55
315 #define	HV_ZAM3_GPD_PIC1		0x56
316 #define	HV_ZAM3_ASU_PCR			0x57
317 #define	HV_ZAM3_ASU_PIC0		0x58
318 #define	HV_ZAM3_ASU_PIC1		0x59
319 
320 #endif
321 
322 #ifndef _ASM
323 /*
324  * prototypes for hypervisor interface to get/set SPARC and DRAM
325  * performance counters
326  */
327 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val);
328 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val);
329 #endif
330 
331 #ifdef __cplusplus
332 }
333 #endif
334 
335 #endif /* _SYS_NIAGARA2REGS_H */
336