xref: /illumos-gate/usr/src/cmd/bhyve/hdac_reg.h (revision 32640292)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef _HDAC_REG_H_
30 #define _HDAC_REG_H_
31 
32 /****************************************************************************
33  * HDA Controller Register Set
34  ****************************************************************************/
35 #define HDAC_GCAP	0x00	/* 2 - Global Capabilities*/
36 #define HDAC_VMIN	0x02	/* 1 - Minor Version */
37 #define HDAC_VMAJ	0x03	/* 1 - Major Version */
38 #define	HDAC_OUTPAY	0x04	/* 2 - Output Payload Capability */
39 #define HDAC_INPAY	0x06	/* 2 - Input Payload Capability */
40 #define HDAC_GCTL	0x08	/* 4 - Global Control */
41 #define HDAC_WAKEEN	0x0c	/* 2 - Wake Enable */
42 #define HDAC_STATESTS	0x0e	/* 2 - State Change Status */
43 #define HDAC_GSTS	0x10	/* 2 - Global Status */
44 #define HDAC_OUTSTRMPAY	0x18	/* 2 - Output Stream Payload Capability */
45 #define HDAC_INSTRMPAY	0x1a	/* 2 - Input Stream Payload Capability */
46 #define HDAC_INTCTL	0x20	/* 4 - Interrupt Control */
47 #define HDAC_INTSTS	0x24	/* 4 - Interrupt Status */
48 #define HDAC_WALCLK	0x30	/* 4 - Wall Clock Counter */
49 #define HDAC_SSYNC	0x38	/* 4 - Stream Synchronization */
50 #define HDAC_CORBLBASE	0x40	/* 4 - CORB Lower Base Address */
51 #define HDAC_CORBUBASE	0x44	/* 4 - CORB Upper Base Address */
52 #define HDAC_CORBWP	0x48	/* 2 - CORB Write Pointer */
53 #define HDAC_CORBRP	0x4a	/* 2 - CORB Read Pointer */
54 #define HDAC_CORBCTL	0x4c	/* 1 - CORB Control */
55 #define HDAC_CORBSTS	0x4d	/* 1 - CORB Status */
56 #define HDAC_CORBSIZE	0x4e	/* 1 - CORB Size */
57 #define HDAC_RIRBLBASE	0x50	/* 4 - RIRB Lower Base Address */
58 #define HDAC_RIRBUBASE	0x54	/* 4 - RIRB Upper Base Address */
59 #define HDAC_RIRBWP	0x58	/* 2 - RIRB Write Pointer */
60 #define HDAC_RINTCNT	0x5a	/* 2 - Response Interrupt Count */
61 #define HDAC_RIRBCTL	0x5c	/* 1 - RIRB Control */
62 #define HDAC_RIRBSTS	0x5d	/* 1 - RIRB Status */
63 #define HDAC_RIRBSIZE	0x5e	/* 1 - RIRB Size */
64 #define HDAC_ICOI	0x60	/* 4 - Immediate Command Output Interface */
65 #define HDAC_ICII	0x64	/* 4 - Immediate Command Input Interface */
66 #define HDAC_ICIS	0x68	/* 2 - Immediate Command Status */
67 #define HDAC_DPIBLBASE	0x70	/* 4 - DMA Position Buffer Lower Base */
68 #define HDAC_DPIBUBASE	0x74	/* 4 - DMA Position Buffer Upper Base */
69 #define HDAC_SDCTL0	0x80	/* 3 - Stream Descriptor Control */
70 #define HDAC_SDCTL1	0x81	/* 3 - Stream Descriptor Control */
71 #define HDAC_SDCTL2	0x82	/* 3 - Stream Descriptor Control */
72 #define HDAC_SDSTS	0x83	/* 1 - Stream Descriptor Status */
73 #define HDAC_SDLPIB	0x84	/* 4 - Link Position in Buffer */
74 #define HDAC_SDCBL	0x88	/* 4 - Cyclic Buffer Length */
75 #define HDAC_SDLVI	0x8C	/* 2 - Last Valid Index */
76 #define HDAC_SDFIFOS	0x90	/* 2 - FIFOS */
77 #define HDAC_SDFMT	0x92	/* 2 - fmt */
78 #define HDAC_SDBDPL	0x98	/* 4 - Buffer Descriptor Pointer Lower Base */
79 #define HDAC_SDBDPU	0x9C	/* 4 - Buffer Descriptor Pointer Upper Base */
80 
81 #define _HDAC_ISDOFFSET(n, iss, oss)	(0x80 + ((n) * 0x20))
82 #define _HDAC_ISDCTL(n, iss, oss)	(0x00 + _HDAC_ISDOFFSET(n, iss, oss))
83 #define _HDAC_ISDSTS(n, iss, oss)	(0x03 + _HDAC_ISDOFFSET(n, iss, oss))
84 #define _HDAC_ISDPICB(n, iss, oss)	(0x04 + _HDAC_ISDOFFSET(n, iss, oss))
85 #define _HDAC_ISDCBL(n, iss, oss)	(0x08 + _HDAC_ISDOFFSET(n, iss, oss))
86 #define _HDAC_ISDLVI(n, iss, oss)	(0x0c + _HDAC_ISDOFFSET(n, iss, oss))
87 #define _HDAC_ISDFIFOD(n, iss, oss)	(0x10 + _HDAC_ISDOFFSET(n, iss, oss))
88 #define _HDAC_ISDFMT(n, iss, oss)	(0x12 + _HDAC_ISDOFFSET(n, iss, oss))
89 #define _HDAC_ISDBDPL(n, iss, oss)	(0x18 + _HDAC_ISDOFFSET(n, iss, oss))
90 #define _HDAC_ISDBDPU(n, iss, oss)	(0x1c + _HDAC_ISDOFFSET(n, iss, oss))
91 
92 #define _HDAC_OSDOFFSET(n, iss, oss)	(0x80 + ((iss) * 0x20) + ((n) * 0x20))
93 #define _HDAC_OSDCTL(n, iss, oss)	(0x00 + _HDAC_OSDOFFSET(n, iss, oss))
94 #define _HDAC_OSDSTS(n, iss, oss)	(0x03 + _HDAC_OSDOFFSET(n, iss, oss))
95 #define _HDAC_OSDPICB(n, iss, oss)	(0x04 + _HDAC_OSDOFFSET(n, iss, oss))
96 #define _HDAC_OSDCBL(n, iss, oss)	(0x08 + _HDAC_OSDOFFSET(n, iss, oss))
97 #define _HDAC_OSDLVI(n, iss, oss)	(0x0c + _HDAC_OSDOFFSET(n, iss, oss))
98 #define _HDAC_OSDFIFOD(n, iss, oss)	(0x10 + _HDAC_OSDOFFSET(n, iss, oss))
99 #define _HDAC_OSDFMT(n, iss, oss)	(0x12 + _HDAC_OSDOFFSET(n, iss, oss))
100 #define _HDAC_OSDBDPL(n, iss, oss)	(0x18 + _HDAC_OSDOFFSET(n, iss, oss))
101 #define _HDAC_OSDBDPU(n, iss, oss)	(0x1c + _HDAC_OSDOFFSET(n, iss, oss))
102 
103 #define _HDAC_BSDOFFSET(n, iss, oss)					\
104 	(0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))
105 #define _HDAC_BSDCTL(n, iss, oss)	(0x00 + _HDAC_BSDOFFSET(n, iss, oss))
106 #define _HDAC_BSDSTS(n, iss, oss)	(0x03 + _HDAC_BSDOFFSET(n, iss, oss))
107 #define _HDAC_BSDPICB(n, iss, oss)	(0x04 + _HDAC_BSDOFFSET(n, iss, oss))
108 #define _HDAC_BSDCBL(n, iss, oss)	(0x08 + _HDAC_BSDOFFSET(n, iss, oss))
109 #define _HDAC_BSDLVI(n, iss, oss)	(0x0c + _HDAC_BSDOFFSET(n, iss, oss))
110 #define _HDAC_BSDFIFOD(n, iss, oss)	(0x10 + _HDAC_BSDOFFSET(n, iss, oss))
111 #define _HDAC_BSDFMT(n, iss, oss)	(0x12 + _HDAC_BSDOFFSET(n, iss, oss))
112 #define _HDAC_BSDBDPL(n, iss, oss)	(0x18 + _HDAC_BSDOFFSET(n, iss, oss))
113 #define _HDAC_BSDBDBU(n, iss, oss)	(0x1c + _HDAC_BSDOFFSET(n, iss, oss))
114 
115 /****************************************************************************
116  * HDA Controller Register Fields
117  ****************************************************************************/
118 
119 /* GCAP - Global Capabilities */
120 #define HDAC_GCAP_64OK			0x0001
121 #define HDAC_GCAP_NSDO_MASK		0x0006
122 #define HDAC_GCAP_NSDO_SHIFT		1
123 #define HDAC_GCAP_BSS_MASK		0x00f8
124 #define HDAC_GCAP_BSS_SHIFT		3
125 #define HDAC_GCAP_ISS_MASK		0x0f00
126 #define HDAC_GCAP_ISS_SHIFT		8
127 #define HDAC_GCAP_OSS_MASK		0xf000
128 #define HDAC_GCAP_OSS_SHIFT		12
129 
130 #define HDAC_GCAP_NSDO_1SDO		0x00
131 #define HDAC_GCAP_NSDO_2SDO		0x02
132 #define HDAC_GCAP_NSDO_4SDO		0x04
133 
134 #define HDAC_GCAP_BSS(gcap)						\
135 	(((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)
136 #define HDAC_GCAP_ISS(gcap)						\
137 	(((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)
138 #define HDAC_GCAP_OSS(gcap)						\
139 	(((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)
140 #define HDAC_GCAP_NSDO(gcap)						\
141 	(((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT)
142 
143 /* GCTL - Global Control */
144 #define HDAC_GCTL_CRST			0x00000001
145 #define HDAC_GCTL_FCNTRL		0x00000002
146 #define HDAC_GCTL_UNSOL			0x00000100
147 
148 /* WAKEEN - Wake Enable */
149 #define HDAC_WAKEEN_SDIWEN_MASK		0x7fff
150 #define HDAC_WAKEEN_SDIWEN_SHIFT	0
151 
152 /* STATESTS - State Change Status */
153 #define HDAC_STATESTS_SDIWAKE_MASK	0x7fff
154 #define HDAC_STATESTS_SDIWAKE_SHIFT	0
155 
156 #define HDAC_STATESTS_SDIWAKE(statests, n)				\
157     (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >>			\
158     HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)
159 
160 /* GSTS - Global Status */
161 #define HDAC_GSTS_FSTS			0x0002
162 
163 /* INTCTL - Interrut Control */
164 #define HDAC_INTCTL_SIE_MASK		0x3fffffff
165 #define HDAC_INTCTL_SIE_SHIFT		0
166 #define HDAC_INTCTL_CIE			0x40000000
167 #define HDAC_INTCTL_GIE			0x80000000
168 
169 /* INTSTS - Interrupt Status */
170 #define HDAC_INTSTS_SIS_MASK		0x3fffffff
171 #define HDAC_INTSTS_SIS_SHIFT		0
172 #define HDAC_INTSTS_CIS			0x40000000
173 #define HDAC_INTSTS_GIS			0x80000000
174 
175 /* SSYNC - Stream Synchronization */
176 #define HDAC_SSYNC_SSYNC_MASK		0x3fffffff
177 #define HDAC_SSYNC_SSYNC_SHIFT		0
178 
179 /* CORBWP - CORB Write Pointer */
180 #define HDAC_CORBWP_CORBWP_MASK		0x00ff
181 #define HDAC_CORBWP_CORBWP_SHIFT	0
182 
183 /* CORBRP - CORB Read Pointer */
184 #define HDAC_CORBRP_CORBRP_MASK		0x00ff
185 #define HDAC_CORBRP_CORBRP_SHIFT	0
186 #define HDAC_CORBRP_CORBRPRST		0x8000
187 
188 /* CORBCTL - CORB Control */
189 #define HDAC_CORBCTL_CMEIE		0x01
190 #define HDAC_CORBCTL_CORBRUN		0x02
191 
192 /* CORBSTS - CORB Status */
193 #define HDAC_CORBSTS_CMEI		0x01
194 
195 /* CORBSIZE - CORB Size */
196 #define HDAC_CORBSIZE_CORBSIZE_MASK	0x03
197 #define HDAC_CORBSIZE_CORBSIZE_SHIFT	0
198 #define HDAC_CORBSIZE_CORBSZCAP_MASK	0xf0
199 #define HDAC_CORBSIZE_CORBSZCAP_SHIFT	4
200 
201 #define HDAC_CORBSIZE_CORBSIZE_2	0x00
202 #define HDAC_CORBSIZE_CORBSIZE_16	0x01
203 #define HDAC_CORBSIZE_CORBSIZE_256	0x02
204 
205 #define HDAC_CORBSIZE_CORBSZCAP_2	0x10
206 #define HDAC_CORBSIZE_CORBSZCAP_16	0x20
207 #define HDAC_CORBSIZE_CORBSZCAP_256	0x40
208 
209 #define HDAC_CORBSIZE_CORBSIZE(corbsize)				\
210     (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)
211 
212 /* RIRBWP - RIRB Write Pointer */
213 #define HDAC_RIRBWP_RIRBWP_MASK		0x00ff
214 #define HDAC_RIRBWP_RIRBWP_SHIFT	0
215 #define HDAC_RIRBWP_RIRBWPRST		0x8000
216 
217 /* RINTCTN - Response Interrupt Count */
218 #define HDAC_RINTCNT_MASK		0x00ff
219 #define HDAC_RINTCNT_SHIFT		0
220 
221 /* RIRBCTL - RIRB Control */
222 #define HDAC_RIRBCTL_RINTCTL		0x01
223 #define HDAC_RIRBCTL_RIRBDMAEN		0x02
224 #define HDAC_RIRBCTL_RIRBOIC		0x04
225 
226 /* RIRBSTS - RIRB Status */
227 #define HDAC_RIRBSTS_RINTFL		0x01
228 #define HDAC_RIRBSTS_RIRBOIS		0x04
229 
230 /* RIRBSIZE - RIRB Size */
231 #define HDAC_RIRBSIZE_RIRBSIZE_MASK	0x03
232 #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT	0
233 #define HDAC_RIRBSIZE_RIRBSZCAP_MASK	0xf0
234 #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT	4
235 
236 #define HDAC_RIRBSIZE_RIRBSIZE_2	0x00
237 #define HDAC_RIRBSIZE_RIRBSIZE_16	0x01
238 #define HDAC_RIRBSIZE_RIRBSIZE_256	0x02
239 
240 #define HDAC_RIRBSIZE_RIRBSZCAP_2	0x10
241 #define HDAC_RIRBSIZE_RIRBSZCAP_16	0x20
242 #define HDAC_RIRBSIZE_RIRBSZCAP_256	0x40
243 
244 #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize)				\
245     (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)
246 
247 /* DPLBASE - DMA Position Lower Base Address */
248 #define HDAC_DPLBASE_DPLBASE_MASK	0xffffff80
249 #define HDAC_DPLBASE_DPLBASE_SHIFT	7
250 #define HDAC_DPLBASE_DPLBASE_DMAPBE	0x00000001
251 
252 /* SDCTL - Stream Descriptor Control */
253 #define HDAC_SDCTL_SRST			0x000001
254 #define HDAC_SDCTL_RUN			0x000002
255 #define HDAC_SDCTL_IOCE			0x000004
256 #define HDAC_SDCTL_FEIE			0x000008
257 #define HDAC_SDCTL_DEIE			0x000010
258 #define HDAC_SDCTL2_STRIPE_MASK		0x03
259 #define HDAC_SDCTL2_STRIPE_SHIFT	0
260 #define HDAC_SDCTL2_TP			0x04
261 #define HDAC_SDCTL2_DIR			0x08
262 #define HDAC_SDCTL2_STRM_MASK		0xf0
263 #define HDAC_SDCTL2_STRM_SHIFT		4
264 
265 #define HDAC_SDSTS_DESE			(1 << 4)
266 #define HDAC_SDSTS_FIFOE		(1 << 3)
267 #define HDAC_SDSTS_BCIS			(1 << 2)
268 
269 #endif /* _HDAC_REG_H_ */
270