xref: /gfx-drm/usr/src/uts/intel/io/i915/i915_reg.h (revision 47dc10d7)
1 /*
2  * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
3  */
4 
5 /*
6  * Copyright (c) 2012, 2013, Intel Corporation.  All rights reserved.
7  */
8 
9 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the
14  * "Software"), to deal in the Software without restriction, including
15  * without limitation the rights to use, copy, modify, merge, publish,
16  * distribute, sub license, and/or sell copies of the Software, and to
17  * permit persons to whom the Software is furnished to do so, subject to
18  * the following conditions:
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
25  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
27  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
28  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31  */
32 
33 #ifndef _I915_REG_H_
34 #define _I915_REG_H_
35 
36 #define	GEN6_CONF_GMADR		0x18
37 #define	GEN6_GTT_BASE_MASK	0xfffff000
38 
39 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
40 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
41 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
42 
43 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
44 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
45 
46 #define I810_SMRAM_MISCC	0x70
47 #define I810_GFX_MEM_WIN_SIZE	0x00010000
48 #define I810_GFX_MEM_WIN_32M	0x00010000
49 /* Note: PGETBL_CTL2 has a different offset on G33. */
50 #define I965_PGETBL_CTL2	0x20c4
51 #define I965_PGETBL_SIZE_MASK	0x0000000e
52 #define I965_PGETBL_SIZE_512KB	(0 << 1)
53 #define I965_PGETBL_SIZE_256KB	(1 << 1)
54 #define I965_PGETBL_SIZE_128KB	(2 << 1)
55 #define I965_PGETBL_SIZE_1MB	(3 << 1)
56 #define I965_PGETBL_SIZE_2MB	(4 << 1)
57 #define I965_PGETBL_SIZE_1_5MB	(5 << 1)
58 #define G33_GMCH_SIZE_MASK	(3 << 8)
59 #define G33_GMCH_SIZE_1M	(1 << 8)
60 #define G33_GMCH_SIZE_2M	(2 << 8)
61 #define G4x_GMCH_SIZE_MASK	(0xf << 8)
62 #define G4x_GMCH_SIZE_1M	(0x1 << 8)
63 #define G4x_GMCH_SIZE_2M	(0x3 << 8)
64 #define G4x_GMCH_SIZE_VT_1M	(0x9 << 8)
65 #define G4x_GMCH_SIZE_VT_1_5M	(0xa << 8)
66 #define G4x_GMCH_SIZE_VT_2M	(0xc << 8)
67 /*
68  * The Bridge device's PCI config space has information about the
69  * fb aperture size and the amount of pre-reserved memory.
70  * This is all handled in the intel-gtt.ko module. i915.ko only
71  * cares about the vga bit for the vga rbiter.
72  */
73 #define INTEL_GMCH_CTRL		0x52
74 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
75 #define SNB_GMCH_CTRL		0x50
76 #define    SNB_GMCH_GGMS_SHIFT	8 /* GTT Graphics Memory Size */
77 #define    SNB_GMCH_GGMS_MASK	0x3
78 #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
79 #define    SNB_GMCH_GMS_MASK    0x1f
80 #define INTEL_GMCH_ENABLED	0x4
81 #define INTEL_GMCH_MEM_MASK	0x1
82 #define INTEL_GMCH_MEM_64M	0x1
83 #define INTEL_GMCH_MEM_128M	0
84 
85 #define I830_GMCH_GMS_MASK		0x70
86 #define I830_GMCH_GMS_DISABLED		0x00
87 #define I830_GMCH_GMS_LOCAL		0x10
88 #define I830_GMCH_GMS_STOLEN_512	0x20
89 #define	I830_GMCH_GMS_STOLEN_1024	0x30
90 #define I830_GMCH_GMS_STOLEN_8192	0x40
91 #define I830_RDRAM_CHANNEL_TYPE		0x03010
92 #define I830_RDRAM_ND(x)		(((x) & 0x20) >> 5)
93 #define I830_RDRAM_DDT(x)		(((x) & 0x18) >> 3)
94 
95 #define INTEL_GMCH_GMS_MASK		(0xf << 4)
96 #define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
97 #define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
98 #define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
99 #define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
100 #define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
101 #define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
102 
103 #define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
104 #define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)
105 #define INTEL_GMCH_GMS_STOLEN_128M	(0x8 << 4)
106 #define INTEL_GMCH_GMS_STOLEN_256M	(0x9 << 4)
107 #define INTEL_GMCH_GMS_STOLEN_96M	(0xa << 4)
108 #define INTEL_GMCH_GMS_STOLEN_160M	(0xb << 4)
109 #define INTEL_GMCH_GMS_STOLEN_224M	(0xc << 4)
110 #define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4)
111 
112 #define SNB_GMCH_CTRL	0x50
113 #define SNB_GMCH_GMS_STOLEN_MASK	0xF8
114 #define SNB_GMCH_GMS_STOLEN_32M		(1 << 3)
115 #define SNB_GMCH_GMS_STOLEN_64M		(2 << 3)
116 #define SNB_GMCH_GMS_STOLEN_96M		(3 << 3)
117 #define SNB_GMCH_GMS_STOLEN_128M	(4 << 3)
118 #define SNB_GMCH_GMS_STOLEN_160M	(5 << 3)
119 #define SNB_GMCH_GMS_STOLEN_192M	(6 << 3)
120 #define SNB_GMCH_GMS_STOLEN_224M	(7 << 3)
121 #define SNB_GMCH_GMS_STOLEN_256M	(8 << 3)
122 #define SNB_GMCH_GMS_STOLEN_288M	(9 << 3)
123 #define SNB_GMCH_GMS_STOLEN_320M	(0xa << 3)
124 #define SNB_GMCH_GMS_STOLEN_352M	(0xb << 3)
125 #define SNB_GMCH_GMS_STOLEN_384M	(0xc << 3)
126 #define SNB_GMCH_GMS_STOLEN_416M	(0xd << 3)
127 #define SNB_GMCH_GMS_STOLEN_448M	(0xe << 3)
128 #define SNB_GMCH_GMS_STOLEN_480M	(0xf << 3)
129 #define SNB_GMCH_GMS_STOLEN_512M	(0x10 << 3)
130 #define SNB_GTT_SIZE_0M			(0 << 8)
131 #define SNB_GTT_SIZE_1M			(1 << 8)
132 #define SNB_GTT_SIZE_2M			(2 << 8)
133 #define SNB_GTT_SIZE_MASK		(3 << 8)
134 
135 /* PCI config space */
136 
137 #define HPLLCC	0xc0 /* 855 only */
138 #define   GC_CLOCK_CONTROL_MASK		(0xf << 0)
139 #define   GC_CLOCK_133_200		(0 << 0)
140 #define   GC_CLOCK_100_200		(1 << 0)
141 #define   GC_CLOCK_100_133		(2 << 0)
142 #define   GC_CLOCK_166_250		(3 << 0)
143 #define GCFGC2	0xda
144 #define GCFGC	0xf0 /* 915+ only */
145 #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
146 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
147 #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
148 #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
149 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
150 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
151 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
152 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
153 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
154 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
155 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
156 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
157 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
158 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
159 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
160 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
161 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
162 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
163 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
164 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
165 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
166 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
167 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
168 #define LBB	0xf4
169 
170 /* Graphics reset regs */
171 #define I965_GDRST 0xc0 /* PCI config register */
172 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
173 #define  GRDOM_FULL	(0<<2)
174 #define  GRDOM_RENDER	(1<<2)
175 #define  GRDOM_MEDIA	(3<<2)
176 #define  GRDOM_MASK	(3<<2)
177 #define  GRDOM_RESET_ENABLE (1<<0)
178 
179 #define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
180 #define   GEN6_MBC_SNPCR_SHIFT	21
181 #define   GEN6_MBC_SNPCR_MASK	(3<<21)
182 #define   GEN6_MBC_SNPCR_MAX	(0<<21)
183 #define   GEN6_MBC_SNPCR_MED	(1<<21)
184 #define   GEN6_MBC_SNPCR_LOW	(2<<21)
185 #define   GEN6_MBC_SNPCR_MIN	(3<<21) /* only 1/16th of the cache is shared */
186 
187 #define GEN6_MBCTL		0x0907c
188 #define   GEN6_MBCTL_ENABLE_BOOT_FETCH	(1 << 4)
189 #define   GEN6_MBCTL_CTX_FETCH_NEEDED	(1 << 3)
190 #define   GEN6_MBCTL_BME_UPDATE_ENABLE	(1 << 2)
191 #define   GEN6_MBCTL_MAE_UPDATE_ENABLE	(1 << 1)
192 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
193 
194 #define GEN6_GDRST	0x941c
195 #define  GEN6_GRDOM_FULL		(1 << 0)
196 #define  GEN6_GRDOM_RENDER		(1 << 1)
197 #define  GEN6_GRDOM_MEDIA		(1 << 2)
198 #define  GEN6_GRDOM_BLT			(1 << 3)
199 
200 #define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
201 #define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
202 #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
203 #define   PP_DIR_DCLV_2G		0xffffffff
204 
205 #define GAM_ECOCHK			0x4090
206 #define   ECOCHK_SNB_BIT		(1<<10)
207 #define   HSW_ECOCHK_ARB_PRIO_SOL	(1<<6)
208 #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
209 #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
210 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1<<4)
211 #define   ECOCHK_PPGTT_LLC_IVB		(0x1<<3)
212 #define   ECOCHK_PPGTT_UC_HSW		(0x1<<3)
213 #define   ECOCHK_PPGTT_WT_HSW		(0x2<<3)
214 #define   ECOCHK_PPGTT_WB_HSW		(0x3<<3)
215 
216 #define GAC_ECO_BITS			0x14090
217 #define   ECOBITS_SNB_BIT		(1<<13)
218 #define   ECOBITS_PPGTT_CACHE64B	(3<<8)
219 #define   ECOBITS_PPGTT_CACHE4B		(0<<8)
220 
221 #define GAB_CTL				0x24000
222 #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
223 
224 /* VGA stuff */
225 
226 #define VGA_ST01_MDA 0x3ba
227 #define VGA_ST01_CGA 0x3da
228 
229 #define VGA_MSR_WRITE 0x3c2
230 #define VGA_MSR_READ 0x3cc
231 #define   VGA_MSR_MEM_EN (1<<1)
232 #define   VGA_MSR_CGA_MODE (1<<0)
233 
234 #define VGA_SR_INDEX 0x3c4
235 #define SR01			1
236 #define VGA_SR_DATA 0x3c5
237 
238 #define VGA_AR_INDEX 0x3c0
239 #define   VGA_AR_VID_EN (1<<5)
240 #define VGA_AR_DATA_WRITE 0x3c0
241 #define VGA_AR_DATA_READ 0x3c1
242 
243 #define VGA_GR_INDEX 0x3ce
244 #define VGA_GR_DATA 0x3cf
245 /* GR05 */
246 #define   VGA_GR_MEM_READ_MODE_SHIFT 3
247 #define     VGA_GR_MEM_READ_MODE_PLANE 1
248 /* GR06 */
249 #define   VGA_GR_MEM_MODE_MASK 0xc
250 #define   VGA_GR_MEM_MODE_SHIFT 2
251 #define   VGA_GR_MEM_A0000_AFFFF 0
252 #define   VGA_GR_MEM_A0000_BFFFF 1
253 #define   VGA_GR_MEM_B0000_B7FFF 2
254 #define   VGA_GR_MEM_B0000_BFFFF 3
255 
256 #define VGA_DACMASK 0x3c6
257 #define VGA_DACRX 0x3c7
258 #define VGA_DACWX 0x3c8
259 #define VGA_DACDATA 0x3c9
260 
261 #define VGA_CR_INDEX_MDA 0x3b4
262 #define VGA_CR_DATA_MDA 0x3b5
263 #define VGA_CR_INDEX_CGA 0x3d4
264 #define VGA_CR_DATA_CGA 0x3d5
265 
266 /*
267  * Memory interface instructions used by the kernel
268  */
269 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
270 
271 #define MI_NOOP			MI_INSTR(0, 0)
272 #define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
273 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
274 #define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
275 #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
276 #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
277 #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
278 #define MI_FLUSH		MI_INSTR(0x04, 0)
279 #define   MI_READ_FLUSH		(1 << 0)
280 #define   MI_EXE_FLUSH		(1 << 1)
281 #define   MI_NO_WRITE_FLUSH	(1 << 2)
282 #define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
283 #define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
284 #define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
285 #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
286 #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
287 #define   MI_SUSPEND_FLUSH_EN	(1<<0)
288 #define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
289 #define MI_OVERLAY_FLIP		MI_INSTR(0x11,0)
290 #define   MI_OVERLAY_CONTINUE	(0x0<<21)
291 #define   MI_OVERLAY_ON		(0x1<<21)
292 #define   MI_OVERLAY_OFF	(0x2<<21)
293 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
294 #define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
295 #define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
296 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
297 /* IVB has funny definitions for which plane to flip. */
298 #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
299 #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
300 #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
301 #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
302 #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
303 #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
304 #define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
305 #define   MI_ARB_ENABLE			(1<<0)
306 #define   MI_ARB_DISABLE		(0<<0)
307 
308 #define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
309 #define   MI_MM_SPACE_GTT		(1<<8)
310 #define   MI_MM_SPACE_PHYSICAL		(0<<8)
311 #define   MI_SAVE_EXT_STATE_EN		(1<<3)
312 #define   MI_RESTORE_EXT_STATE_EN	(1<<2)
313 #define   MI_FORCE_RESTORE		(1<<1)
314 #define   MI_RESTORE_INHIBIT		(1<<0)
315 #define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
316 #define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
317 #define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
318 #define   MI_STORE_DWORD_INDEX_SHIFT 2
319 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
320  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
321  *   simply ignores the register load under certain conditions.
322  * - One can actually load arbitrary many arbitrary registers: Simply issue x
323  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
324  */
325 #define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*x-1)
326 #define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
327 #define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
328 #define   MI_INVALIDATE_TLB		(1<<18)
329 #define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
330 #define   MI_INVALIDATE_BSD		(1<<7)
331 #define   MI_FLUSH_DW_USE_GTT		(1<<2)
332 #define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
333 #define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
334 #define   MI_BATCH_NON_SECURE		(1)
335 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
336 #define   MI_BATCH_NON_SECURE_I965 	(1<<8)
337 #define   MI_BATCH_PPGTT_HSW		(1<<8)
338 #define   MI_BATCH_NON_SECURE_HSW 	(1<<13)
339 #define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
340 #define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
341 #define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6+ */
342 #define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
343 #define  MI_SEMAPHORE_UPDATE	    (1<<21)
344 #define  MI_SEMAPHORE_COMPARE	    (1<<20)
345 #define  MI_SEMAPHORE_REGISTER	    (1<<18)
346 #define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
347 #define  MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
348 #define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
349 #define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
350 #define  MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
351 #define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
352 #define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
353 #define  MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
354 #define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
355 #define  MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
356 #define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
357 #define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
358 #define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)
359 /*
360  * 3D instructions used by the kernel
361  */
362 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
363 
364 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
365 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
366 #define   SC_UPDATE_SCISSOR       (0x1<<1)
367 #define   SC_ENABLE_MASK          (0x1<<0)
368 #define   SC_ENABLE               (0x1<<0)
369 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
370 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
371 #define   SCI_YMIN_MASK      (0xffff<<16)
372 #define   SCI_XMIN_MASK      (0xffff<<0)
373 #define   SCI_YMAX_MASK      (0xffff<<16)
374 #define   SCI_XMAX_MASK      (0xffff<<0)
375 #define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
376 #define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
377 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
378 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
379 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
380 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
381 #define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
382 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
383 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
384 #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
385 #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
386 #define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
387 #define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
388 #define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
389 #define   BLT_DEPTH_8			(0<<24)
390 #define   BLT_DEPTH_16_565		(1<<24)
391 #define   BLT_DEPTH_16_1555		(2<<24)
392 #define   BLT_DEPTH_32			(3<<24)
393 #define   BLT_ROP_GXCOPY		(0xcc<<16)
394 #define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
395 #define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
396 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
397 #define   ASYNC_FLIP                (1<<22)
398 #define   DISPLAY_PLANE_A           (0<<20)
399 #define   DISPLAY_PLANE_B           (1<<20)
400 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
401 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
402 #define   PIPE_CONTROL_CS_STALL				(1<<20)
403 #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
404 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
405 #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
406 #define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
407 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
408 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
409 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
410 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
411 #define   PIPE_CONTROL_NOTIFY				(1<<8)
412 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
413 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
414 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
415 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
416 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
417 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
418 
419 
420 /*
421  * Reset registers
422  */
423 #define DEBUG_RESET_I830		0x6070
424 #define  DEBUG_RESET_FULL		(1<<7)
425 #define  DEBUG_RESET_RENDER		(1<<8)
426 #define  DEBUG_RESET_DISPLAY		(1<<9)
427 
428 /*
429  * IOSF sideband
430  */
431 #define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
432 #define   IOSF_DEVFN_SHIFT			24
433 #define   IOSF_OPCODE_SHIFT			16
434 #define   IOSF_PORT_SHIFT			8
435 #define   IOSF_BYTE_ENABLES_SHIFT		4
436 #define   IOSF_BAR_SHIFT			1
437 #define   IOSF_SB_BUSY				(1<<0)
438 #define   IOSF_PORT_PUNIT			0x4
439 #define   IOSF_PORT_NC				0x11
440 #define   IOSF_PORT_DPIO			0x12
441 #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
442 #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
443 
444 #define PUNIT_OPCODE_REG_READ			6
445 #define PUNIT_OPCODE_REG_WRITE			7
446 
447 #define PUNIT_REG_GPU_LFM			0xd3
448 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
449 #define PUNIT_REG_GPU_FREQ_STS			0xd8
450 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
451 
452 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
453 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
454 
455 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
456 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
457 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
458 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
459 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
460 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
461 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
462 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
463 #define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
464 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
465 
466 /*
467  * DPIO - a special bus for various display related registers to hide behind
468  *
469  * DPIO is VLV only.
470  *
471  * Note: digital port B is DDI0, digital pot C is DDI1
472  */
473 #define DPIO_DEVFN			0
474 #define DPIO_OPCODE_REG_WRITE		1
475 #define DPIO_OPCODE_REG_READ		0
476 
477 #define DPIO_CTL			(VLV_DISPLAY_BASE + 0x2110)
478 #define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
479 #define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
480 #define  DPIO_SFR_BYPASS		(1<<1)
481 #define  DPIO_RESET			(1<<0)
482 
483 #define _DPIO_TX3_SWING_CTL4_A		0x690
484 #define _DPIO_TX3_SWING_CTL4_B		0x2a90
485 #define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
486 					_DPIO_TX3_SWING_CTL4_B)
487 
488 /*
489  * Per pipe/PLL DPIO regs
490  */
491 #define _DPIO_DIV_A			0x800c
492 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
493 #define   DPIO_POST_DIV_DAC		0
494 #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
495 #define   DPIO_POST_DIV_LVDS1		2
496 #define   DPIO_POST_DIV_LVDS2		3
497 #define   DPIO_K_SHIFT			(24) /* 4 bits */
498 #define   DPIO_P1_SHIFT			(21) /* 3 bits */
499 #define   DPIO_P2_SHIFT			(16) /* 5 bits */
500 #define   DPIO_N_SHIFT			(12) /* 4 bits */
501 #define   DPIO_ENABLE_CALIBRATION	(1<<11)
502 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
503 #define   DPIO_M2DIV_MASK		0xff
504 #define _DPIO_DIV_B			0x802c
505 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
506 
507 #define _DPIO_REFSFR_A			0x8014
508 #define   DPIO_REFSEL_OVERRIDE		27
509 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
510 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
511 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
512 #define   DPIO_PLL_REFCLK_SEL_MASK	3
513 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
514 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
515 #define _DPIO_REFSFR_B			0x8034
516 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
517 
518 #define _DPIO_CORE_CLK_A		0x801c
519 #define _DPIO_CORE_CLK_B		0x803c
520 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
521 
522 #define _DPIO_IREF_CTL_A		0x8040
523 #define _DPIO_IREF_CTL_B		0x8060
524 #define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
525 
526 #define DPIO_IREF_BCAST			0xc044
527 #define _DPIO_IREF_A			0x8044
528 #define _DPIO_IREF_B			0x8064
529 #define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
530 
531 #define _DPIO_PLL_CML_A			0x804c
532 #define _DPIO_PLL_CML_B			0x806c
533 #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
534 
535 #define _DPIO_LPF_COEFF_A		0x8048
536 #define _DPIO_LPF_COEFF_B		0x8068
537 #define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B)
538 
539 #define DPIO_CALIBRATION		0x80ac
540 
541 #define DPIO_FASTCLK_DISABLE		0x8100
542 
543 /*
544  * Per DDI channel DPIO regs
545  */
546 
547 #define _DPIO_PCS_TX_0			0x8200
548 #define _DPIO_PCS_TX_1			0x8400
549 #define   DPIO_PCS_TX_LANE2_RESET	(1<<16)
550 #define   DPIO_PCS_TX_LANE1_RESET	(1<<7)
551 #define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
552 
553 #define _DPIO_PCS_CLK_0			0x8204
554 #define _DPIO_PCS_CLK_1			0x8404
555 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1<<22)
556 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
557 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
558 #define   DPIO_PCS_CLK_SOFT_RESET	(1<<5)
559 #define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
560 
561 #define _DPIO_PCS_CTL_OVR1_A		0x8224
562 #define _DPIO_PCS_CTL_OVR1_B		0x8424
563 #define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
564 				       _DPIO_PCS_CTL_OVR1_B)
565 
566 #define _DPIO_PCS_STAGGER0_A		0x822c
567 #define _DPIO_PCS_STAGGER0_B		0x842c
568 #define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
569 				      _DPIO_PCS_STAGGER0_B)
570 
571 #define _DPIO_PCS_STAGGER1_A		0x8230
572 #define _DPIO_PCS_STAGGER1_B		0x8430
573 #define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
574 				      _DPIO_PCS_STAGGER1_B)
575 
576 #define _DPIO_PCS_CLOCKBUF0_A		0x8238
577 #define _DPIO_PCS_CLOCKBUF0_B		0x8438
578 #define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
579 				       _DPIO_PCS_CLOCKBUF0_B)
580 
581 #define _DPIO_PCS_CLOCKBUF8_A		0x825c
582 #define _DPIO_PCS_CLOCKBUF8_B		0x845c
583 #define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
584 				       _DPIO_PCS_CLOCKBUF8_B)
585 
586 #define _DPIO_TX_SWING_CTL2_A		0x8288
587 #define _DPIO_TX_SWING_CTL2_B		0x8488
588 #define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
589 				       _DPIO_TX_SWING_CTL2_B)
590 
591 #define _DPIO_TX_SWING_CTL3_A		0x828c
592 #define _DPIO_TX_SWING_CTL3_B		0x848c
593 #define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
594 				       _DPIO_TX_SWING_CTL3_B)
595 
596 #define _DPIO_TX_SWING_CTL4_A		0x8290
597 #define _DPIO_TX_SWING_CTL4_B		0x8490
598 #define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
599 				       _DPIO_TX_SWING_CTL4_B)
600 
601 #define _DPIO_TX_OCALINIT_0		0x8294
602 #define _DPIO_TX_OCALINIT_1		0x8494
603 #define   DPIO_TX_OCALINIT_EN		(1UL<<31)
604 #define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
605 				     _DPIO_TX_OCALINIT_1)
606 
607 #define _DPIO_TX_CTL_0			0x82ac
608 #define _DPIO_TX_CTL_1			0x84ac
609 #define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
610 
611 #define _DPIO_TX_LANE_0			0x82b8
612 #define _DPIO_TX_LANE_1			0x84b8
613 #define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
614 
615 #define _DPIO_DATA_CHANNEL1		0x8220
616 #define _DPIO_DATA_CHANNEL2		0x8420
617 #define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
618 
619 #define _DPIO_PORT0_PCS0		0x0220
620 #define _DPIO_PORT0_PCS1		0x0420
621 #define _DPIO_PORT1_PCS2		0x2620
622 #define _DPIO_PORT1_PCS3		0x2820
623 #define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
624 #define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
625 #define DPIO_DATA_CHANNEL1		0x8220
626 #define DPIO_DATA_CHANNEL2		0x8420
627 
628 /*
629  * Fence registers
630  */
631 #define FENCE_REG_830_0			0x2000
632 #define FENCE_REG_945_8			0x3000
633 #define   I830_FENCE_START_MASK		0x07f80000
634 #define   I830_FENCE_TILING_Y_SHIFT	12
635 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
636 #define   I830_FENCE_PITCH_SHIFT	4
637 #define   I830_FENCE_REG_VALID		(1<<0)
638 #define   I915_FENCE_MAX_PITCH_VAL	4
639 #define   I830_FENCE_MAX_PITCH_VAL	6
640 #define   I830_FENCE_MAX_SIZE_VAL	(1<<8)
641 
642 #define   I915_FENCE_START_MASK		0x0ff00000
643 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
644 
645 #define FENCE_REG_965_0			0x03000
646 #define   I965_FENCE_PITCH_SHIFT	2
647 #define   I965_FENCE_TILING_Y_SHIFT	1
648 #define   I965_FENCE_REG_VALID		(1<<0)
649 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
650 
651 #define FENCE_REG_SANDYBRIDGE_0		0x100000
652 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
653 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
654 
655 /* control register for cpu gtt access */
656 #define TILECTL				0x101000
657 #define   TILECTL_SWZCTL			(1 << 0)
658 #define   TILECTL_TLB_PREFETCH_DIS	(1 << 2)
659 #define   TILECTL_BACKSNOOP_DIS		(1 << 3)
660 
661 /*
662  * Instruction and interrupt control regs
663  */
664 #define I810_PGETBL_CTL		0x2020
665 #define I810_PGETBL_ENABLED	0x00000001
666 #define I965_PGETBL_CTL2	0x20c4
667 #define I965_PGETBL_SIZE_MASK	0x0000000e
668 #define PGTBL_ER	0x02024
669 #define RENDER_RING_BASE	0x02000
670 #define BSD_RING_BASE		0x04000
671 #define GEN6_BSD_RING_BASE	0x12000
672 #define VEBOX_RING_BASE		0x1a000
673 #define BLT_RING_BASE		0x22000
674 #define RING_TAIL(base)		((base)+0x30)
675 #define RING_HEAD(base)		((base)+0x34)
676 #define RING_START(base)	((base)+0x38)
677 #define RING_CTL(base)		((base)+0x3c)
678 #define RING_SYNC_0(base)	((base)+0x40)
679 #define RING_SYNC_1(base)	((base)+0x44)
680 #define RING_SYNC_2(base)	((base)+0x48)
681 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
682 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
683 #define GEN6_RVESYNC	(RING_SYNC_2(RENDER_RING_BASE))
684 #define GEN6_VBSYNC	(RING_SYNC_0(GEN6_BSD_RING_BASE))
685 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
686 #define GEN6_VVESYNC	(RING_SYNC_2(GEN6_BSD_RING_BASE))
687 #define GEN6_BRSYNC	(RING_SYNC_0(BLT_RING_BASE))
688 #define GEN6_BVSYNC	(RING_SYNC_1(BLT_RING_BASE))
689 #define GEN6_BVESYNC	(RING_SYNC_2(BLT_RING_BASE))
690 #define GEN6_VEBSYNC	(RING_SYNC_0(VEBOX_RING_BASE))
691 #define GEN6_VERSYNC	(RING_SYNC_1(VEBOX_RING_BASE))
692 #define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))
693 #define GEN6_NOSYNC 0
694 #define RING_MAX_IDLE(base)	((base)+0x54)
695 #define RING_HWS_PGA(base)	((base)+0x80)
696 #define RING_HWS_PGA_GEN6(base)	((base)+0x2080)
697 #define ARB_MODE		0x04030
698 #define   ARB_MODE_SWIZZLE_SNB	(1<<4)
699 #define   ARB_MODE_SWIZZLE_IVB	(1<<5)
700 #define RENDER_HWS_PGA_GEN7	(0x04080)
701 #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
702 #define DONE_REG		0x40b0
703 #define	BSD_HWS_PGA_GEN7	(0x04180)
704 #define	BLT_HWS_PGA_GEN7	(0x04280)
705 #define VEBOX_HWS_PGA_GEN7	(0x04380)
706 #define RING_ACTHD(base)	((base)+0x74)
707 #define RING_NOPID(base)	((base)+0x94)
708 #define RING_IMR(base)		((base)+0xa8)
709 #define RING_TIMESTAMP(base)	((base)+0x358)
710 #define   TAIL_ADDR		0x001FFFF8
711 #define   HEAD_WRAP_COUNT	0xFFE00000
712 #define   HEAD_WRAP_ONE		0x00200000
713 #define   HEAD_ADDR		0x001FFFFC
714 #define   RING_NR_PAGES		0x001FF000
715 #define   RING_REPORT_MASK	0x00000006
716 #define   RING_REPORT_64K	0x00000002
717 #define   RING_REPORT_128K	0x00000004
718 #define   RING_NO_REPORT	0x00000000
719 #define   RING_VALID_MASK	0x00000001
720 #define   RING_VALID		0x00000001
721 #define   RING_INVALID		0x00000000
722 #define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
723 #define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
724 #define   RING_WAIT_SEMAPHORE	(1<<10) /* gen6+ */
725 #if 0
726 #define PRB0_TAIL	0x02030
727 #define PRB0_HEAD	0x02034
728 #define PRB0_START	0x02038
729 #define PRB0_CTL	0x0203c
730 #define PRB1_TAIL	0x02040 /* 915+ only */
731 #define PRB1_HEAD	0x02044 /* 915+ only */
732 #define PRB1_START	0x02048 /* 915+ only */
733 #define PRB1_CTL	0x0204c /* 915+ only */
734 #endif
735 #define IPEIR_I965	0x02064
736 #define IPEHR_I965	0x02068
737 #define INSTDONE_I965	0x0206c
738 #define GEN7_INSTDONE_1		0x0206c
739 #define GEN7_SC_INSTDONE	0x07100
740 #define GEN7_SAMPLER_INSTDONE	0x0e160
741 #define GEN7_ROW_INSTDONE	0x0e164
742 #define I915_NUM_INSTDONE_REG	4
743 #define RING_IPEIR(base)	((base)+0x64)
744 #define RING_IPEHR(base)	((base)+0x68)
745 #define RING_INSTDONE(base)	((base)+0x6c)
746 #define RING_INSTPS(base)	((base)+0x70)
747 #define RING_DMA_FADD(base)	((base)+0x78)
748 #define RING_INSTPM(base)	((base)+0xc0)
749 #define INSTPS		0x02070 /* 965+ only */
750 #define INSTDONE1	0x0207c /* 965+ only */
751 #define ACTHD_I965	0x02074
752 #define HWS_PGA		0x02080
753 #define HWS_ADDRESS_MASK	0xfffff000
754 #define HWS_START_ADDRESS_SHIFT	4
755 #define PWRCTXA		0x2088 /* 965GM+ only */
756 #define   PWRCTX_EN	(1<<0)
757 #define IPEIR		0x02088
758 #define IPEHR		0x0208c
759 #define INSTDONE	0x02090
760 #define HWSTAM		0x02098
761 #define DMA_FADD_I8XX	0x020d0
762 
763 #define ERROR_GEN6	0x040a0
764 #define GEN7_ERR_INT	0x44040
765 #define   ERR_INT_POISON		(1UL<<31)
766 #define   ERR_INT_MMIO_UNCLAIMED	(1<<13)
767 #define   ERR_INT_FIFO_UNDERRUN_C	(1<<6)
768 #define   ERR_INT_FIFO_UNDERRUN_B	(1<<3)
769 #define   ERR_INT_FIFO_UNDERRUN_A	(1<<0)
770 
771 #define FPGA_DBG		0x42300
772 #define   FPGA_DBG_RM_NOCLAIM	(1UL<<31)
773 
774 #define DERRMR		0x44050
775 
776 /* GM45+ chicken bits -- debug workaround bits that may be required
777  * for various sorts of correct behavior.  The top 16 bits of each are
778  * the enables for writing to the corresponding low bit.
779  */
780 #define _3D_CHICKEN	0x02084
781 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB	(1 << 10)
782 #define _3D_CHICKEN2	0x0208c
783 /* Disables pipelining of read flushes past the SF-WIZ interface.
784  * Required on all Ironlake steppings according to the B-Spec, but the
785  * particular danger of not doing so is not specified.
786  */
787 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
788 #define _3D_CHICKEN3	0x02090
789 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
790 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
791 
792 #define MI_MODE		0x0209c
793 #define VS_TIMER_DISPATCH	(1 << 6)
794 #define MI_FLUSH_ENABLE	(1 << 12)
795 # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
796 
797 #define GEN6_GT_MODE	0x20d0
798 #define   GEN6_GT_MODE_HI	(1 << 9)
799 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE		(1 << 5)
800 
801 #define GFX_MODE	0x02520
802 #define	GFX_MODE_GEN7	0x0229c
803 #define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
804 #define   GFX_RUN_LIST_ENABLE		(1<<15)
805 #define   GFX_TLB_INVALIDATE_ALWAYS	(1<<13)
806 #define   GFX_SURFACE_FAULT_ENABLE	(1<<12)
807 #define   GFX_REPLAY_MODE		(1<<11)
808 #define   GFX_PSMI_GRANULARITY		(1<<10)
809 #define   GFX_PPGTT_ENABLE		(1<<9)
810 
811 #define VLV_DISPLAY_BASE 0x180000
812 
813 #define SCPD0		0x0209c /* 915+ only */
814 #define IER		0x020a0
815 #define IIR		0x020a4
816 #define IMR		0x020a8
817 #define ISR		0x020ac
818 #define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
819 #define   GCFG_DIS		(1<<8)
820 #define VLV_IIR_RW	(VLV_DISPLAY_BASE + 0x2084)
821 #define VLV_IER		(VLV_DISPLAY_BASE + 0x20a0)
822 #define VLV_IIR		(VLV_DISPLAY_BASE + 0x20a4)
823 #define VLV_IMR		(VLV_DISPLAY_BASE + 0x20a8)
824 #define VLV_ISR		(VLV_DISPLAY_BASE + 0x20ac)
825 #define VLV_PCBR	(VLV_DISPLAY_BASE + 0x2120)
826 #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
827 #define EIR		0x020b0
828 #define EMR		0x020b4
829 #define ESR		0x020b8
830 #define   GM45_ERROR_PAGE_TABLE				(1<<5)
831 #define   GM45_ERROR_MEM_PRIV				(1<<4)
832 #define   I915_ERROR_PAGE_TABLE				(1<<4)
833 #define   GM45_ERROR_CP_PRIV				(1<<3)
834 #define   I915_ERROR_MEMORY_REFRESH			(1<<1)
835 #define   I915_ERROR_INSTRUCTION			(1<<0)
836 #define INSTPM	        0x020c0
837 #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
838 #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
839 					will not assert AGPBUSY# and will only
840 					be delivered when out of C3. */
841 #define	INSTPM_FORCE_ORDERING	(1<<7) /* GEN6+ */
842 #define	INSTPM_TLB_INVALIDATE	(1<<9)
843 #define	INSTPM_SYNC_FLUSH	(1<<5)
844 #define ACTHD	        0x020c8
845 #define FW_BLC		0x020d8
846 #define FW_BLC2	 	0x020dc
847 #define FW_BLC_SELF	0x020e0 /* 915+ only */
848 #define   FW_BLC_SELF_EN_MASK      (1UL<<31)
849 #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
850 #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
851 #define MM_BURST_LENGTH     0x00700000
852 #define MM_FIFO_WATERMARK   0x0001F000
853 #define LM_BURST_LENGTH     0x00000700
854 #define LM_FIFO_WATERMARK   0x0000001F
855 #define MI_ARB_STATE	0x020e4 /* 915+ only */
856 
857 /* Make render/texture TLB fetches lower priorty than associated data
858  *   fetches. This is not turned on by default
859  */
860 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
861 
862 /* Isoch request wait on GTT enable (Display A/B/C streams).
863  * Make isoch requests stall on the TLB update. May cause
864  * display underruns (test mode only)
865  */
866 #define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
867 
868 /* Block grant count for isoch requests when block count is
869  * set to a finite value.
870  */
871 #define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
872 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
873 #define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
874 #define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
875 #define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
876 
877 /* Enable render writes to complete in C2/C3/C4 power states.
878  * If this isn't enabled, render writes are prevented in low
879  * power states. That seems bad to me.
880  */
881 #define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
882 
883 /* This acknowledges an async flip immediately instead
884  * of waiting for 2TLB fetches.
885  */
886 #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
887 
888 /* Enables non-sequential data reads through arbiter
889  */
890 #define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)
891 
892 /* Disable FSB snooping of cacheable write cycles from binner/render
893  * command stream
894  */
895 #define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
896 
897 /* Arbiter time slice for non-isoch streams */
898 #define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
899 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
900 #define   MI_ARB_TIME_SLICE_2			(1 << 5)
901 #define   MI_ARB_TIME_SLICE_4			(2 << 5)
902 #define   MI_ARB_TIME_SLICE_6			(3 << 5)
903 #define   MI_ARB_TIME_SLICE_8			(4 << 5)
904 #define   MI_ARB_TIME_SLICE_10			(5 << 5)
905 #define   MI_ARB_TIME_SLICE_14			(6 << 5)
906 #define   MI_ARB_TIME_SLICE_16			(7 << 5)
907 
908 /* Low priority grace period page size */
909 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
910 #define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
911 
912 /* Disable display A/B trickle feed */
913 #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
914 
915 /* Set display plane priority */
916 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
917 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
918 
919 #define CACHE_MODE_0	0x02120 /* 915+ only */
920 #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
921 #define   CM0_IZ_OPT_DISABLE      (1<<6)
922 #define   CM0_ZR_OPT_DISABLE      (1<<5)
923 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
924 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
925 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
926 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
927 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
928 #define BB_ADDR		0x02140 /* 8 bytes */
929 #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
930 #define GFX_FLSH_CNTL_GEN6	0x101008
931 #define   GFX_FLSH_CNTL_EN	(1<<0)
932 #define ECOSKPD		0x021d0
933 #define   ECO_GATING_CX_ONLY	(1<<3)
934 #define   ECO_FLIP_DONE		(1<<0)
935 
936 #define CACHE_MODE_1		0x7004 /* IVB+ */
937 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
938 
939 #define GEN6_BLITTER_ECOSKPD	0x221d0
940 #define   GEN6_BLITTER_LOCK_SHIFT			16
941 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
942 
943 #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
944 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
945 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
946 #define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)
947 #define   GEN6_BSD_GO_INDICATOR		(1 << 4)
948 
949 /* On modern GEN architectures interrupt control consists of two sets
950  * of registers. The first set pertains to the ring generating the
951  * interrupt. The second control is for the functional block generating the
952  * interrupt. These are PM, GT, DE, etc.
953  *
954  * Luckily *knocks on wood* all the ring interrupt bits match up with the
955  * GT interrupt bits, so we don't need to duplicate the defines.
956  *
957  * These defines should cover us well from SNB->HSW with minor exceptions
958  * it can also work on ILK.
959  */
960 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
961 #define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
962 #define GT_BLT_USER_INTERRUPT			(1 << 22)
963 #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
964 #define GT_BSD_USER_INTERRUPT			(1 << 12)
965 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
966 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
967 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
968 #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
969 #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
970 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
971 
972 #define PM_VEBOX_CS_ERROR_INTERRUPT		(1 << 12) /* hsw+ */
973 #define PM_VEBOX_USER_INTERRUPT			(1 << 10) /* hsw+ */
974 
975 /* These are all the "old" interrupts */
976 #define ILK_BSD_USER_INTERRUPT				(1<<5)
977 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
978 #define I915_DISPLAY_PORT_INTERRUPT			(1<<17)
979 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
980 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14) /* p-state */
981 #define I915_HWB_OOM_INTERRUPT				(1<<13)
982 #define I915_SYNC_STATUS_INTERRUPT			(1<<12)
983 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
984 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
985 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
986 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
987 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
988 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
989 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
990 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
991 #define I915_DEBUG_INTERRUPT				(1<<2)
992 #define I915_USER_INTERRUPT				(1<<1)
993 #define I915_ASLE_INTERRUPT				(1<<0)
994 #define I915_BSD_USER_INTERRUPT				(1 << 25)
995 
996 #define GEN6_BSD_RNCID			0x12198
997 
998 #define GEN7_FF_THREAD_MODE		0x20a0
999 #define   GEN7_FF_SCHED_MASK		0x0077070
1000 #define   GEN7_FF_TS_SCHED_HS1		(0x5<<16)
1001 #define   GEN7_FF_TS_SCHED_HS0		(0x3<<16)
1002 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1<<16)
1003 #define   GEN7_FF_TS_SCHED_HW		(0x0<<16) /* Default */
1004 #define   GEN7_FF_VS_REF_CNT_FFME	(1 << 15)
1005 #define   GEN7_FF_VS_SCHED_HS1		(0x5<<12)
1006 #define   GEN7_FF_VS_SCHED_HS0		(0x3<<12)
1007 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1<<12) /* Default */
1008 #define   GEN7_FF_VS_SCHED_HW		(0x0<<12)
1009 #define   GEN7_FF_DS_SCHED_HS1		(0x5<<4)
1010 #define   GEN7_FF_DS_SCHED_HS0		(0x3<<4)
1011 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1<<4)  /* Default */
1012 #define   GEN7_FF_DS_SCHED_HW		(0x0<<4)
1013 
1014 /*
1015  * Framebuffer compression (915+ only)
1016  */
1017 
1018 #define FBC_CFB_BASE		0x03200 /* 4k page aligned */
1019 #define FBC_LL_BASE		0x03204 /* 4k page aligned */
1020 #define FBC_CONTROL		0x03208
1021 #define   FBC_CTL_EN		(1UL<<31)  /* OSOL_i915 */
1022 #define   FBC_CTL_PERIODIC	(1<<30)
1023 #define   FBC_CTL_INTERVAL_SHIFT (16)
1024 #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
1025 #define   FBC_CTL_C3_IDLE	(1<<13)
1026 #define   FBC_CTL_STRIDE_SHIFT	(5)
1027 #define   FBC_CTL_FENCENO	(1<<0)
1028 #define FBC_COMMAND		0x0320c
1029 #define   FBC_CMD_COMPRESS	(1<<0)
1030 #define FBC_STATUS		0x03210
1031 #define   FBC_STAT_COMPRESSING	(1UL<<31)  /* OSOL_i915 */
1032 #define   FBC_STAT_COMPRESSED	(1<<30)
1033 #define   FBC_STAT_MODIFIED	(1<<29)
1034 #define   FBC_STAT_CURRENT_LINE	(1<<0)
1035 #define FBC_CONTROL2		0x03214
1036 #define   FBC_CTL_FENCE_DBL	(0<<4)
1037 #define   FBC_CTL_IDLE_IMM	(0<<2)
1038 #define   FBC_CTL_IDLE_FULL	(1<<2)
1039 #define   FBC_CTL_IDLE_LINE	(2<<2)
1040 #define   FBC_CTL_IDLE_DEBUG	(3<<2)
1041 #define   FBC_CTL_CPU_FENCE	(1<<1)
1042 #define   FBC_CTL_PLANEA	(0<<0)
1043 #define   FBC_CTL_PLANEB	(1<<0)
1044 #define FBC_FENCE_OFF		0x0321b
1045 #define FBC_TAG			0x03300
1046 
1047 #define FBC_LL_SIZE		(1536)
1048 
1049 /* Framebuffer compression for GM45+ */
1050 #define DPFC_CB_BASE		0x3200
1051 #define DPFC_CONTROL		0x3208
1052 #define   DPFC_CTL_EN		(1UL<<31)  /* OSOL_i915 */
1053 #define   DPFC_CTL_PLANEA	(0<<30)
1054 #define   DPFC_CTL_PLANEB	(1<<30)
1055 #define   IVB_DPFC_CTL_PLANE_SHIFT	(29)
1056 #define   DPFC_CTL_FENCE_EN	(1<<29)
1057 #define   IVB_DPFC_CTL_FENCE_EN	(1<<28)
1058 #define   DPFC_CTL_PERSISTENT_MODE	(1<<25)
1059 #define   DPFC_SR_EN		(1<<10)
1060 #define   DPFC_CTL_LIMIT_1X	(0<<6)
1061 #define   DPFC_CTL_LIMIT_2X	(1<<6)
1062 #define   DPFC_CTL_LIMIT_4X	(2<<6)
1063 #define DPFC_RECOMP_CTL		0x320c
1064 #define   DPFC_RECOMP_STALL_EN	(1<<27)
1065 #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
1066 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1067 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1068 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1069 #define DPFC_STATUS		0x3210
1070 #define   DPFC_INVAL_SEG_SHIFT  (16)
1071 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
1072 #define   DPFC_COMP_SEG_SHIFT	(0)
1073 #define   DPFC_COMP_SEG_MASK	(0x000003ff)
1074 #define DPFC_STATUS2		0x3214
1075 #define DPFC_FENCE_YOFF		0x3218
1076 #define DPFC_CHICKEN		0x3224
1077 #define   DPFC_HT_MODIFY	(1UL<<31)  /* OSOL_i915 */
1078 
1079 /* Framebuffer compression for Ironlake */
1080 #define ILK_DPFC_CB_BASE	0x43200
1081 #define ILK_DPFC_CONTROL	0x43208
1082 /* The bit 28-8 is reserved */
1083 #define   DPFC_RESERVED		(0x1FFFFF00)
1084 #define ILK_DPFC_RECOMP_CTL	0x4320c
1085 #define ILK_DPFC_STATUS		0x43210
1086 #define ILK_DPFC_FENCE_YOFF	0x43218
1087 #define ILK_DPFC_CHICKEN	0x43224
1088 #define ILK_FBC_RT_BASE		0x2128
1089 #define   ILK_FBC_RT_VALID	(1<<0)
1090 
1091 #define ILK_DISPLAY_CHICKEN1	0x42000
1092 #define   ILK_FBCQ_DIS		(1<<22)
1093 #define   ILK_PABSTRETCH_DIS 	(1<<21)
1094 
1095 
1096 /*
1097  * Framebuffer compression for Sandybridge
1098  *
1099  * The following two registers are of type GTTMMADR
1100  */
1101 #define SNB_DPFC_CTL_SA		0x100100
1102 #define   SNB_CPU_FENCE_ENABLE	(1<<29)
1103 #define DPFC_CPU_FENCE_OFFSET	0x100104
1104 
1105 /* Framebuffer compression for Ivybridge */
1106 #define IVB_FBC_RT_BASE			0x7020
1107 
1108 #define IPS_CTL		0x43408
1109 #define   IPS_ENABLE	(1UL << 31)
1110 
1111 #define MSG_FBC_REND_STATE	0x50380
1112 #define   FBC_REND_NUKE		(1<<2)
1113 #define   FBC_REND_CACHE_CLEAN	(1<<1)
1114 
1115 #define _HSW_PIPE_SLICE_CHICKEN_1_A	0x420B0
1116 #define _HSW_PIPE_SLICE_CHICKEN_1_B	0x420B4
1117 #define   HSW_BYPASS_FBC_QUEUE		(1<<22)
1118 #define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1119 					     _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1120 					     _HSW_PIPE_SLICE_CHICKEN_1_B)
1121 
1122 #define HSW_CLKGATE_DISABLE_PART_1	0x46500
1123 #define   HSW_DPFC_GATING_DISABLE	(1<<23)
1124 
1125 /*
1126  * GPIO regs
1127  */
1128 #define GPIOA			0x5010
1129 #define GPIOB			0x5014
1130 #define GPIOC			0x5018
1131 #define GPIOD			0x501c
1132 #define GPIOE			0x5020
1133 #define GPIOF			0x5024
1134 #define GPIOG			0x5028
1135 #define GPIOH			0x502c
1136 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
1137 # define GPIO_CLOCK_DIR_IN		(0 << 1)
1138 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
1139 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
1140 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
1141 # define GPIO_CLOCK_VAL_IN		(1 << 4)
1142 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
1143 # define GPIO_DATA_DIR_MASK		(1 << 8)
1144 # define GPIO_DATA_DIR_IN		(0 << 9)
1145 # define GPIO_DATA_DIR_OUT		(1 << 9)
1146 # define GPIO_DATA_VAL_MASK		(1 << 10)
1147 # define GPIO_DATA_VAL_OUT		(1 << 11)
1148 # define GPIO_DATA_VAL_IN		(1 << 12)
1149 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
1150 
1151 #define GMBUS0			0x5100
1152 #define   GMBUS_RATE_100KHZ	(0<<8)
1153 #define   GMBUS_RATE_50KHZ	(1<<8)
1154 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
1155 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
1156 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
1157 #define   GMBUS_PORT_DISABLED	0
1158 #define   GMBUS_PORT_SSC	1
1159 #define   GMBUS_PORT_VGADDC	2
1160 #define   GMBUS_PORT_PANEL	3
1161 #define   GMBUS_PORT_DPC	4 /* HDMIC */
1162 #define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
1163 #define   GMBUS_PORT_DPD	6 /* HDMID */
1164 #define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
1165 #define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1166 #define GMBUS1			0x5104 /* command/status */
1167 #define   GMBUS_SW_CLR_INT	(1UL<<31)
1168 #define   GMBUS_SW_RDY		(1<<30)
1169 #define   GMBUS_ENT		(1<<29) /* enable timeout */
1170 #define   GMBUS_CYCLE_NONE	(0<<25)
1171 #define   GMBUS_CYCLE_WAIT	(1<<25)
1172 #define   GMBUS_CYCLE_INDEX	(2<<25)
1173 #define   GMBUS_CYCLE_STOP	(4<<25)
1174 #define   GMBUS_BYTE_COUNT_SHIFT 16
1175 #define   GMBUS_SLAVE_INDEX_SHIFT 8
1176 #define   GMBUS_SLAVE_ADDR_SHIFT 1
1177 #define   GMBUS_SLAVE_READ	(1<<0)
1178 #define   GMBUS_SLAVE_WRITE	(0<<0)
1179 #define GMBUS2			0x5108 /* status */
1180 #define   GMBUS_INUSE		(1<<15)
1181 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
1182 #define   GMBUS_STALL_TIMEOUT	(1<<13)
1183 #define   GMBUS_INT		(1<<12)
1184 #define   GMBUS_HW_RDY		(1<<11)
1185 #define   GMBUS_SATOER		(1<<10)
1186 #define   GMBUS_ACTIVE		(1<<9)
1187 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
1188 #define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
1189 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1190 #define   GMBUS_NAK_EN		(1<<3)
1191 #define   GMBUS_IDLE_EN		(1<<2)
1192 #define   GMBUS_HW_WAIT_EN	(1<<1)
1193 #define   GMBUS_HW_RDY_EN	(1<<0)
1194 #define GMBUS5			0x5120 /* byte index */
1195 #define   GMBUS_2BYTE_INDEX_EN	(1UL<<31)
1196 
1197 /*
1198  * Clock control & power management
1199  */
1200 
1201 #define VGA0	0x6000
1202 #define VGA1	0x6004
1203 #define VGA_PD	0x6010
1204 #define   VGA0_PD_P2_DIV_4	(1 << 7)
1205 #define   VGA0_PD_P1_DIV_2	(1 << 5)
1206 #define   VGA0_PD_P1_SHIFT	0
1207 #define   VGA0_PD_P1_MASK	(0x1f << 0)
1208 #define   VGA1_PD_P2_DIV_4	(1 << 15)
1209 #define   VGA1_PD_P1_DIV_2	(1 << 13)
1210 #define   VGA1_PD_P1_SHIFT	8
1211 #define   VGA1_PD_P1_MASK	(0x1f << 8)
1212 #define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
1213 #define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
1214 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
1215 #define   DPLL_VCO_ENABLE		(1UL << 31)  /* OSOL_i915 */
1216 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
1217 #define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
1218 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
1219 #define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
1220 #define   DPLL_VGA_MODE_DIS		(1 << 28)
1221 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
1222 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
1223 #define   DPLL_MODE_MASK		(3 << 26)
1224 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1225 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1226 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
1227 #define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
1228 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
1229 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
1230 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
1231 #define   DPLL_LOCK_VLV			(1<<15)
1232 #define   DPLL_INTEGRATED_CRI_CLK_VLV	(1<<14)
1233 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
1234 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
1235 #define   DPLL_PORTB_READY_MASK		(0xf)
1236 
1237 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
1238 /*
1239  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1240  * this field (only one bit may be set).
1241  */
1242 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
1243 #define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
1244 #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1245 /* i830, required in DVO non-gang */
1246 #define   PLL_P2_DIVIDE_BY_4		(1 << 23)
1247 #define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
1248 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
1249 #define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
1250 #define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
1251 #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1252 #define   PLL_REF_INPUT_MASK		(3 << 13)
1253 #define   PLL_LOAD_PULSE_PHASE_SHIFT		9
1254 /* Ironlake */
1255 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
1256 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
1257 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)	(((x)-1) << 9)
1258 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
1259 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
1260 
1261 /*
1262  * Parallel to Serial Load Pulse phase selection.
1263  * Selects the phase for the 10X DPLL clock for the PCIe
1264  * digital display port. The range is 4 to 13; 10 or more
1265  * is just a flip delay. The default is 6
1266  */
1267 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1268 #define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
1269 /*
1270  * SDVO multiplier for 945G/GM. Not used on 965.
1271  */
1272 #define   SDVO_MULTIPLIER_MASK			0x000000ff
1273 #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
1274 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
1275 #define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
1276 /*
1277  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1278  *
1279  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
1280  */
1281 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1282 #define   DPLL_MD_UDI_DIVIDER_SHIFT		24
1283 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1284 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1285 #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
1286 /*
1287  * SDVO/UDI pixel multiplier.
1288  *
1289  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1290  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
1291  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1292  * dummy bytes in the datastream at an increased clock rate, with both sides of
1293  * the link knowing how many bytes are fill.
1294  *
1295  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1296  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
1297  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1298  * through an SDVO command.
1299  *
1300  * This register field has values of multiplication factor minus 1, with
1301  * a maximum multiplier of 5 for SDVO.
1302  */
1303 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1304 #define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
1305 /*
1306  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1307  * This best be set to the default value (3) or the CRT won't work. No,
1308  * I don't entirely understand what this does...
1309  */
1310 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1311 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
1312 #define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
1313 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1314 
1315 #define _FPA0	0x06040
1316 #define _FPA1	0x06044
1317 #define _FPB0	0x06048
1318 #define _FPB1	0x0604c
1319 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1320 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1321 #define   FP_N_DIV_MASK		0x003f0000
1322 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1323 #define   FP_N_DIV_SHIFT		16
1324 #define   FP_M1_DIV_MASK	0x00003f00
1325 #define   FP_M1_DIV_SHIFT		 8
1326 #define   FP_M2_DIV_MASK	0x0000003f
1327 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1328 #define   FP_M2_DIV_SHIFT		 0
1329 #define DPLL_TEST	0x606c
1330 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1331 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
1332 #define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
1333 #define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
1334 #define   DPLLB_TEST_N_BYPASS		(1 << 19)
1335 #define   DPLLB_TEST_M_BYPASS		(1 << 18)
1336 #define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
1337 #define   DPLLA_TEST_N_BYPASS		(1 << 3)
1338 #define   DPLLA_TEST_M_BYPASS		(1 << 2)
1339 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1340 #define D_STATE		0x6104
1341 #define  DSTATE_GFX_RESET_I830			(1<<6)
1342 #define  DSTATE_PLL_D3_OFF			(1<<3)
1343 #define  DSTATE_GFX_CLOCK_GATING		(1<<1)
1344 #define  DSTATE_DOT_CLOCK_GATING		(1<<0)
1345 #define DSPCLK_GATE_D	(dev_priv->info->display_mmio_offset + 0x6200)
1346 # define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
1347 # define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
1348 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
1349 # define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
1350 # define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
1351 # define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
1352 # define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
1353 # define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
1354 # define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
1355 # define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
1356 # define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
1357 # define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
1358 # define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
1359 # define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
1360 # define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
1361 # define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
1362 # define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
1363 # define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
1364 # define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
1365 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1366 # define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
1367 # define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
1368 # define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
1369 # define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
1370 # define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
1371 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
1372 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
1373 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
1374 /**
1375  * This bit must be set on the 830 to prevent hangs when turning off the
1376  * overlay scaler.
1377  */
1378 # define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
1379 # define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
1380 # define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
1381 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1382 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1383 
1384 #define RENCLK_GATE_D1		0x6204
1385 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
1386 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
1387 # define PC_FE_CLOCK_GATE_DISABLE		(1 << 11)
1388 # define PC_BE_CLOCK_GATE_DISABLE		(1 << 10)
1389 # define WINDOWER_CLOCK_GATE_DISABLE		(1 << 9)
1390 # define INTERPOLATOR_CLOCK_GATE_DISABLE	(1 << 8)
1391 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE	(1 << 7)
1392 # define MOTION_COMP_CLOCK_GATE_DISABLE		(1 << 6)
1393 # define MAG_CLOCK_GATE_DISABLE			(1 << 5)
1394 /** This bit must be unset on 855,865 */
1395 # define MECI_CLOCK_GATE_DISABLE		(1 << 4)
1396 # define DCMP_CLOCK_GATE_DISABLE		(1 << 3)
1397 # define MEC_CLOCK_GATE_DISABLE			(1 << 2)
1398 # define MECO_CLOCK_GATE_DISABLE		(1 << 1)
1399 /** This bit must be set on 855,865. */
1400 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
1401 # define I915_MPEG_CLOCK_GATE_DISABLE		(1 << 16)
1402 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE	(1 << 15)
1403 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE	(1 << 14)
1404 # define I915_BD_BF_CLOCK_GATE_DISABLE		(1 << 13)
1405 # define I915_SF_SE_CLOCK_GATE_DISABLE		(1 << 12)
1406 # define I915_WM_CLOCK_GATE_DISABLE		(1 << 11)
1407 # define I915_IZ_CLOCK_GATE_DISABLE		(1 << 10)
1408 # define I915_PI_CLOCK_GATE_DISABLE		(1 << 9)
1409 # define I915_DI_CLOCK_GATE_DISABLE		(1 << 8)
1410 # define I915_SH_SV_CLOCK_GATE_DISABLE		(1 << 7)
1411 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE	(1 << 6)
1412 # define I915_SC_CLOCK_GATE_DISABLE		(1 << 5)
1413 # define I915_FL_CLOCK_GATE_DISABLE		(1 << 4)
1414 # define I915_DM_CLOCK_GATE_DISABLE		(1 << 3)
1415 # define I915_PS_CLOCK_GATE_DISABLE		(1 << 2)
1416 # define I915_CC_CLOCK_GATE_DISABLE		(1 << 1)
1417 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1418 
1419 # define I965_RCZ_CLOCK_GATE_DISABLE		(1 << 30)
1420 /** This bit must always be set on 965G/965GM */
1421 # define I965_RCC_CLOCK_GATE_DISABLE		(1 << 29)
1422 # define I965_RCPB_CLOCK_GATE_DISABLE		(1 << 28)
1423 # define I965_DAP_CLOCK_GATE_DISABLE		(1 << 27)
1424 # define I965_ROC_CLOCK_GATE_DISABLE		(1 << 26)
1425 # define I965_GW_CLOCK_GATE_DISABLE		(1 << 25)
1426 # define I965_TD_CLOCK_GATE_DISABLE		(1 << 24)
1427 /** This bit must always be set on 965G */
1428 # define I965_ISC_CLOCK_GATE_DISABLE		(1 << 23)
1429 # define I965_IC_CLOCK_GATE_DISABLE		(1 << 22)
1430 # define I965_EU_CLOCK_GATE_DISABLE		(1 << 21)
1431 # define I965_IF_CLOCK_GATE_DISABLE		(1 << 20)
1432 # define I965_TC_CLOCK_GATE_DISABLE		(1 << 19)
1433 # define I965_SO_CLOCK_GATE_DISABLE		(1 << 17)
1434 # define I965_FBC_CLOCK_GATE_DISABLE		(1 << 16)
1435 # define I965_MARI_CLOCK_GATE_DISABLE		(1 << 15)
1436 # define I965_MASF_CLOCK_GATE_DISABLE		(1 << 14)
1437 # define I965_MAWB_CLOCK_GATE_DISABLE		(1 << 13)
1438 # define I965_EM_CLOCK_GATE_DISABLE		(1 << 12)
1439 # define I965_UC_CLOCK_GATE_DISABLE		(1 << 11)
1440 # define I965_SI_CLOCK_GATE_DISABLE		(1 << 6)
1441 # define I965_MT_CLOCK_GATE_DISABLE		(1 << 5)
1442 # define I965_PL_CLOCK_GATE_DISABLE		(1 << 4)
1443 # define I965_DG_CLOCK_GATE_DISABLE		(1 << 3)
1444 # define I965_QC_CLOCK_GATE_DISABLE		(1 << 2)
1445 # define I965_FT_CLOCK_GATE_DISABLE		(1 << 1)
1446 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1447 
1448 #define RENCLK_GATE_D2		0x6208
1449 #define VF_UNIT_CLOCK_GATE_DISABLE		(1 << 9)
1450 #define GS_UNIT_CLOCK_GATE_DISABLE		(1 << 7)
1451 #define CL_UNIT_CLOCK_GATE_DISABLE		(1 << 6)
1452 #define RAMCLK_GATE_D		0x6210		/* CRL only */
1453 #define DEUC			0x6214          /* CRL only */
1454 
1455 #define FW_BLC_SELF_VLV		(VLV_DISPLAY_BASE + 0x6500)
1456 #define  FW_CSPWRDWNEN		(1<<15)
1457 
1458 #define MI_ARB_VLV		(VLV_DISPLAY_BASE + 0x6504)
1459 
1460 /*
1461  * Palette regs
1462  */
1463 
1464 #define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
1465 #define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
1466 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1467 
1468 /* MCH MMIO space */
1469 
1470 /*
1471  * MCHBAR mirror.
1472  *
1473  * This mirrors the MCHBAR MMIO space whose location is determined by
1474  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1475  * every way.  It is not accessible from the CP register read instructions.
1476  *
1477  */
1478 #define MCHBAR_MIRROR_BASE	0x10000
1479 
1480 #define MCHBAR_MIRROR_BASE_SNB	0x140000
1481 
1482 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1483 #define DCLK 0x5e04
1484 
1485 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1486 #define DCC			0x10200
1487 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
1488 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
1489 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
1490 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
1491 #define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
1492 #define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
1493 
1494 /** Pineview MCH register contains DDR3 setting */
1495 #define CSHRDDR3CTL            0x101a8
1496 #define CSHRDDR3CTL_DDR3       (1 << 2)
1497 
1498 /** 965 MCH register controlling DRAM channel configuration */
1499 #define C0DRB3			0x10206
1500 #define C1DRB3			0x10606
1501 
1502 /** snb MCH registers for reading the DRAM channel configuration */
1503 #define MAD_DIMM_C0			(MCHBAR_MIRROR_BASE_SNB + 0x5004)
1504 #define MAD_DIMM_C1			(MCHBAR_MIRROR_BASE_SNB + 0x5008)
1505 #define MAD_DIMM_C2			(MCHBAR_MIRROR_BASE_SNB + 0x500C)
1506 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
1507 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
1508 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
1509 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
1510 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
1511 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
1512 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
1513 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
1514 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
1515 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
1516 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
1517 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
1518 /* DIMM sizes are in multiples of 256mb. */
1519 #define   MAD_DIMM_B_SIZE_SHIFT		8
1520 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
1521 #define   MAD_DIMM_A_SIZE_SHIFT		0
1522 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
1523 
1524 /** snb MCH registers for priority tuning */
1525 #define MCH_SSKPD			(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1526 #define   MCH_SSKPD_WM0_MASK		0x3f
1527 #define   MCH_SSKPD_WM0_VAL		0xc
1528 
1529 /* Clocking configuration register */
1530 #define CLKCFG			0x10c00
1531 #define CLKCFG_FSB_400					(5 << 0)	/* hrawclk 100 */
1532 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
1533 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
1534 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
1535 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
1536 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
1537 /* Note, below two are guess */
1538 #define CLKCFG_FSB_1600					(4 << 0)	/* hrawclk 400 */
1539 #define CLKCFG_FSB_1600_ALT				(0 << 0)	/* hrawclk 400 */
1540 #define CLKCFG_FSB_MASK					(7 << 0)
1541 #define CLKCFG_MEM_533					(1 << 4)
1542 #define CLKCFG_MEM_667					(2 << 4)
1543 #define CLKCFG_MEM_800					(3 << 4)
1544 #define CLKCFG_MEM_MASK					(7 << 4)
1545 
1546 #define TSC1			0x11001
1547 #define   TSE			(1<<0)
1548 #define TR1			0x11006
1549 #define TSFS			0x11020
1550 #define   TSFS_SLOPE_MASK	0x0000ff00
1551 #define   TSFS_SLOPE_SHIFT	8
1552 #define   TSFS_INTR_MASK	0x000000ff
1553 
1554 #define CRSTANDVID		0x11100
1555 #define PXVFREQ_BASE		0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1556 #define   PXVFREQ_PX_MASK	0x7f000000
1557 #define   PXVFREQ_PX_SHIFT	24
1558 #define VIDFREQ_BASE		0x11110
1559 #define VIDFREQ1		0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1560 #define VIDFREQ2		0x11114
1561 #define VIDFREQ3		0x11118
1562 #define VIDFREQ4		0x1111c
1563 #define   VIDFREQ_P0_MASK	0x1f000000
1564 #define   VIDFREQ_P0_SHIFT	24
1565 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
1566 #define   VIDFREQ_P0_CSCLK_SHIFT 20
1567 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
1568 #define   VIDFREQ_P0_CRCLK_SHIFT 16
1569 #define   VIDFREQ_P1_MASK	0x00001f00
1570 #define   VIDFREQ_P1_SHIFT	8
1571 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
1572 #define   VIDFREQ_P1_CSCLK_SHIFT 4
1573 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
1574 #define INTTOEXT_BASE_ILK	0x11300
1575 #define INTTOEXT_BASE		0x11120 /* INTTOEXT1-8 (0x1113c) */
1576 #define   INTTOEXT_MAP3_SHIFT	24
1577 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
1578 #define   INTTOEXT_MAP2_SHIFT	16
1579 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
1580 #define   INTTOEXT_MAP1_SHIFT	8
1581 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
1582 #define   INTTOEXT_MAP0_SHIFT	0
1583 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
1584 #define MEMSWCTL		0x11170 /* Ironlake only */
1585 #define   MEMCTL_CMD_MASK	0xe000
1586 #define   MEMCTL_CMD_SHIFT	13
1587 #define   MEMCTL_CMD_RCLK_OFF	0
1588 #define   MEMCTL_CMD_RCLK_ON	1
1589 #define   MEMCTL_CMD_CHFREQ	2
1590 #define   MEMCTL_CMD_CHVID	3
1591 #define   MEMCTL_CMD_VMMOFF	4
1592 #define   MEMCTL_CMD_VMMON	5
1593 #define   MEMCTL_CMD_STS	(1<<12) /* write 1 triggers command, clears
1594 					   when command complete */
1595 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
1596 #define   MEMCTL_FREQ_SHIFT	8
1597 #define   MEMCTL_SFCAVM		(1<<7)
1598 #define   MEMCTL_TGT_VID_MASK	0x007f
1599 #define MEMIHYST		0x1117c
1600 #define MEMINTREN		0x11180 /* 16 bits */
1601 #define   MEMINT_RSEXIT_EN	(1<<8)
1602 #define   MEMINT_CX_SUPR_EN	(1<<7)
1603 #define   MEMINT_CONT_BUSY_EN	(1<<6)
1604 #define   MEMINT_AVG_BUSY_EN	(1<<5)
1605 #define   MEMINT_EVAL_CHG_EN	(1<<4)
1606 #define   MEMINT_MON_IDLE_EN	(1<<3)
1607 #define   MEMINT_UP_EVAL_EN	(1<<2)
1608 #define   MEMINT_DOWN_EVAL_EN	(1<<1)
1609 #define   MEMINT_SW_CMD_EN	(1<<0)
1610 #define MEMINTRSTR		0x11182 /* 16 bits */
1611 #define   MEM_RSEXIT_MASK	0xc000
1612 #define   MEM_RSEXIT_SHIFT	14
1613 #define   MEM_CONT_BUSY_MASK	0x3000
1614 #define   MEM_CONT_BUSY_SHIFT	12
1615 #define   MEM_AVG_BUSY_MASK	0x0c00
1616 #define   MEM_AVG_BUSY_SHIFT	10
1617 #define   MEM_EVAL_CHG_MASK	0x0300
1618 #define   MEM_EVAL_BUSY_SHIFT	8
1619 #define   MEM_MON_IDLE_MASK	0x00c0
1620 #define   MEM_MON_IDLE_SHIFT	6
1621 #define   MEM_UP_EVAL_MASK	0x0030
1622 #define   MEM_UP_EVAL_SHIFT	4
1623 #define   MEM_DOWN_EVAL_MASK	0x000c
1624 #define   MEM_DOWN_EVAL_SHIFT	2
1625 #define   MEM_SW_CMD_MASK	0x0003
1626 #define   MEM_INT_STEER_GFX	0
1627 #define   MEM_INT_STEER_CMR	1
1628 #define   MEM_INT_STEER_SMI	2
1629 #define   MEM_INT_STEER_SCI	3
1630 #define MEMINTRSTS		0x11184
1631 #define   MEMINT_RSEXIT		(1<<7)
1632 #define   MEMINT_CONT_BUSY	(1<<6)
1633 #define   MEMINT_AVG_BUSY	(1<<5)
1634 #define   MEMINT_EVAL_CHG	(1<<4)
1635 #define   MEMINT_MON_IDLE	(1<<3)
1636 #define   MEMINT_UP_EVAL	(1<<2)
1637 #define   MEMINT_DOWN_EVAL	(1<<1)
1638 #define   MEMINT_SW_CMD		(1<<0)
1639 #define MEMMODECTL		0x11190
1640 #define   MEMMODE_BOOST_EN	(1UL<<31)
1641 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1642 #define   MEMMODE_BOOST_FREQ_SHIFT 24
1643 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
1644 #define   MEMMODE_IDLE_MODE_SHIFT 16
1645 #define   MEMMODE_IDLE_MODE_EVAL 0
1646 #define   MEMMODE_IDLE_MODE_CONT 1
1647 #define   MEMMODE_HWIDLE_EN	(1<<15)
1648 #define   MEMMODE_SWMODE_EN	(1<<14)
1649 #define   MEMMODE_RCLK_GATE	(1<<13)
1650 #define   MEMMODE_HW_UPDATE	(1<<12)
1651 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
1652 #define   MEMMODE_FSTART_SHIFT	8
1653 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
1654 #define   MEMMODE_FMAX_SHIFT	4
1655 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
1656 #define RCBMAXAVG		0x1119c
1657 #define MEMSWCTL2		0x1119e /* Cantiga only */
1658 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
1659 #define   SWMEMCMD_RENDER_ON	(1 << 13)
1660 #define   SWMEMCMD_SWFREQ	(2 << 13)
1661 #define   SWMEMCMD_TARVID	(3 << 13)
1662 #define   SWMEMCMD_VRM_OFF	(4 << 13)
1663 #define   SWMEMCMD_VRM_ON	(5 << 13)
1664 #define   CMDSTS		(1<<12)
1665 #define   SFCAVM		(1<<11)
1666 #define   SWFREQ_MASK		0x0380 /* P0-7 */
1667 #define   SWFREQ_SHIFT		7
1668 #define   TARVID_MASK		0x001f
1669 #define MEMSTAT_CTG		0x111a0
1670 #define RCBMINAVG		0x111a0
1671 #define RCUPEI			0x111b0
1672 #define RCDNEI			0x111b4
1673 #define RSTDBYCTL		0x111b8
1674 #define   RS1EN			(1UL<<31)
1675 #define   RS2EN			(1UL<<30)
1676 #define   RS3EN			(1<<29)
1677 #define   D3RS3EN		(1<<28) /* Display D3 imlies RS3 */
1678 #define   SWPROMORSX		(1<<27) /* RSx promotion timers ignored */
1679 #define   RCWAKERW		(1<<26) /* Resetwarn from PCH causes wakeup */
1680 #define   DPRSLPVREN		(1<<25) /* Fast voltage ramp enable */
1681 #define   GFXTGHYST		(1<<24) /* Hysteresis to allow trunk gating */
1682 #define   RCX_SW_EXIT		(1<<23) /* Leave RSx and prevent re-entry */
1683 #define   RSX_STATUS_MASK	(7<<20)
1684 #define   RSX_STATUS_ON		(0<<20)
1685 #define   RSX_STATUS_RC1	(1<<20)
1686 #define   RSX_STATUS_RC1E	(2<<20)
1687 #define   RSX_STATUS_RS1	(3<<20)
1688 #define   RSX_STATUS_RS2	(4<<20) /* aka rc6 */
1689 #define   RSX_STATUS_RSVD	(5<<20) /* deep rc6 unsupported on ilk */
1690 #define   RSX_STATUS_RS3	(6<<20) /* rs3 unsupported on ilk */
1691 #define   RSX_STATUS_RSVD2	(7<<20)
1692 #define   UWRCRSXE		(1<<19) /* wake counter limit prevents rsx */
1693 #define   RSCRP			(1<<18) /* rs requests control on rs1/2 reqs */
1694 #define   JRSC			(1<<17) /* rsx coupled to cpu c-state */
1695 #define   RS2INC0		(1<<16) /* allow rs2 in cpu c0 */
1696 #define   RS1CONTSAV_MASK	(3<<14)
1697 #define   RS1CONTSAV_NO_RS1	(0<<14) /* rs1 doesn't save/restore context */
1698 #define   RS1CONTSAV_RSVD	(1<<14)
1699 #define   RS1CONTSAV_SAVE_RS1	(2<<14) /* rs1 saves context */
1700 #define   RS1CONTSAV_FULL_RS1	(3<<14) /* rs1 saves and restores context */
1701 #define   NORMSLEXLAT_MASK	(3<<12)
1702 #define   SLOW_RS123		(0<<12)
1703 #define   SLOW_RS23		(1<<12)
1704 #define   SLOW_RS3		(2<<12)
1705 #define   NORMAL_RS123		(3<<12)
1706 #define   RCMODE_TIMEOUT	(1<<11) /* 0 is eval interval method */
1707 #define   IMPROMOEN		(1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1708 #define   RCENTSYNC		(1<<9) /* rs coupled to cpu c-state (3/6/7) */
1709 #define   STATELOCK		(1<<7) /* locked to rs_cstate if 0 */
1710 #define   RS_CSTATE_MASK	(3<<4)
1711 #define   RS_CSTATE_C367_RS1	(0<<4)
1712 #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1713 #define   RS_CSTATE_RSVD	(2<<4)
1714 #define   RS_CSTATE_C367_RS2	(3<<4)
1715 #define   REDSAVES		(1<<3) /* no context save if was idle during rs0 */
1716 #define   REDRESTORES		(1<<2) /* no restore if was idle during rs0 */
1717 #define VIDCTL			0x111c0
1718 #define VIDSTS			0x111c8
1719 #define VIDSTART		0x111cc /* 8 bits */
1720 #define MEMSTAT_ILK			0x111f8
1721 #define   MEMSTAT_VID_MASK	0x7f00
1722 #define   MEMSTAT_VID_SHIFT	8
1723 #define   MEMSTAT_PSTATE_MASK	0x00f8
1724 #define   MEMSTAT_PSTATE_SHIFT  3
1725 #define   MEMSTAT_MON_ACTV	(1<<2)
1726 #define   MEMSTAT_SRC_CTL_MASK	0x0003
1727 #define   MEMSTAT_SRC_CTL_CORE	0
1728 #define   MEMSTAT_SRC_CTL_TRB	1
1729 #define   MEMSTAT_SRC_CTL_THM	2
1730 #define   MEMSTAT_SRC_CTL_STDBY 3
1731 #define RCPREVBSYTUPAVG		0x113b8
1732 #define RCPREVBSYTDNAVG		0x113bc
1733 #define PMMISC			0x11214
1734 #define   MCPPCE_EN		(1<<0) /* enable PM_MSG from PCH->MPC */
1735 #define SDEW			0x1124c
1736 #define CSIEW0			0x11250
1737 #define CSIEW1			0x11254
1738 #define CSIEW2			0x11258
1739 #define PEW			0x1125c
1740 #define DEW			0x11270
1741 #define MCHAFE			0x112c0
1742 #define CSIEC			0x112e0
1743 #define DMIEC			0x112e4
1744 #define DDREC			0x112e8
1745 #define PEG0EC			0x112ec
1746 #define PEG1EC			0x112f0
1747 #define GFXEC			0x112f4
1748 #define RPPREVBSYTUPAVG		0x113b8
1749 #define RPPREVBSYTDNAVG		0x113bc
1750 #define ECR			0x11600
1751 #define   ECR_GPFE		(1UL<<31)
1752 #define   ECR_IMONE		(1<<30)
1753 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
1754 #define OGW0			0x11608
1755 #define OGW1			0x1160c
1756 #define EG0			0x11610
1757 #define EG1			0x11614
1758 #define EG2			0x11618
1759 #define EG3			0x1161c
1760 #define EG4			0x11620
1761 #define EG5			0x11624
1762 #define EG6			0x11628
1763 #define EG7			0x1162c
1764 #define PXW			0x11664
1765 #define PXWL			0x11680
1766 #define LCFUSE02		0x116c0
1767 #define   LCFUSE_HIV_MASK	0x000000ff
1768 #define CSIPLL0			0x12c10
1769 #define DDRMPLL1		0X12c20
1770 #define PEG_BAND_GAP_DATA	0x14d68
1771 
1772 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1773 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1774 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1775 
1776 #define GEN6_GT_PERF_STATUS	0x145948
1777 #define GEN6_RP_STATE_LIMITS	0x145994
1778 #define GEN6_RP_STATE_CAP	0x145998
1779 
1780 /*
1781  * Logical Context regs
1782  */
1783 #define CCID			0x2180
1784 #define   CCID_EN		(1<<0)
1785 #define CXT_SIZE		0x21a0
1786 #define GEN6_CXT_POWER_SIZE(cxt_reg)	((cxt_reg >> 24) & 0x3f)
1787 #define GEN6_CXT_RING_SIZE(cxt_reg)	((cxt_reg >> 18) & 0x3f)
1788 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	((cxt_reg >> 12) & 0x3f)
1789 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	((cxt_reg >> 6) & 0x3f)
1790 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	((cxt_reg >> 0) & 0x3f)
1791 #define GEN6_CXT_TOTAL_SIZE(cxt_reg)	(GEN6_CXT_POWER_SIZE(cxt_reg) + \
1792 					GEN6_CXT_RING_SIZE(cxt_reg) + \
1793 					GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1794 					GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1795 					GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1796 #define GEN7_CXT_SIZE		0x21a8
1797 #define GEN7_CXT_POWER_SIZE(ctx_reg)	((ctx_reg >> 25) & 0x7f)
1798 #define GEN7_CXT_RING_SIZE(ctx_reg)	((ctx_reg >> 22) & 0x7)
1799 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	((ctx_reg >> 16) & 0x3f)
1800 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	((ctx_reg >> 9) & 0x7f)
1801 #define GEN7_CXT_GT1_SIZE(ctx_reg)	((ctx_reg >> 6) & 0x7)
1802 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	((ctx_reg >> 0) & 0x3f)
1803 #define GEN7_CXT_TOTAL_SIZE(ctx_reg)	(GEN7_CXT_POWER_SIZE(ctx_reg) + \
1804 					 GEN7_CXT_RING_SIZE(ctx_reg) + \
1805 					 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1806 					 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1807 					 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1808 					 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1809 /* Haswell does have the CXT_SIZE register however it does not appear to be
1810  * valid. Now, docs explain in dwords what is in the context object. The full
1811  * size is 70720 bytes, however, the power context and execlist context will
1812  * never be saved (power context is stored elsewhere, and execlists don't work
1813  * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1814  */
1815 #define HSW_CXT_TOTAL_SIZE		(17 * PAGE_SIZE)
1816 
1817 /*
1818  * Overlay regs
1819  */
1820 
1821 #define OVADD			0x30000
1822 #define DOVSTA			0x30008
1823 #define OC_BUF			(0x3<<20)
1824 #define OGAMC5			0x30010
1825 #define OGAMC4			0x30014
1826 #define OGAMC3			0x30018
1827 #define OGAMC2			0x3001c
1828 #define OGAMC1			0x30020
1829 #define OGAMC0			0x30024
1830 
1831 /*
1832  * Display engine regs
1833  */
1834 
1835 /* Pipe A timing regs */
1836 #define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
1837 #define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
1838 #define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
1839 #define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
1840 #define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
1841 #define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
1842 #define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
1843 #define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
1844 #define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
1845 
1846 /* Pipe B timing regs */
1847 #define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
1848 #define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
1849 #define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
1850 #define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
1851 #define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
1852 #define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
1853 #define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
1854 #define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
1855 #define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
1856 
1857 
1858 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1859 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1860 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1861 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1862 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1863 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1864 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1865 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1866 
1867 /* VGA port control */
1868 #define ADPA			0x61100
1869 #define PCH_ADPA                0xe1100
1870 #define VLV_ADPA		(VLV_DISPLAY_BASE + ADPA)
1871 
1872 #define   ADPA_DAC_ENABLE	(1UL<<31)  /* OSOL_i915 */
1873 #define   ADPA_DAC_DISABLE	0
1874 #define   ADPA_PIPE_SELECT_MASK	(1<<30)
1875 #define   ADPA_PIPE_A_SELECT	0
1876 #define   ADPA_PIPE_B_SELECT	(1<<30)
1877 #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1878 /* CPT uses bits 29:30 for pch transcoder select */
1879 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
1880 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
1881 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
1882 #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1883 #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
1884 #define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
1885 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
1886 #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
1887 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
1888 #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
1889 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
1890 #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
1891 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
1892 #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
1893 #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
1894 #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
1895 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
1896 #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
1897 #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1898 #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
1899 #define   ADPA_SETS_HVPOLARITY	0
1900 #define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
1901 #define   ADPA_VSYNC_CNTL_ENABLE 0
1902 #define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
1903 #define   ADPA_HSYNC_CNTL_ENABLE 0
1904 #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1905 #define   ADPA_VSYNC_ACTIVE_LOW	0
1906 #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1907 #define   ADPA_HSYNC_ACTIVE_LOW	0
1908 #define   ADPA_DPMS_MASK	(~(3<<10))
1909 #define   ADPA_DPMS_ON		(0<<10)
1910 #define   ADPA_DPMS_SUSPEND	(1<<10)
1911 #define   ADPA_DPMS_STANDBY	(2<<10)
1912 #define   ADPA_DPMS_OFF		(3<<10)
1913 
1914 
1915 /* Hotplug control (945+ only) */
1916 #define PORT_HOTPLUG_EN		(dev_priv->info->display_mmio_offset + 0x61110)
1917 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
1918 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
1919 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
1920 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
1921 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
1922 #define   TV_HOTPLUG_INT_EN			(1 << 18)
1923 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
1924 #define HOTPLUG_INT_EN_MASK			(PORTB_HOTPLUG_INT_EN | \
1925 						 PORTC_HOTPLUG_INT_EN | \
1926 						 PORTD_HOTPLUG_INT_EN | \
1927 						 SDVOC_HOTPLUG_INT_EN | \
1928 						 SDVOB_HOTPLUG_INT_EN | \
1929 						 CRT_HOTPLUG_INT_EN)
1930 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
1931 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
1932 /* must use period 64 on GM45 according to docs */
1933 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
1934 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
1935 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
1936 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
1937 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
1938 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
1939 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
1940 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
1941 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
1942 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
1943 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
1944 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
1945 
1946 #define PORT_HOTPLUG_STAT	(dev_priv->info->display_mmio_offset + 0x61114)
1947 /*
1948  * HDMI/DP bits are gen4+
1949  *
1950  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
1951  * Please check the detailed lore in the commit message for for experimental
1952  * evidence.
1953  */
1954 #define   PORTD_HOTPLUG_LIVE_STATUS               (1 << 29)
1955 #define   PORTC_HOTPLUG_LIVE_STATUS               (1 << 28)
1956 #define   PORTB_HOTPLUG_LIVE_STATUS               (1 << 27)
1957 #define   PORTD_HOTPLUG_INT_STATUS		(3 << 21)
1958 #define   PORTC_HOTPLUG_INT_STATUS		(3 << 19)
1959 #define   PORTB_HOTPLUG_INT_STATUS		(3 << 17)
1960 /* CRT/TV common between gen3+ */
1961 #define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
1962 #define   TV_HOTPLUG_INT_STATUS			(1 << 10)
1963 #define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
1964 #define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
1965 #define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
1966 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
1967 /* SDVO is different across gen3/4 */
1968 #define   SDVOC_HOTPLUG_INT_STATUS_G4X		(1 << 3)
1969 #define   SDVOB_HOTPLUG_INT_STATUS_G4X		(1 << 2)
1970 /*
1971  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
1972  * since reality corrobates that they're the same as on gen3. But keep these
1973  * bits here (and the comment!) to help any other lost wanderers back onto the
1974  * right tracks.
1975  */
1976 #define   SDVOC_HOTPLUG_INT_STATUS_I965		(3 << 4)
1977 #define   SDVOB_HOTPLUG_INT_STATUS_I965		(3 << 2)
1978 #define   SDVOC_HOTPLUG_INT_STATUS_I915		(1 << 7)
1979 #define   SDVOB_HOTPLUG_INT_STATUS_I915		(1 << 6)
1980 #define   HOTPLUG_INT_STATUS_G4X		(CRT_HOTPLUG_INT_STATUS | \
1981 						 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1982 						 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1983 						 PORTB_HOTPLUG_INT_STATUS | \
1984 						 PORTC_HOTPLUG_INT_STATUS | \
1985 						 PORTD_HOTPLUG_INT_STATUS)
1986 
1987 #define HOTPLUG_INT_STATUS_I915			(CRT_HOTPLUG_INT_STATUS | \
1988 						 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1989 						 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1990 						 PORTB_HOTPLUG_INT_STATUS | \
1991 						 PORTC_HOTPLUG_INT_STATUS | \
1992 						 PORTD_HOTPLUG_INT_STATUS)
1993 
1994 /* SDVO and HDMI port control.
1995  * The same register may be used for SDVO or HDMI */
1996 #define GEN3_SDVOB	0x61140
1997 #define GEN3_SDVOC	0x61160
1998 #define GEN4_HDMIB	GEN3_SDVOB
1999 #define GEN4_HDMIC	GEN3_SDVOC
2000 #define PCH_SDVOB	0xe1140
2001 #define PCH_HDMIB	PCH_SDVOB
2002 #define PCH_HDMIC	0xe1150
2003 #define PCH_HDMID	0xe1160
2004 
2005 /* Gen 3 SDVO bits: */
2006 #define   SDVO_ENABLE				(1UL << 31)
2007 #define   SDVO_PIPE_SEL(pipe)			((pipe) << 30)
2008 #define   SDVO_PIPE_SEL_MASK			(1 << 30)
2009 #define   SDVO_PIPE_B_SELECT			(1 << 30)
2010 #define   SDVO_STALL_SELECT			(1 << 29)
2011 #define   SDVO_INTERRUPT_ENABLE			(1 << 26)
2012 /**
2013  * 915G/GM SDVO pixel multiplier.
2014  * Programmed value is multiplier - 1, up to 5x.
2015  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2016  */
2017 #define   SDVO_PORT_MULTIPLY_MASK		(7 << 23)
2018 #define   SDVO_PORT_MULTIPLY_SHIFT		23
2019 #define   SDVO_PHASE_SELECT_MASK		(15 << 19)
2020 #define   SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
2021 #define   SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
2022 #define   SDVOC_GANG_MODE			(1 << 16) /* Port C only */
2023 #define   SDVO_BORDER_ENABLE			(1 << 7) /* SDVO only */
2024 #define   SDVOB_PCIE_CONCURRENCY		(1 << 3) /* Port B only */
2025 #define   SDVO_DETECTED				(1 << 2)
2026 /* Bits to be preserved when writing */
2027 #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2028 			       SDVO_INTERRUPT_ENABLE)
2029 #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2030 
2031 /* Gen 4 SDVO/HDMI bits: */
2032 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
2033 #define   SDVO_ENCODING_SDVO			(0 << 10)
2034 #define   SDVO_ENCODING_HDMI			(2 << 10)
2035 #define   HDMI_MODE_SELECT_HDMI			(1 << 9) /* HDMI only */
2036 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
2037 #define   HDMI_COLOR_RANGE_16_235		(1 << 8) /* HDMI only */
2038 #define   SDVO_AUDIO_ENABLE			(1 << 6)
2039 /* VSYNC/HSYNC bits new with 965, default is to be set */
2040 #define   SDVO_VSYNC_ACTIVE_HIGH		(1 << 4)
2041 #define   SDVO_HSYNC_ACTIVE_HIGH		(1 << 3)
2042 
2043 /* Gen 5 (IBX) SDVO/HDMI bits: */
2044 #define   HDMI_COLOR_FORMAT_12bpc		(3 << 26) /* HDMI only */
2045 #define   SDVOB_HOTPLUG_ENABLE			(1 << 23) /* SDVO only */
2046 
2047 /* Gen 6 (CPT) SDVO/HDMI bits: */
2048 #define   SDVO_PIPE_SEL_CPT(pipe)		((pipe) << 29)
2049 #define   SDVO_PIPE_SEL_MASK_CPT		(3 << 29)
2050 
2051 /* DVO port control */
2052 #define DVOA			0x61120
2053 #define DVOB			0x61140
2054 #define DVOC			0x61160
2055 #define   DVO_ENABLE			(1UL << 31)  /* OSOL_i915 */
2056 #define   DVO_PIPE_B_SELECT		(1 << 30)
2057 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
2058 #define   DVO_PIPE_STALL		(1 << 28)
2059 #define   DVO_PIPE_STALL_TV		(2 << 28)
2060 #define   DVO_PIPE_STALL_MASK		(3 << 28)
2061 #define   DVO_USE_VGA_SYNC		(1 << 15)
2062 #define   DVO_DATA_ORDER_I740		(0 << 14)
2063 #define   DVO_DATA_ORDER_FP		(1 << 14)
2064 #define   DVO_VSYNC_DISABLE		(1 << 11)
2065 #define   DVO_HSYNC_DISABLE		(1 << 10)
2066 #define   DVO_VSYNC_TRISTATE		(1 << 9)
2067 #define   DVO_HSYNC_TRISTATE		(1 << 8)
2068 #define   DVO_BORDER_ENABLE		(1 << 7)
2069 #define   DVO_DATA_ORDER_GBRG		(1 << 6)
2070 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
2071 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
2072 #define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
2073 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
2074 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
2075 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
2076 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
2077 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
2078 #define   DVO_PRESERVE_MASK		(0x7<<24)
2079 #define DVOA_SRCDIM		0x61124
2080 #define DVOB_SRCDIM		0x61144
2081 #define DVOC_SRCDIM		0x61164
2082 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
2083 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
2084 
2085 /* LVDS port control */
2086 #define LVDS			0x61180
2087 /*
2088  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
2089  * the DPLL semantics change when the LVDS is assigned to that pipe.
2090  */
2091 #define   LVDS_PORT_EN			(1UL << 31)  /* OSOL_i915 */
2092 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
2093 #define   LVDS_PIPEB_SELECT		(1 << 30)
2094 #define   LVDS_PIPE_MASK		(1 << 30)
2095 #define   LVDS_PIPE(pipe)		((pipe) << 30)
2096 /* LVDS dithering flag on 965/g4x platform */
2097 #define   LVDS_ENABLE_DITHER		(1 << 25)
2098 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2099 #define   LVDS_VSYNC_POLARITY		(1 << 21)
2100 #define   LVDS_HSYNC_POLARITY		(1 << 20)
2101 
2102 /* Enable border for unscaled (or aspect-scaled) display */
2103 #define   LVDS_BORDER_ENABLE		(1 << 15)
2104 /*
2105  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2106  * pixel.
2107  */
2108 #define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
2109 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
2110 #define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
2111 /*
2112  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2113  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2114  * on.
2115  */
2116 #define   LVDS_A3_POWER_MASK		(3 << 6)
2117 #define   LVDS_A3_POWER_DOWN		(0 << 6)
2118 #define   LVDS_A3_POWER_UP		(3 << 6)
2119 /*
2120  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
2121  * is set.
2122  */
2123 #define   LVDS_CLKB_POWER_MASK		(3 << 4)
2124 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
2125 #define   LVDS_CLKB_POWER_UP		(3 << 4)
2126 /*
2127  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
2128  * setting for whether we are in dual-channel mode.  The B3 pair will
2129  * additionally only be powered up when LVDS_A3_POWER_UP is set.
2130  */
2131 #define   LVDS_B0B3_POWER_MASK		(3 << 2)
2132 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
2133 #define   LVDS_B0B3_POWER_UP		(3 << 2)
2134 
2135 /* Video Data Island Packet control */
2136 #define VIDEO_DIP_DATA		0x61178
2137 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2138  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2139  * of the infoframe structure specified by CEA-861. */
2140 #define   VIDEO_DIP_DATA_SIZE	32
2141 #define VIDEO_DIP_CTL		0x61170
2142 /* Pre HSW: */
2143 #define   VIDEO_DIP_ENABLE		(1UL << 31)
2144 #define   VIDEO_DIP_PORT_B		(1 << 29)
2145 #define   VIDEO_DIP_PORT_C		(2 << 29)
2146 #define   VIDEO_DIP_PORT_D		(3 << 29)
2147 #define   VIDEO_DIP_PORT_MASK		(3 << 29)
2148 #define   VIDEO_DIP_ENABLE_GCP		(1 << 25)
2149 #define   VIDEO_DIP_ENABLE_AVI		(1 << 21)
2150 #define   VIDEO_DIP_ENABLE_VENDOR	(2 << 21)
2151 #define   VIDEO_DIP_ENABLE_GAMUT	(4 << 21)
2152 #define   VIDEO_DIP_ENABLE_SPD		(8 << 21)
2153 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
2154 #define   VIDEO_DIP_SELECT_VENDOR	(1 << 19)
2155 #define   VIDEO_DIP_SELECT_SPD		(3 << 19)
2156 #define   VIDEO_DIP_SELECT_MASK		(3 << 19)
2157 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
2158 #define   VIDEO_DIP_FREQ_VSYNC		(1 << 16)
2159 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
2160 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
2161 /* HSW and later: */
2162 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
2163 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
2164 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
2165 #define   VIDEO_DIP_ENABLE_VS_HSW	(1 << 8)
2166 #define   VIDEO_DIP_ENABLE_GMP_HSW	(1 << 4)
2167 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2168 
2169 /* Panel power sequencing */
2170 #define PP_STATUS	0x61200
2171 #define   PP_ON		(1UL << 31)  /* OSOL_i915 */
2172 /*
2173  * Indicates that all dependencies of the panel are on:
2174  *
2175  * - PLL enabled
2176  * - pipe enabled
2177  * - LVDS/DVOB/DVOC on
2178  */
2179 #define   PP_READY		(1 << 30)
2180 #define   PP_SEQUENCE_NONE	(0 << 28)
2181 #define   PP_SEQUENCE_POWER_UP	(1 << 28)
2182 #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
2183 #define   PP_SEQUENCE_MASK	(3 << 28)
2184 #define   PP_SEQUENCE_SHIFT	28
2185 #define   PP_CYCLE_DELAY_ACTIVE	(1 << 27)
2186 #define   PP_SEQUENCE_STATE_MASK 0x0000000f
2187 #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
2188 #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
2189 #define   PP_SEQUENCE_STATE_OFF_S0_2	(0x2 << 0)
2190 #define   PP_SEQUENCE_STATE_OFF_S0_3	(0x3 << 0)
2191 #define   PP_SEQUENCE_STATE_ON_IDLE	(0x8 << 0)
2192 #define   PP_SEQUENCE_STATE_ON_S1_0	(0x9 << 0)
2193 #define   PP_SEQUENCE_STATE_ON_S1_2	(0xa << 0)
2194 #define   PP_SEQUENCE_STATE_ON_S1_3	(0xb << 0)
2195 #define   PP_SEQUENCE_STATE_RESET	(0xf << 0)
2196 #define PP_CONTROL	0x61204
2197 #define   POWER_TARGET_ON	(1 << 0)
2198 #define PP_ON_DELAYS	0x61208
2199 #define PP_OFF_DELAYS	0x6120c
2200 #define PP_DIVISOR	0x61210
2201 
2202 /* Panel fitting */
2203 #define PFIT_CONTROL	(dev_priv->info->display_mmio_offset + 0x61230)
2204 #define   PFIT_ENABLE		(1UL << 31)
2205 #define   PFIT_PIPE_MASK	(3 << 29)
2206 #define   PFIT_PIPE_SHIFT	29
2207 #define   VERT_INTERP_DISABLE	(0 << 10)
2208 #define   VERT_INTERP_BILINEAR	(1 << 10)
2209 #define   VERT_INTERP_MASK	(3 << 10)
2210 #define   VERT_AUTO_SCALE	(1 << 9)
2211 #define   HORIZ_INTERP_DISABLE	(0 << 6)
2212 #define   HORIZ_INTERP_BILINEAR	(1 << 6)
2213 #define   HORIZ_INTERP_MASK	(3 << 6)
2214 #define   HORIZ_AUTO_SCALE	(1 << 5)
2215 #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
2216 #define   PFIT_FILTER_FUZZY	(0 << 24)
2217 #define   PFIT_SCALING_AUTO	(0 << 26)
2218 #define   PFIT_SCALING_PROGRAMMED (1 << 26)
2219 #define   PFIT_SCALING_PILLAR	(2 << 26)
2220 #define   PFIT_SCALING_LETTER	(3 << 26)
2221 #define PFIT_PGM_RATIOS	(dev_priv->info->display_mmio_offset + 0x61234)
2222 /* Pre-965 */
2223 #define		PFIT_VERT_SCALE_SHIFT		20
2224 #define		PFIT_VERT_SCALE_MASK		0xfff00000
2225 #define		PFIT_HORIZ_SCALE_SHIFT		4
2226 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
2227 /* 965+ */
2228 #define		PFIT_VERT_SCALE_SHIFT_965	16
2229 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
2230 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
2231 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
2232 
2233 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
2234 
2235 /* Backlight control */
2236 #define BLC_PWM_CTL2		0x61250 /* 965+ only */
2237 #define   BLM_PWM_ENABLE		(1UL << 31)
2238 #define   BLM_COMBINATION_MODE (1 << 30)
2239 #define   BLM_PIPE_SELECT		(1 << 29)
2240 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
2241 #define   BLM_PIPE_A			(0 << 29)
2242 #define   BLM_PIPE_B			(1 << 29)
2243 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
2244 #define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
2245 #define   BLM_TRANSCODER_B		BLM_PIPE_B
2246 #define   BLM_TRANSCODER_C		BLM_PIPE_C
2247 #define   BLM_TRANSCODER_EDP		(3 << 29)
2248 #define   BLM_PIPE(pipe)		((pipe) << 29)
2249 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
2250 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
2251 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
2252 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
2253 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
2254 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
2255 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
2256 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
2257 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
2258 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
2259 #define BLC_PWM_CTL		0x61254
2260 /*
2261  * This is the most significant 15 bits of the number of backlight cycles in a
2262  * complete cycle of the modulated backlight control.
2263  *
2264  * The actual value is this field multiplied by two.
2265  */
2266 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
2267 #define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fffUL << 17)  /* OSOL_i915 */
2268 #define   BLM_LEGACY_MODE				(1 << 16)
2269 /*
2270  * This is the number of cycles out of the backlight modulation cycle for which
2271  * the backlight is on.
2272  *
2273  * This field must be no greater than the number of cycles in the complete
2274  * backlight modulation cycle.
2275  */
2276 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
2277 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
2278 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
2279 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
2280 
2281 #define BLC_HIST_CTL	(dev_priv->info->display_mmio_offset + 0x61260)
2282 
2283 /* New registers for PCH-split platforms. Safe where new bits show up, the
2284  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2285 #define BLC_PWM_CPU_CTL2	0x48250
2286 #define BLC_PWM_CPU_CTL		0x48254
2287 
2288 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2289  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2290 #define BLC_PWM_PCH_CTL1	0xc8250
2291 #define   BLM_PCH_PWM_ENABLE			(1UL << 31)
2292 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
2293 #define   BLM_PCH_POLARITY			(1 << 29)
2294 #define BLC_PWM_PCH_CTL2	0xc8254
2295 
2296 /* TV port control */
2297 #define TV_CTL			0x68000
2298 /** Enables the TV encoder */
2299 # define TV_ENC_ENABLE			(1UL << 31)  /* OSOL_i915 */
2300 /** Sources the TV encoder input from pipe B instead of A. */
2301 # define TV_ENC_PIPEB_SELECT		(1 << 30)
2302 /** Outputs composite video (DAC A only) */
2303 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
2304 /** Outputs SVideo video (DAC B/C) */
2305 # define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
2306 /** Outputs Component video (DAC A/B/C) */
2307 # define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
2308 /** Outputs Composite and SVideo (DAC A/B/C) */
2309 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
2310 # define TV_TRILEVEL_SYNC		(1 << 21)
2311 /** Enables slow sync generation (945GM only) */
2312 # define TV_SLOW_SYNC			(1 << 20)
2313 /** Selects 4x oversampling for 480i and 576p */
2314 # define TV_OVERSAMPLE_4X		(0 << 18)
2315 /** Selects 2x oversampling for 720p and 1080i */
2316 # define TV_OVERSAMPLE_2X		(1 << 18)
2317 /** Selects no oversampling for 1080p */
2318 # define TV_OVERSAMPLE_NONE		(2 << 18)
2319 /** Selects 8x oversampling */
2320 # define TV_OVERSAMPLE_8X		(3 << 18)
2321 /** Selects progressive mode rather than interlaced */
2322 # define TV_PROGRESSIVE			(1 << 17)
2323 /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
2324 # define TV_PAL_BURST			(1 << 16)
2325 /** Field for setting delay of Y compared to C */
2326 # define TV_YC_SKEW_MASK		(7 << 12)
2327 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2328 # define TV_ENC_SDP_FIX			(1 << 11)
2329 /**
2330  * Enables a fix for the 915GM only.
2331  *
2332  * Not sure what it does.
2333  */
2334 # define TV_ENC_C0_FIX			(1 << 10)
2335 /** Bits that must be preserved by software */
2336 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2337 # define TV_FUSE_STATE_MASK		(3 << 4)
2338 /** Read-only state that reports all features enabled */
2339 # define TV_FUSE_STATE_ENABLED		(0 << 4)
2340 /** Read-only state that reports that Macrovision is disabled in hardware*/
2341 # define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
2342 /** Read-only state that reports that TV-out is disabled in hardware. */
2343 # define TV_FUSE_STATE_DISABLED		(2 << 4)
2344 /** Normal operation */
2345 # define TV_TEST_MODE_NORMAL		(0 << 0)
2346 /** Encoder test pattern 1 - combo pattern */
2347 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
2348 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2349 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
2350 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2351 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
2352 /** Encoder test pattern 4 - random noise */
2353 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
2354 /** Encoder test pattern 5 - linear color ramps */
2355 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
2356 /**
2357  * This test mode forces the DACs to 50% of full output.
2358  *
2359  * This is used for load detection in combination with TVDAC_SENSE_MASK
2360  */
2361 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
2362 # define TV_TEST_MODE_MASK		(7 << 0)
2363 
2364 #define TV_DAC			0x68004
2365 # define TV_DAC_SAVE		0x00ffff00
2366 /**
2367  * Reports that DAC state change logic has reported change (RO).
2368  *
2369  * This gets cleared when TV_DAC_STATE_EN is cleared
2370 */
2371 # define TVDAC_STATE_CHG		(1UL << 31)  /* OSOL_i915 */
2372 # define TVDAC_SENSE_MASK		(7 << 28)
2373 /** Reports that DAC A voltage is above the detect threshold */
2374 # define TVDAC_A_SENSE			(1 << 30)
2375 /** Reports that DAC B voltage is above the detect threshold */
2376 # define TVDAC_B_SENSE			(1 << 29)
2377 /** Reports that DAC C voltage is above the detect threshold */
2378 # define TVDAC_C_SENSE			(1 << 28)
2379 /**
2380  * Enables DAC state detection logic, for load-based TV detection.
2381  *
2382  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2383  * to off, for load detection to work.
2384  */
2385 # define TVDAC_STATE_CHG_EN		(1 << 27)
2386 /** Sets the DAC A sense value to high */
2387 # define TVDAC_A_SENSE_CTL		(1 << 26)
2388 /** Sets the DAC B sense value to high */
2389 # define TVDAC_B_SENSE_CTL		(1 << 25)
2390 /** Sets the DAC C sense value to high */
2391 # define TVDAC_C_SENSE_CTL		(1 << 24)
2392 /** Overrides the ENC_ENABLE and DAC voltage levels */
2393 # define DAC_CTL_OVERRIDE		(1 << 7)
2394 /** Sets the slew rate.  Must be preserved in software */
2395 # define ENC_TVDAC_SLEW_FAST		(1 << 6)
2396 # define DAC_A_1_3_V			(0 << 4)
2397 # define DAC_A_1_1_V			(1 << 4)
2398 # define DAC_A_0_7_V			(2 << 4)
2399 # define DAC_A_MASK			(3 << 4)
2400 # define DAC_B_1_3_V			(0 << 2)
2401 # define DAC_B_1_1_V			(1 << 2)
2402 # define DAC_B_0_7_V			(2 << 2)
2403 # define DAC_B_MASK			(3 << 2)
2404 # define DAC_C_1_3_V			(0 << 0)
2405 # define DAC_C_1_1_V			(1 << 0)
2406 # define DAC_C_0_7_V			(2 << 0)
2407 # define DAC_C_MASK			(3 << 0)
2408 
2409 /**
2410  * CSC coefficients are stored in a floating point format with 9 bits of
2411  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
2412  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2413  * -1 (0x3) being the only legal negative value.
2414  */
2415 #define TV_CSC_Y		0x68010
2416 # define TV_RY_MASK			0x07ff0000
2417 # define TV_RY_SHIFT			16
2418 # define TV_GY_MASK			0x00000fff
2419 # define TV_GY_SHIFT			0
2420 
2421 #define TV_CSC_Y2		0x68014
2422 # define TV_BY_MASK			0x07ff0000
2423 # define TV_BY_SHIFT			16
2424 /**
2425  * Y attenuation for component video.
2426  *
2427  * Stored in 1.9 fixed point.
2428  */
2429 # define TV_AY_MASK			0x000003ff
2430 # define TV_AY_SHIFT			0
2431 
2432 #define TV_CSC_U		0x68018
2433 # define TV_RU_MASK			0x07ff0000
2434 # define TV_RU_SHIFT			16
2435 # define TV_GU_MASK			0x000007ff
2436 # define TV_GU_SHIFT			0
2437 
2438 #define TV_CSC_U2		0x6801c
2439 # define TV_BU_MASK			0x07ff0000
2440 # define TV_BU_SHIFT			16
2441 /**
2442  * U attenuation for component video.
2443  *
2444  * Stored in 1.9 fixed point.
2445  */
2446 # define TV_AU_MASK			0x000003ff
2447 # define TV_AU_SHIFT			0
2448 
2449 #define TV_CSC_V		0x68020
2450 # define TV_RV_MASK			0x0fff0000
2451 # define TV_RV_SHIFT			16
2452 # define TV_GV_MASK			0x000007ff
2453 # define TV_GV_SHIFT			0
2454 
2455 #define TV_CSC_V2		0x68024
2456 # define TV_BV_MASK			0x07ff0000
2457 # define TV_BV_SHIFT			16
2458 /**
2459  * V attenuation for component video.
2460  *
2461  * Stored in 1.9 fixed point.
2462  */
2463 # define TV_AV_MASK			0x000007ff
2464 # define TV_AV_SHIFT			0
2465 
2466 #define TV_CLR_KNOBS		0x68028
2467 /** 2s-complement brightness adjustment */
2468 # define TV_BRIGHTNESS_MASK		0xff000000
2469 # define TV_BRIGHTNESS_SHIFT		24
2470 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2471 # define TV_CONTRAST_MASK		0x00ff0000
2472 # define TV_CONTRAST_SHIFT		16
2473 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2474 # define TV_SATURATION_MASK		0x0000ff00
2475 # define TV_SATURATION_SHIFT		8
2476 /** Hue adjustment, as an integer phase angle in degrees */
2477 # define TV_HUE_MASK			0x000000ff
2478 # define TV_HUE_SHIFT			0
2479 
2480 #define TV_CLR_LEVEL		0x6802c
2481 /** Controls the DAC level for black */
2482 # define TV_BLACK_LEVEL_MASK		0x01ff0000
2483 # define TV_BLACK_LEVEL_SHIFT		16
2484 /** Controls the DAC level for blanking */
2485 # define TV_BLANK_LEVEL_MASK		0x000001ff
2486 # define TV_BLANK_LEVEL_SHIFT		0
2487 
2488 #define TV_H_CTL_1		0x68030
2489 /** Number of pixels in the hsync. */
2490 # define TV_HSYNC_END_MASK		0x1fff0000
2491 # define TV_HSYNC_END_SHIFT		16
2492 /** Total number of pixels minus one in the line (display and blanking). */
2493 # define TV_HTOTAL_MASK			0x00001fff
2494 # define TV_HTOTAL_SHIFT		0
2495 
2496 #define TV_H_CTL_2		0x68034
2497 /** Enables the colorburst (needed for non-component color) */
2498 # define TV_BURST_ENA			(1UL << 31)  /* OSOL_i915 */
2499 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2500 # define TV_HBURST_START_SHIFT		16
2501 # define TV_HBURST_START_MASK		0x1fff0000
2502 /** Length of the colorburst */
2503 # define TV_HBURST_LEN_SHIFT		0
2504 # define TV_HBURST_LEN_MASK		0x0001fff
2505 
2506 #define TV_H_CTL_3		0x68038
2507 /** End of hblank, measured in pixels minus one from start of hsync */
2508 # define TV_HBLANK_END_SHIFT		16
2509 # define TV_HBLANK_END_MASK		0x1fff0000
2510 /** Start of hblank, measured in pixels minus one from start of hsync */
2511 # define TV_HBLANK_START_SHIFT		0
2512 # define TV_HBLANK_START_MASK		0x0001fff
2513 
2514 #define TV_V_CTL_1		0x6803c
2515 /** XXX */
2516 # define TV_NBR_END_SHIFT		16
2517 # define TV_NBR_END_MASK		0x07ff0000
2518 /** XXX */
2519 # define TV_VI_END_F1_SHIFT		8
2520 # define TV_VI_END_F1_MASK		0x00003f00
2521 /** XXX */
2522 # define TV_VI_END_F2_SHIFT		0
2523 # define TV_VI_END_F2_MASK		0x0000003f
2524 
2525 #define TV_V_CTL_2		0x68040
2526 /** Length of vsync, in half lines */
2527 # define TV_VSYNC_LEN_MASK		0x07ff0000
2528 # define TV_VSYNC_LEN_SHIFT		16
2529 /** Offset of the start of vsync in field 1, measured in one less than the
2530  * number of half lines.
2531  */
2532 # define TV_VSYNC_START_F1_MASK		0x00007f00
2533 # define TV_VSYNC_START_F1_SHIFT	8
2534 /**
2535  * Offset of the start of vsync in field 2, measured in one less than the
2536  * number of half lines.
2537  */
2538 # define TV_VSYNC_START_F2_MASK		0x0000007f
2539 # define TV_VSYNC_START_F2_SHIFT	0
2540 
2541 #define TV_V_CTL_3		0x68044
2542 /** Enables generation of the equalization signal */
2543 # define TV_EQUAL_ENA			(1UL << 31)  /* OSOL_i915 */
2544 /** Length of vsync, in half lines */
2545 # define TV_VEQ_LEN_MASK		0x007f0000
2546 # define TV_VEQ_LEN_SHIFT		16
2547 /** Offset of the start of equalization in field 1, measured in one less than
2548  * the number of half lines.
2549  */
2550 # define TV_VEQ_START_F1_MASK		0x0007f00
2551 # define TV_VEQ_START_F1_SHIFT		8
2552 /**
2553  * Offset of the start of equalization in field 2, measured in one less than
2554  * the number of half lines.
2555  */
2556 # define TV_VEQ_START_F2_MASK		0x000007f
2557 # define TV_VEQ_START_F2_SHIFT		0
2558 
2559 #define TV_V_CTL_4		0x68048
2560 /**
2561  * Offset to start of vertical colorburst, measured in one less than the
2562  * number of lines from vertical start.
2563  */
2564 # define TV_VBURST_START_F1_MASK	0x003f0000
2565 # define TV_VBURST_START_F1_SHIFT	16
2566 /**
2567  * Offset to the end of vertical colorburst, measured in one less than the
2568  * number of lines from the start of NBR.
2569  */
2570 # define TV_VBURST_END_F1_MASK		0x000000ff
2571 # define TV_VBURST_END_F1_SHIFT		0
2572 
2573 #define TV_V_CTL_5		0x6804c
2574 /**
2575  * Offset to start of vertical colorburst, measured in one less than the
2576  * number of lines from vertical start.
2577  */
2578 # define TV_VBURST_START_F2_MASK	0x003f0000
2579 # define TV_VBURST_START_F2_SHIFT	16
2580 /**
2581  * Offset to the end of vertical colorburst, measured in one less than the
2582  * number of lines from the start of NBR.
2583  */
2584 # define TV_VBURST_END_F2_MASK		0x000000ff
2585 # define TV_VBURST_END_F2_SHIFT		0
2586 
2587 #define TV_V_CTL_6		0x68050
2588 /**
2589  * Offset to start of vertical colorburst, measured in one less than the
2590  * number of lines from vertical start.
2591  */
2592 # define TV_VBURST_START_F3_MASK	0x003f0000
2593 # define TV_VBURST_START_F3_SHIFT	16
2594 /**
2595  * Offset to the end of vertical colorburst, measured in one less than the
2596  * number of lines from the start of NBR.
2597  */
2598 # define TV_VBURST_END_F3_MASK		0x000000ff
2599 # define TV_VBURST_END_F3_SHIFT		0
2600 
2601 #define TV_V_CTL_7		0x68054
2602 /**
2603  * Offset to start of vertical colorburst, measured in one less than the
2604  * number of lines from vertical start.
2605  */
2606 # define TV_VBURST_START_F4_MASK	0x003f0000
2607 # define TV_VBURST_START_F4_SHIFT	16
2608 /**
2609  * Offset to the end of vertical colorburst, measured in one less than the
2610  * number of lines from the start of NBR.
2611  */
2612 # define TV_VBURST_END_F4_MASK		0x000000ff
2613 # define TV_VBURST_END_F4_SHIFT		0
2614 
2615 #define TV_SC_CTL_1		0x68060
2616 /** Turns on the first subcarrier phase generation DDA */
2617 # define TV_SC_DDA1_EN			(1UL << 31)  /* OSOL_i915 */
2618 /** Turns on the first subcarrier phase generation DDA */
2619 # define TV_SC_DDA2_EN			(1 << 30)
2620 /** Turns on the first subcarrier phase generation DDA */
2621 # define TV_SC_DDA3_EN			(1 << 29)
2622 /** Sets the subcarrier DDA to reset frequency every other field */
2623 # define TV_SC_RESET_EVERY_2		(0 << 24)
2624 /** Sets the subcarrier DDA to reset frequency every fourth field */
2625 # define TV_SC_RESET_EVERY_4		(1 << 24)
2626 /** Sets the subcarrier DDA to reset frequency every eighth field */
2627 # define TV_SC_RESET_EVERY_8		(2 << 24)
2628 /** Sets the subcarrier DDA to never reset the frequency */
2629 # define TV_SC_RESET_NEVER		(3 << 24)
2630 /** Sets the peak amplitude of the colorburst.*/
2631 # define TV_BURST_LEVEL_MASK		0x00ff0000
2632 # define TV_BURST_LEVEL_SHIFT		16
2633 /** Sets the increment of the first subcarrier phase generation DDA */
2634 # define TV_SCDDA1_INC_MASK		0x00000fff
2635 # define TV_SCDDA1_INC_SHIFT		0
2636 
2637 #define TV_SC_CTL_2		0x68064
2638 /** Sets the rollover for the second subcarrier phase generation DDA */
2639 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
2640 # define TV_SCDDA2_SIZE_SHIFT		16
2641 /** Sets the increent of the second subcarrier phase generation DDA */
2642 # define TV_SCDDA2_INC_MASK		0x00007fff
2643 # define TV_SCDDA2_INC_SHIFT		0
2644 
2645 #define TV_SC_CTL_3		0x68068
2646 /** Sets the rollover for the third subcarrier phase generation DDA */
2647 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
2648 # define TV_SCDDA3_SIZE_SHIFT		16
2649 /** Sets the increent of the third subcarrier phase generation DDA */
2650 # define TV_SCDDA3_INC_MASK		0x00007fff
2651 # define TV_SCDDA3_INC_SHIFT		0
2652 
2653 #define TV_WIN_POS		0x68070
2654 /** X coordinate of the display from the start of horizontal active */
2655 # define TV_XPOS_MASK			0x1fff0000
2656 # define TV_XPOS_SHIFT			16
2657 /** Y coordinate of the display from the start of vertical active (NBR) */
2658 # define TV_YPOS_MASK			0x00000fff
2659 # define TV_YPOS_SHIFT			0
2660 
2661 #define TV_WIN_SIZE		0x68074
2662 /** Horizontal size of the display window, measured in pixels*/
2663 # define TV_XSIZE_MASK			0x1fff0000
2664 # define TV_XSIZE_SHIFT			16
2665 /**
2666  * Vertical size of the display window, measured in pixels.
2667  *
2668  * Must be even for interlaced modes.
2669  */
2670 # define TV_YSIZE_MASK			0x00000fff
2671 # define TV_YSIZE_SHIFT			0
2672 
2673 #define TV_FILTER_CTL_1		0x68080
2674 /**
2675  * Enables automatic scaling calculation.
2676  *
2677  * If set, the rest of the registers are ignored, and the calculated values can
2678  * be read back from the register.
2679  */
2680 # define TV_AUTO_SCALE			(1UL << 31)  /* OSOL_i915 */
2681 /**
2682  * Disables the vertical filter.
2683  *
2684  * This is required on modes more than 1024 pixels wide */
2685 # define TV_V_FILTER_BYPASS		(1 << 29)
2686 /** Enables adaptive vertical filtering */
2687 # define TV_VADAPT			(1 << 28)
2688 # define TV_VADAPT_MODE_MASK		(3 << 26)
2689 /** Selects the least adaptive vertical filtering mode */
2690 # define TV_VADAPT_MODE_LEAST		(0 << 26)
2691 /** Selects the moderately adaptive vertical filtering mode */
2692 # define TV_VADAPT_MODE_MODERATE	(1 << 26)
2693 /** Selects the most adaptive vertical filtering mode */
2694 # define TV_VADAPT_MODE_MOST		(3 << 26)
2695 /**
2696  * Sets the horizontal scaling factor.
2697  *
2698  * This should be the fractional part of the horizontal scaling factor divided
2699  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
2700  *
2701  * (src width - 1) / ((oversample * dest width) - 1)
2702  */
2703 # define TV_HSCALE_FRAC_MASK		0x00003fff
2704 # define TV_HSCALE_FRAC_SHIFT		0
2705 
2706 #define TV_FILTER_CTL_2		0x68084
2707 /**
2708  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2709  *
2710  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2711  */
2712 # define TV_VSCALE_INT_MASK		0x00038000
2713 # define TV_VSCALE_INT_SHIFT		15
2714 /**
2715  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2716  *
2717  * \sa TV_VSCALE_INT_MASK
2718  */
2719 # define TV_VSCALE_FRAC_MASK		0x00007fff
2720 # define TV_VSCALE_FRAC_SHIFT		0
2721 
2722 #define TV_FILTER_CTL_3		0x68088
2723 /**
2724  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2725  *
2726  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2727  *
2728  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2729  */
2730 # define TV_VSCALE_IP_INT_MASK		0x00038000
2731 # define TV_VSCALE_IP_INT_SHIFT		15
2732 /**
2733  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2734  *
2735  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2736  *
2737  * \sa TV_VSCALE_IP_INT_MASK
2738  */
2739 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
2740 # define TV_VSCALE_IP_FRAC_SHIFT		0
2741 
2742 #define TV_CC_CONTROL		0x68090
2743 # define TV_CC_ENABLE			(1UL << 31)  /* OSOL_i915 */
2744 /**
2745  * Specifies which field to send the CC data in.
2746  *
2747  * CC data is usually sent in field 0.
2748  */
2749 # define TV_CC_FID_MASK			(1 << 27)
2750 # define TV_CC_FID_SHIFT		27
2751 /** Sets the horizontal position of the CC data.  Usually 135. */
2752 # define TV_CC_HOFF_MASK		0x03ff0000
2753 # define TV_CC_HOFF_SHIFT		16
2754 /** Sets the vertical position of the CC data.  Usually 21 */
2755 # define TV_CC_LINE_MASK		0x0000003f
2756 # define TV_CC_LINE_SHIFT		0
2757 
2758 #define TV_CC_DATA		0x68094
2759 # define TV_CC_RDY			(1UL << 31)  /* OSOL_i915 */
2760 /** Second word of CC data to be transmitted. */
2761 # define TV_CC_DATA_2_MASK		0x007f0000
2762 # define TV_CC_DATA_2_SHIFT		16
2763 /** First word of CC data to be transmitted. */
2764 # define TV_CC_DATA_1_MASK		0x0000007f
2765 # define TV_CC_DATA_1_SHIFT		0
2766 
2767 #define TV_H_LUMA_0		0x68100
2768 #define TV_H_LUMA_59		0x681ec
2769 #define TV_H_CHROMA_0		0x68200
2770 #define TV_H_CHROMA_59		0x682ec
2771 #define TV_V_LUMA_0		0x68300
2772 #define TV_V_LUMA_42		0x683a8
2773 #define TV_V_CHROMA_0		0x68400
2774 #define TV_V_CHROMA_42		0x684a8
2775 
2776 /* Display Port */
2777 #define DP_A				0x64000 /* eDP */
2778 #define DP_B				0x64100
2779 #define DP_C				0x64200
2780 #define DP_D				0x64300
2781 
2782 #define   DP_PORT_EN			(1UL << 31)  /* OSOL_i915 */
2783 #define   DP_PIPEB_SELECT		(1 << 30)
2784 #define   DP_PIPE_MASK			(1 << 30)
2785 
2786 /* Link training mode - select a suitable mode for each stage */
2787 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2788 #define   DP_LINK_TRAIN_PAT_2		(1 << 28)
2789 #define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
2790 #define   DP_LINK_TRAIN_OFF		(3 << 28)
2791 #define   DP_LINK_TRAIN_MASK		(3 << 28)
2792 #define   DP_LINK_TRAIN_SHIFT		28
2793 
2794 /* CPT Link training mode */
2795 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2796 #define   DP_LINK_TRAIN_PAT_2_CPT	(1 << 8)
2797 #define   DP_LINK_TRAIN_PAT_IDLE_CPT	(2 << 8)
2798 #define   DP_LINK_TRAIN_OFF_CPT		(3 << 8)
2799 #define   DP_LINK_TRAIN_MASK_CPT	(7 << 8)
2800 #define   DP_LINK_TRAIN_SHIFT_CPT	8
2801 
2802 /* Signal voltages. These are mostly controlled by the other end */
2803 #define   DP_VOLTAGE_0_4		(0 << 25)
2804 #define   DP_VOLTAGE_0_6		(1 << 25)
2805 #define   DP_VOLTAGE_0_8		(2 << 25)
2806 #define   DP_VOLTAGE_1_2		(3 << 25)
2807 #define   DP_VOLTAGE_MASK		(7 << 25)
2808 #define   DP_VOLTAGE_SHIFT		25
2809 
2810 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2811  * they want
2812  */
2813 #define   DP_PRE_EMPHASIS_0		(0 << 22)
2814 #define   DP_PRE_EMPHASIS_3_5		(1 << 22)
2815 #define   DP_PRE_EMPHASIS_6		(2 << 22)
2816 #define   DP_PRE_EMPHASIS_9_5		(3 << 22)
2817 #define   DP_PRE_EMPHASIS_MASK		(7 << 22)
2818 #define   DP_PRE_EMPHASIS_SHIFT		22
2819 
2820 /* How many wires to use. I guess 3 was too hard */
2821 #define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)
2822 #define   DP_PORT_WIDTH_MASK		(7 << 19)
2823 
2824 /* Mystic DPCD version 1.1 special mode */
2825 #define   DP_ENHANCED_FRAMING		(1 << 18)
2826 
2827 /* eDP */
2828 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
2829 #define   DP_PLL_FREQ_160MHZ		(1 << 16)
2830 #define   DP_PLL_FREQ_MASK		(3 << 16)
2831 
2832 /** locked once port is enabled */
2833 #define   DP_PORT_REVERSAL		(1 << 15)
2834 
2835 /* eDP */
2836 #define   DP_PLL_ENABLE			(1 << 14)
2837 
2838 /** sends the clock on lane 15 of the PEG for debug */
2839 #define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
2840 
2841 #define   DP_SCRAMBLING_DISABLE		(1 << 12)
2842 #define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
2843 
2844 /** limit RGB values to avoid confusing TVs */
2845 #define   DP_COLOR_RANGE_16_235		(1 << 8)
2846 
2847 /** Turn on the audio link */
2848 #define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
2849 
2850 /** vs and hs sync polarity */
2851 #define   DP_SYNC_VS_HIGH		(1 << 4)
2852 #define   DP_SYNC_HS_HIGH		(1 << 3)
2853 
2854 /** A fantasy */
2855 #define   DP_DETECTED			(1 << 2)
2856 
2857 /** The aux channel provides a way to talk to the
2858  * signal sink for DDC etc. Max packet size supported
2859  * is 20 bytes in each direction, hence the 5 fixed
2860  * data registers
2861  */
2862 #define DPA_AUX_CH_CTL			0x64010
2863 #define DPA_AUX_CH_DATA1		0x64014
2864 #define DPA_AUX_CH_DATA2		0x64018
2865 #define DPA_AUX_CH_DATA3		0x6401c
2866 #define DPA_AUX_CH_DATA4		0x64020
2867 #define DPA_AUX_CH_DATA5		0x64024
2868 
2869 #define DPB_AUX_CH_CTL			0x64110
2870 #define DPB_AUX_CH_DATA1		0x64114
2871 #define DPB_AUX_CH_DATA2		0x64118
2872 #define DPB_AUX_CH_DATA3		0x6411c
2873 #define DPB_AUX_CH_DATA4		0x64120
2874 #define DPB_AUX_CH_DATA5		0x64124
2875 
2876 #define DPC_AUX_CH_CTL			0x64210
2877 #define DPC_AUX_CH_DATA1		0x64214
2878 #define DPC_AUX_CH_DATA2		0x64218
2879 #define DPC_AUX_CH_DATA3		0x6421c
2880 #define DPC_AUX_CH_DATA4		0x64220
2881 #define DPC_AUX_CH_DATA5		0x64224
2882 
2883 #define DPD_AUX_CH_CTL			0x64310
2884 #define DPD_AUX_CH_DATA1		0x64314
2885 #define DPD_AUX_CH_DATA2		0x64318
2886 #define DPD_AUX_CH_DATA3		0x6431c
2887 #define DPD_AUX_CH_DATA4		0x64320
2888 #define DPD_AUX_CH_DATA5		0x64324
2889 
2890 #define   DP_AUX_CH_CTL_SEND_BUSY	    (1UL << 31)  /* OSOL_i915 */
2891 #define   DP_AUX_CH_CTL_DONE		    (1 << 30)
2892 #define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
2893 #define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
2894 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
2895 #define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
2896 #define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
2897 #define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
2898 #define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
2899 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
2900 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
2901 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
2902 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
2903 #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
2904 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
2905 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
2906 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
2907 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
2908 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
2909 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
2910 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
2911 
2912 /*
2913  * Computing GMCH M and N values for the Display Port link
2914  *
2915  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2916  *
2917  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2918  *
2919  * The GMCH value is used internally
2920  *
2921  * bytes_per_pixel is the number of bytes coming out of the plane,
2922  * which is after the LUTs, so we want the bytes for our color format.
2923  * For our current usage, this is always 3, one byte for R, G and B.
2924  */
2925 #define _PIPEA_DATA_M_G4X	0x70050
2926 #define _PIPEB_DATA_M_G4X	0x71050
2927 
2928 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2929 #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
2930 #define  TU_SIZE_SHIFT		25
2931 #define  TU_SIZE_MASK           (0x3f << 25)
2932 
2933 #define  DATA_LINK_M_N_MASK	(0xffffff)
2934 #define  DATA_LINK_N_MAX	(0x800000)
2935 
2936 #define _PIPEA_DATA_N_G4X	0x70054
2937 #define _PIPEB_DATA_N_G4X	0x71054
2938 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
2939 
2940 /*
2941  * Computing Link M and N values for the Display Port link
2942  *
2943  * Link M / N = pixel_clock / ls_clk
2944  *
2945  * (the DP spec calls pixel_clock the 'strm_clk')
2946  *
2947  * The Link value is transmitted in the Main Stream
2948  * Attributes and VB-ID.
2949  */
2950 
2951 #define _PIPEA_LINK_M_G4X	0x70060
2952 #define _PIPEB_LINK_M_G4X	0x71060
2953 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
2954 
2955 #define _PIPEA_LINK_N_G4X	0x70064
2956 #define _PIPEB_LINK_N_G4X	0x71064
2957 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
2958 
2959 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
2960 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
2961 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
2962 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2963 
2964 /* Display & cursor control */
2965 
2966 /* Pipe A */
2967 #define _PIPEADSL		(dev_priv->info->display_mmio_offset + 0x70000)
2968 #define   DSL_LINEMASK_GEN2	0x00000fff
2969 #define   DSL_LINEMASK_GEN3	0x00001fff
2970 #define _PIPEACONF		(dev_priv->info->display_mmio_offset + 0x70008)
2971 #define   PIPECONF_ENABLE	(1UL<<31) /* OSOL_i915 */
2972 #define   PIPECONF_DISABLE	0
2973 #define   PIPECONF_DOUBLE_WIDE	(1<<30)
2974 #define   I965_PIPECONF_ACTIVE	(1<<30)
2975 #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2976 #define   PIPECONF_SINGLE_WIDE	0
2977 #define   PIPECONF_PIPE_UNLOCKED 0
2978 #define   PIPECONF_PIPE_LOCKED	(1<<25)
2979 #define   PIPECONF_PALETTE	0
2980 #define   PIPECONF_GAMMA		(1<<24)
2981 #define   PIPECONF_FORCE_BORDER	(1<<25)
2982 #define   PIPECONF_INTERLACE_MASK	(7 << 21)
2983 #define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)
2984 /* Note that pre-gen3 does not support interlaced display directly. Panel
2985  * fitting must be disabled on pre-ilk for interlaced. */
2986 #define   PIPECONF_PROGRESSIVE			(0 << 21)
2987 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL	(4 << 21) /* gen4 only */
2988 #define   PIPECONF_INTERLACE_W_SYNC_SHIFT	(5 << 21) /* gen4 only */
2989 #define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
2990 #define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
2991 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2992  * means panel fitter required, PF means progressive fetch, DBL means power
2993  * saving pixel doubling. */
2994 #define   PIPECONF_PFIT_PF_INTERLACED_ILK	(1 << 21)
2995 #define   PIPECONF_INTERLACED_ILK		(3 << 21)
2996 #define   PIPECONF_INTERLACED_DBL_ILK		(4 << 21) /* ilk/snb only */
2997 #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK	(5 << 21) /* ilk/snb only */
2998 #define   PIPECONF_INTERLACE_MODE_MASK		(7 << 21)
2999 #define   PIPECONF_CXSR_DOWNCLOCK	(1<<16)
3000 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
3001 #define   PIPECONF_BPC_MASK	(0x7 << 5)
3002 #define   PIPECONF_8BPC		(0<<5)
3003 #define   PIPECONF_10BPC	(1<<5)
3004 #define   PIPECONF_6BPC		(2<<5)
3005 #define   PIPECONF_12BPC	(3<<5)
3006 #define   PIPECONF_DITHER_EN	(1<<4)
3007 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3008 #define   PIPECONF_DITHER_TYPE_SP (0<<2)
3009 #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
3010 #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
3011 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
3012 #define _PIPEASTAT		(dev_priv->info->display_mmio_offset + 0x70024)
3013 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
3014 #define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
3015 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
3016 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
3017 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
3018 #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
3019 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
3020 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
3021 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
3022 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
3023 #define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<22)
3024 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
3025 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
3026 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
3027 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
3028 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
3029 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
3030 #define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
3031 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
3032 #define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
3033 #define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<14)
3034 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
3035 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
3036 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
3037 #define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
3038 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
3039 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
3040 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
3041 #define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
3042 #define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
3043 #define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
3044 #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
3045 #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
3046 #define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
3047 #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
3048 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
3049 
3050 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
3051 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
3052 #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
3053 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
3054 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
3055 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
3056 
3057 #define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)
3058 #define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)
3059 #define   PIPEB_HLINE_INT_EN			(1<<28)
3060 #define   PIPEB_VBLANK_INT_EN			(1<<27)
3061 #define   SPRITED_FLIPDONE_INT_EN		(1<<26)
3062 #define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
3063 #define   PLANEB_FLIPDONE_INT_EN		(1<<24)
3064 #define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)
3065 #define   PIPEA_HLINE_INT_EN			(1<<20)
3066 #define   PIPEA_VBLANK_INT_EN			(1<<19)
3067 #define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
3068 #define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
3069 #define   PLANEA_FLIPDONE_INT_EN		(1<<16)
3070 
3071 #define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3072 #define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
3073 #define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
3074 #define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
3075 #define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
3076 #define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
3077 #define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
3078 #define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
3079 #define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
3080 #define   DPINVGTT_EN_MASK			0xff0000
3081 #define   CURSORB_INVALID_GTT_STATUS		(1<<7)
3082 #define   CURSORA_INVALID_GTT_STATUS		(1<<6)
3083 #define   SPRITED_INVALID_GTT_STATUS		(1<<5)
3084 #define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
3085 #define   PLANEB_INVALID_GTT_STATUS		(1<<3)
3086 #define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
3087 #define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
3088 #define   PLANEA_INVALID_GTT_STATUS		(1<<0)
3089 #define   DPINVGTT_STATUS_MASK			0xff
3090 
3091 #define DSPARB			0x70030
3092 #define   DSPARB_CSTART_MASK	(0x7f << 7)
3093 #define   DSPARB_CSTART_SHIFT	7
3094 #define   DSPARB_BSTART_MASK	(0x7f)
3095 #define   DSPARB_BSTART_SHIFT	0
3096 #define   DSPARB_BEND_SHIFT	9 /* on 855 */
3097 #define   DSPARB_AEND_SHIFT	0
3098 
3099 #define DSPFW1			(dev_priv->info->display_mmio_offset + 0x70034)
3100 #define   DSPFW_SR_SHIFT	23
3101 #define   DSPFW_SR_MASK 	(0x1ffUL<<23)
3102 #define   DSPFW_CURSORB_SHIFT	16
3103 #define   DSPFW_CURSORB_MASK	(0x3f<<16)
3104 #define   DSPFW_PLANEB_SHIFT	8
3105 #define   DSPFW_PLANEB_MASK	(0x7f<<8)
3106 #define   DSPFW_PLANEA_MASK	(0x7f)
3107 #define DSPFW2			(dev_priv->info->display_mmio_offset + 0x70038)
3108 #define   DSPFW_CURSORA_MASK	0x00003f00
3109 #define   DSPFW_CURSORA_SHIFT	8
3110 #define   DSPFW_PLANEC_MASK	(0x7f)
3111 #define DSPFW3			(dev_priv->info->display_mmio_offset + 0x7003c)
3112 #define   DSPFW_HPLL_SR_EN	(1UL<<31)  /* OSOL_i915 */
3113 #define   DSPFW_CURSOR_SR_SHIFT	24
3114 #define   PINEVIEW_SELF_REFRESH_EN	(1<<30)
3115 #define   DSPFW_CURSOR_SR_MASK		(0x3f<<24)
3116 #define   DSPFW_HPLL_CURSOR_SHIFT	16
3117 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
3118 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
3119 #define DSPFW4			(dev_priv->info->display_mmio_offset + 0x70070)
3120 #define DSPFW7			(dev_priv->info->display_mmio_offset + 0x7007c)
3121 
3122 /* drain latency register values*/
3123 #define DRAIN_LATENCY_PRECISION_32	32
3124 #define DRAIN_LATENCY_PRECISION_16	16
3125 #define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)
3126 #define DDL_CURSORA_PRECISION_32	(1UL<<31)
3127 #define DDL_CURSORA_PRECISION_16	(0<<31)
3128 #define DDL_CURSORA_SHIFT		24
3129 #define DDL_PLANEA_PRECISION_32		(1<<7)
3130 #define DDL_PLANEA_PRECISION_16		(0<<7)
3131 #define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)
3132 #define DDL_CURSORB_PRECISION_32	(1UL<<31)
3133 #define DDL_CURSORB_PRECISION_16	(0<<31)
3134 #define DDL_CURSORB_SHIFT		24
3135 #define DDL_PLANEB_PRECISION_32		(1<<7)
3136 #define DDL_PLANEB_PRECISION_16		(0<<7)
3137 
3138 /* FIFO watermark sizes etc */
3139 #define G4X_FIFO_LINE_SIZE	64
3140 #define I915_FIFO_LINE_SIZE	64
3141 #define I830_FIFO_LINE_SIZE	32
3142 
3143 #define VALLEYVIEW_FIFO_SIZE	255
3144 #define G4X_FIFO_SIZE		127
3145 #define I965_FIFO_SIZE		512
3146 #define I945_FIFO_SIZE		127 /* 945 & 965 */
3147 #define I915_FIFO_SIZE		95
3148 #define I855GM_FIFO_SIZE	127 /* In cachelines */
3149 #define I830_FIFO_SIZE		95
3150 
3151 #define VALLEYVIEW_MAX_WM	0xff
3152 #define G4X_MAX_WM		0x3f
3153 #define I915_MAX_WM		0x3f
3154 
3155 #define PINEVIEW_DISPLAY_FIFO	512 /* in 64byte unit */
3156 #define PINEVIEW_FIFO_LINE_SIZE	64
3157 #define PINEVIEW_MAX_WM		0x1ff
3158 #define PINEVIEW_DFT_WM		0x3f
3159 #define PINEVIEW_DFT_HPLLOFF_WM	0
3160 #define PINEVIEW_GUARD_WM		10
3161 #define PINEVIEW_CURSOR_FIFO		64
3162 #define PINEVIEW_CURSOR_MAX_WM	0x3f
3163 #define PINEVIEW_CURSOR_DFT_WM	0
3164 #define PINEVIEW_CURSOR_GUARD_WM	5
3165 
3166 #define VALLEYVIEW_CURSOR_MAX_WM 64
3167 #define I965_CURSOR_FIFO	64
3168 #define I965_CURSOR_MAX_WM	32
3169 #define I965_CURSOR_DFT_WM	8
3170 
3171 /* define the Watermark register on Ironlake */
3172 #define WM0_PIPEA_ILK		0x45100
3173 #define  WM0_PIPE_PLANE_MASK	(0x7f<<16)
3174 #define  WM0_PIPE_PLANE_SHIFT	16
3175 #define  WM0_PIPE_SPRITE_MASK	(0x3f<<8)
3176 #define  WM0_PIPE_SPRITE_SHIFT	8
3177 #define  WM0_PIPE_CURSOR_MASK	(0x1f)
3178 
3179 #define WM0_PIPEB_ILK		0x45104
3180 #define WM0_PIPEC_IVB		0x45200
3181 #define WM1_LP_ILK		0x45108
3182 #define  WM1_LP_SR_EN		(1UL<<31)
3183 #define  WM1_LP_LATENCY_SHIFT	24
3184 #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
3185 #define  WM1_LP_FBC_MASK	(0xf<<20)
3186 #define  WM1_LP_FBC_SHIFT	20
3187 #define  WM1_LP_SR_MASK		(0x1ff<<8)
3188 #define  WM1_LP_SR_SHIFT	8
3189 #define  WM1_LP_CURSOR_MASK	(0x3f)
3190 #define WM2_LP_ILK		0x4510c
3191 #define  WM2_LP_EN		(1UL<<31)
3192 #define WM3_LP_ILK		0x45110
3193 #define  WM3_LP_EN		(1UL<<31)
3194 #define WM1S_LP_ILK		0x45120
3195 #define WM2S_LP_IVB		0x45124
3196 #define WM3S_LP_IVB		0x45128
3197 #define  WM1S_LP_EN		(1UL<<31)
3198 
3199 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3200 	(WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3201 	 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3202 
3203 /* Memory latency timer register */
3204 #define MLTR_ILK		0x11222
3205 #define  MLTR_WM1_SHIFT		0
3206 #define  MLTR_WM2_SHIFT		8
3207 /* the unit of memory self-refresh latency time is 0.5us */
3208 #define  ILK_SRLT_MASK		0x3f
3209 #define ILK_LATENCY(shift)	(I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
3210 #define ILK_READ_WM1_LATENCY()	ILK_LATENCY(MLTR_WM1_SHIFT)
3211 #define ILK_READ_WM2_LATENCY()	ILK_LATENCY(MLTR_WM2_SHIFT)
3212 
3213 /* define the fifo size on Ironlake */
3214 #define ILK_DISPLAY_FIFO	128
3215 #define ILK_DISPLAY_MAXWM	64
3216 #define ILK_DISPLAY_DFTWM	8
3217 #define ILK_CURSOR_FIFO		32
3218 #define ILK_CURSOR_MAXWM	16
3219 #define ILK_CURSOR_DFTWM	8
3220 
3221 #define ILK_DISPLAY_SR_FIFO	512
3222 #define ILK_DISPLAY_MAX_SRWM	0x1ff
3223 #define ILK_DISPLAY_DFT_SRWM	0x3f
3224 #define ILK_CURSOR_SR_FIFO	64
3225 #define ILK_CURSOR_MAX_SRWM	0x3f
3226 #define ILK_CURSOR_DFT_SRWM	8
3227 
3228 #define ILK_FIFO_LINE_SIZE	64
3229 
3230 /* define the WM info on Sandybridge */
3231 #define SNB_DISPLAY_FIFO	128
3232 #define SNB_DISPLAY_MAXWM	0x7f	/* bit 16:22 */
3233 #define SNB_DISPLAY_DFTWM	8
3234 #define SNB_CURSOR_FIFO		32
3235 #define SNB_CURSOR_MAXWM	0x1f	/* bit 4:0 */
3236 #define SNB_CURSOR_DFTWM	8
3237 
3238 #define SNB_DISPLAY_SR_FIFO	512
3239 #define SNB_DISPLAY_MAX_SRWM	0x1ff	/* bit 16:8 */
3240 #define SNB_DISPLAY_DFT_SRWM	0x3f
3241 #define SNB_CURSOR_SR_FIFO	64
3242 #define SNB_CURSOR_MAX_SRWM	0x3f	/* bit 5:0 */
3243 #define SNB_CURSOR_DFT_SRWM	8
3244 
3245 #define SNB_FBC_MAX_SRWM	0xf	/* bit 23:20 */
3246 
3247 #define SNB_FIFO_LINE_SIZE	64
3248 
3249 
3250 /* the address where we get all kinds of latency value */
3251 #define SSKPD			0x5d10
3252 #define SSKPD_WM_MASK		0x3f
3253 #define SSKPD_WM0_SHIFT		0
3254 #define SSKPD_WM1_SHIFT		8
3255 #define SSKPD_WM2_SHIFT		16
3256 #define SSKPD_WM3_SHIFT		24
3257 
3258 #define SNB_LATENCY(shift)	(I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
3259 #define SNB_READ_WM0_LATENCY()		SNB_LATENCY(SSKPD_WM0_SHIFT)
3260 #define SNB_READ_WM1_LATENCY()		SNB_LATENCY(SSKPD_WM1_SHIFT)
3261 #define SNB_READ_WM2_LATENCY()		SNB_LATENCY(SSKPD_WM2_SHIFT)
3262 #define SNB_READ_WM3_LATENCY()		SNB_LATENCY(SSKPD_WM3_SHIFT)
3263 
3264 /*
3265  * The two pipe frame counter registers are not synchronized, so
3266  * reading a stable value is somewhat tricky. The following code
3267  * should work:
3268  *
3269  *  do {
3270  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3271  *             PIPE_FRAME_HIGH_SHIFT;
3272  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3273  *             PIPE_FRAME_LOW_SHIFT);
3274  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3275  *             PIPE_FRAME_HIGH_SHIFT);
3276  *  } while (high1 != high2);
3277  *  frame = (high1 << 8) | low1;
3278  */
3279 #define _PIPEAFRAMEHIGH          (dev_priv->info->display_mmio_offset + 0x70040)
3280 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
3281 #define   PIPE_FRAME_HIGH_SHIFT   0
3282 #define _PIPEAFRAMEPIXEL         (dev_priv->info->display_mmio_offset + 0x70044)
3283 #define   PIPE_FRAME_LOW_MASK     0xff000000
3284 #define   PIPE_FRAME_LOW_SHIFT    24
3285 #define   PIPE_PIXEL_MASK         0x00ffffff
3286 #define   PIPE_PIXEL_SHIFT        0
3287 /* GM45+ just has to be different */
3288 #define _PIPEA_FRMCOUNT_GM45	0x70040
3289 #define _PIPEA_FLIPCOUNT_GM45	0x70044
3290 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3291 
3292 /* Cursor A & B regs */
3293 #define _CURACNTR		(dev_priv->info->display_mmio_offset + 0x70080)
3294 /* Old style CUR*CNTR flags (desktop 8xx) */
3295 #define   CURSOR_ENABLE		0x80000000
3296 #define   CURSOR_GAMMA_ENABLE	0x40000000
3297 #define   CURSOR_STRIDE_MASK	0x30000000
3298 #define   CURSOR_PIPE_CSC_ENABLE (1<<24)
3299 #define   CURSOR_FORMAT_SHIFT	24
3300 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
3301 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
3302 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
3303 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
3304 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
3305 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
3306 /* New style CUR*CNTR flags */
3307 #define   CURSOR_MODE		0x27
3308 #define   CURSOR_MODE_DISABLE   0x00
3309 #define   CURSOR_MODE_64_32B_AX 0x07
3310 #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3311 #define   MCURSOR_PIPE_SELECT	(1 << 28)
3312 #define   MCURSOR_PIPE_A	0x00
3313 #define   MCURSOR_PIPE_B	(1 << 28)
3314 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
3315 #define _CURABASE		(dev_priv->info->display_mmio_offset + 0x70084)
3316 #define _CURAPOS		(dev_priv->info->display_mmio_offset + 0x70088)
3317 #define   CURSOR_POS_MASK       0x007FF
3318 #define   CURSOR_POS_SIGN       0x8000UL  /* OSOL_i915 */
3319 #define   CURSOR_X_SHIFT        0
3320 #define   CURSOR_Y_SHIFT        16
3321 #define CURSIZE			0x700a0
3322 #define _CURBCNTR		(dev_priv->info->display_mmio_offset + 0x700c0)
3323 #define _CURBBASE		(dev_priv->info->display_mmio_offset + 0x700c4)
3324 #define _CURBPOS		(dev_priv->info->display_mmio_offset + 0x700c8)
3325 
3326 #define _CURBCNTR_IVB		0x71080
3327 #define _CURBBASE_IVB		0x71084
3328 #define _CURBPOS_IVB		0x71088
3329 
3330 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3331 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3332 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3333 
3334 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3335 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3336 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3337 
3338 /* Display A control */
3339 #define _DSPACNTR                (dev_priv->info->display_mmio_offset + 0x70180)
3340 #define   DISPLAY_PLANE_ENABLE			(1UL<<31)  /* OSOL_i915 */
3341 #define   DISPLAY_PLANE_DISABLE			0
3342 #define   DISPPLANE_GAMMA_ENABLE		(1<<30)
3343 #define   DISPPLANE_GAMMA_DISABLE		0
3344 #define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
3345 #define   DISPPLANE_YUV422			(0x0<<26)
3346 #define   DISPPLANE_8BPP			(0x2<<26)
3347 #define   DISPPLANE_BGRA555			(0x3<<26)
3348 #define   DISPPLANE_BGRX555			(0x4<<26)
3349 #define   DISPPLANE_BGRX565			(0x5<<26)
3350 #define   DISPPLANE_BGRX888			(0x6<<26)
3351 #define   DISPPLANE_BGRA888			(0x7<<26)
3352 #define   DISPPLANE_RGBX101010			(0x8<<26)
3353 #define   DISPPLANE_RGBA101010			(0x9<<26)
3354 #define   DISPPLANE_BGRX101010			(0xa<<26)
3355 #define   DISPPLANE_RGBX161616			(0xc<<26)
3356 #define   DISPPLANE_RGBX888			(0xe<<26)
3357 #define   DISPPLANE_RGBA888			(0xf<<26)
3358 #define   DISPPLANE_STEREO_ENABLE		(1<<25)
3359 #define   DISPPLANE_STEREO_DISABLE		0
3360 #define   DISPPLANE_PIPE_CSC_ENABLE		(1<<24)
3361 #define   DISPPLANE_SEL_PIPE_SHIFT		24
3362 #define   DISPPLANE_SEL_PIPE_MASK		(3<<DISPPLANE_SEL_PIPE_SHIFT)
3363 #define   DISPPLANE_SEL_PIPE_A			0
3364 #define   DISPPLANE_SEL_PIPE_B			(1<<DISPPLANE_SEL_PIPE_SHIFT)
3365 #define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
3366 #define   DISPPLANE_SRC_KEY_DISABLE		0
3367 #define   DISPPLANE_LINE_DOUBLE			(1<<20)
3368 #define   DISPPLANE_NO_LINE_DOUBLE		0
3369 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
3370 #define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
3371 #define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */
3372 #define   DISPPLANE_TILED			(1<<10)
3373 #define _DSPAADDR		(dev_priv->info->display_mmio_offset + 0x70184)
3374 #define _DSPASTRIDE		(dev_priv->info->display_mmio_offset + 0x70188)
3375 #define _DSPAPOS		(dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3376 #define _DSPASIZE		(dev_priv->info->display_mmio_offset + 0x70190)
3377 #define _DSPASURF		(dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3378 #define _DSPATILEOFF		(dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3379 #define _DSPAOFFSET		(dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3380 #define _DSPASURFLIVE		(dev_priv->info->display_mmio_offset + 0x701AC)
3381 
3382 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3383 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3384 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3385 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3386 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3387 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3388 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3389 #define DSPLINOFF(plane) DSPADDR(plane)
3390 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3391 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3392 
3393 /* Display/Sprite base address macros */
3394 #define DISP_BASEADDR_MASK	(0xfffff000)
3395 #define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)
3396 #define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)
3397 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3398 		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3399 
3400 /* VBIOS flags */
3401 #define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)
3402 #define SWF01			(dev_priv->info->display_mmio_offset + 0x71414)
3403 #define SWF02			(dev_priv->info->display_mmio_offset + 0x71418)
3404 #define SWF03			(dev_priv->info->display_mmio_offset + 0x7141c)
3405 #define SWF04			(dev_priv->info->display_mmio_offset + 0x71420)
3406 #define SWF05			(dev_priv->info->display_mmio_offset + 0x71424)
3407 #define SWF06			(dev_priv->info->display_mmio_offset + 0x71428)
3408 #define SWF10			(dev_priv->info->display_mmio_offset + 0x70410)
3409 #define SWF11			(dev_priv->info->display_mmio_offset + 0x70414)
3410 #define SWF14			(dev_priv->info->display_mmio_offset + 0x71420)
3411 #define SWF30			(dev_priv->info->display_mmio_offset + 0x72414)
3412 #define SWF31			(dev_priv->info->display_mmio_offset + 0x72418)
3413 #define SWF32			(dev_priv->info->display_mmio_offset + 0x7241c)
3414 
3415 /* Pipe B */
3416 #define _PIPEBDSL		(dev_priv->info->display_mmio_offset + 0x71000)
3417 #define _PIPEBCONF		(dev_priv->info->display_mmio_offset + 0x71008)
3418 #define _PIPEBSTAT		(dev_priv->info->display_mmio_offset + 0x71024)
3419 #define _PIPEBFRAMEHIGH		(dev_priv->info->display_mmio_offset + 0x71040)
3420 #define _PIPEBFRAMEPIXEL	(dev_priv->info->display_mmio_offset + 0x71044)
3421 #define _PIPEB_FRMCOUNT_GM45	0x71040
3422 #define _PIPEB_FLIPCOUNT_GM45	0x71044
3423 
3424 
3425 /* Display B control */
3426 #define _DSPBCNTR		(dev_priv->info->display_mmio_offset + 0x71180)
3427 #define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
3428 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
3429 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
3430 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
3431 #define _DSPBADDR		(dev_priv->info->display_mmio_offset + 0x71184)
3432 #define _DSPBSTRIDE		(dev_priv->info->display_mmio_offset + 0x71188)
3433 #define _DSPBPOS		(dev_priv->info->display_mmio_offset + 0x7118C)
3434 #define _DSPBSIZE		(dev_priv->info->display_mmio_offset + 0x71190)
3435 #define _DSPBSURF		(dev_priv->info->display_mmio_offset + 0x7119C)
3436 #define _DSPBTILEOFF		(dev_priv->info->display_mmio_offset + 0x711A4)
3437 #define _DSPBOFFSET		(dev_priv->info->display_mmio_offset + 0x711A4)
3438 #define _DSPBSURFLIVE		(dev_priv->info->display_mmio_offset + 0x711AC)
3439 
3440 /* Sprite A control */
3441 #define _DVSACNTR		0x72180
3442 #define   DVS_ENABLE		(1UL<<31)
3443 #define   DVS_GAMMA_ENABLE	(1<<30)
3444 #define   DVS_PIXFORMAT_MASK	(3<<25)
3445 #define   DVS_FORMAT_YUV422	(0<<25)
3446 #define   DVS_FORMAT_RGBX101010	(1<<25)
3447 #define   DVS_FORMAT_RGBX888	(2<<25)
3448 #define   DVS_FORMAT_RGBX161616	(3<<25)
3449 #define   DVS_PIPE_CSC_ENABLE   (1<<24)
3450 #define   DVS_SOURCE_KEY	(1<<22)
3451 #define   DVS_RGB_ORDER_XBGR	(1<<20)
3452 #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
3453 #define   DVS_YUV_ORDER_YUYV	(0<<16)
3454 #define   DVS_YUV_ORDER_UYVY	(1<<16)
3455 #define   DVS_YUV_ORDER_YVYU	(2<<16)
3456 #define   DVS_YUV_ORDER_VYUY	(3<<16)
3457 #define   DVS_DEST_KEY		(1<<2)
3458 #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
3459 #define   DVS_TILED		(1<<10)
3460 #define _DVSALINOFF		0x72184
3461 #define _DVSASTRIDE		0x72188
3462 #define _DVSAPOS		0x7218c
3463 #define _DVSASIZE		0x72190
3464 #define _DVSAKEYVAL		0x72194
3465 #define _DVSAKEYMSK		0x72198
3466 #define _DVSASURF		0x7219c
3467 #define _DVSAKEYMAXVAL		0x721a0
3468 #define _DVSATILEOFF		0x721a4
3469 #define _DVSASURFLIVE		0x721ac
3470 #define _DVSASCALE		0x72204
3471 #define   DVS_SCALE_ENABLE	(1UL<<31)
3472 #define   DVS_FILTER_MASK	(3<<29)
3473 #define   DVS_FILTER_MEDIUM	(0<<29)
3474 #define   DVS_FILTER_ENHANCING	(1<<29)
3475 #define   DVS_FILTER_SOFTENING	(2<<29)
3476 #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3477 #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3478 #define _DVSAGAMC		0x72300
3479 
3480 #define _DVSBCNTR		0x73180
3481 #define _DVSBLINOFF		0x73184
3482 #define _DVSBSTRIDE		0x73188
3483 #define _DVSBPOS		0x7318c
3484 #define _DVSBSIZE		0x73190
3485 #define _DVSBKEYVAL		0x73194
3486 #define _DVSBKEYMSK		0x73198
3487 #define _DVSBSURF		0x7319c
3488 #define _DVSBKEYMAXVAL		0x731a0
3489 #define _DVSBTILEOFF		0x731a4
3490 #define _DVSBSURFLIVE		0x731ac
3491 #define _DVSBSCALE		0x73204
3492 #define _DVSBGAMC		0x73300
3493 
3494 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3495 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3496 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3497 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3498 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3499 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3500 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3501 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3502 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3503 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3504 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3505 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3506 
3507 #define _SPRA_CTL		0x70280
3508 #define   SPRITE_ENABLE			(1UL<<31)
3509 #define   SPRITE_GAMMA_ENABLE		(1<<30)
3510 #define   SPRITE_PIXFORMAT_MASK		(7<<25)
3511 #define   SPRITE_FORMAT_YUV422		(0<<25)
3512 #define   SPRITE_FORMAT_RGBX101010	(1<<25)
3513 #define   SPRITE_FORMAT_RGBX888		(2<<25)
3514 #define   SPRITE_FORMAT_RGBX161616	(3<<25)
3515 #define   SPRITE_FORMAT_YUV444		(4<<25)
3516 #define   SPRITE_FORMAT_XR_BGR101010	(5<<25) /* Extended range */
3517 #define   SPRITE_PIPE_CSC_ENABLE	(1<<24)
3518 #define   SPRITE_SOURCE_KEY		(1<<22)
3519 #define   SPRITE_RGB_ORDER_RGBX		(1<<20) /* only for 888 and 161616 */
3520 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1<<19)
3521 #define   SPRITE_YUV_CSC_FORMAT_BT709	(1<<18) /* 0 is BT601 */
3522 #define   SPRITE_YUV_BYTE_ORDER_MASK	(3<<16)
3523 #define   SPRITE_YUV_ORDER_YUYV		(0<<16)
3524 #define   SPRITE_YUV_ORDER_UYVY		(1<<16)
3525 #define   SPRITE_YUV_ORDER_YVYU		(2<<16)
3526 #define   SPRITE_YUV_ORDER_VYUY		(3<<16)
3527 #define   SPRITE_TRICKLE_FEED_DISABLE	(1<<14)
3528 #define   SPRITE_INT_GAMMA_ENABLE	(1<<13)
3529 #define   SPRITE_TILED			(1<<10)
3530 #define   SPRITE_DEST_KEY		(1<<2)
3531 #define _SPRA_LINOFF		0x70284
3532 #define _SPRA_STRIDE		0x70288
3533 #define _SPRA_POS		0x7028c
3534 #define _SPRA_SIZE		0x70290
3535 #define _SPRA_KEYVAL		0x70294
3536 #define _SPRA_KEYMSK		0x70298
3537 #define _SPRA_SURF		0x7029c
3538 #define _SPRA_KEYMAX		0x702a0
3539 #define _SPRA_TILEOFF		0x702a4
3540 #define _SPRA_OFFSET		0x702a4
3541 #define _SPRA_SURFLIVE		0x702ac
3542 #define _SPRA_SCALE		0x70304
3543 #define   SPRITE_SCALE_ENABLE	(1UL<<31)
3544 #define   SPRITE_FILTER_MASK	(3<<29)
3545 #define   SPRITE_FILTER_MEDIUM	(0<<29)
3546 #define   SPRITE_FILTER_ENHANCING	(1<<29)
3547 #define   SPRITE_FILTER_SOFTENING	(2<<29)
3548 #define   SPRITE_VERTICAL_OFFSET_HALF	(1<<28) /* must be enabled below */
3549 #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1<<27)
3550 #define _SPRA_GAMC		0x70400
3551 
3552 #define _SPRB_CTL		0x71280
3553 #define _SPRB_LINOFF		0x71284
3554 #define _SPRB_STRIDE		0x71288
3555 #define _SPRB_POS		0x7128c
3556 #define _SPRB_SIZE		0x71290
3557 #define _SPRB_KEYVAL		0x71294
3558 #define _SPRB_KEYMSK		0x71298
3559 #define _SPRB_SURF		0x7129c
3560 #define _SPRB_KEYMAX		0x712a0
3561 #define _SPRB_TILEOFF		0x712a4
3562 #define _SPRB_OFFSET		0x712a4
3563 #define _SPRB_SURFLIVE		0x712ac
3564 #define _SPRB_SCALE		0x71304
3565 #define _SPRB_GAMC		0x71400
3566 
3567 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3568 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3569 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3570 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3571 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3572 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3573 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3574 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3575 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3576 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3577 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3578 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3579 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3580 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3581 
3582 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
3583 #define   SP_ENABLE			(1UL<<31)
3584 #define   SP_GEAMMA_ENABLE		(1<<30)
3585 #define   SP_PIXFORMAT_MASK		(0xf<<26)
3586 #define   SP_FORMAT_YUV422		(0<<26)
3587 #define   SP_FORMAT_BGR565		(5<<26)
3588 #define   SP_FORMAT_BGRX8888		(6<<26)
3589 #define   SP_FORMAT_BGRA8888		(7<<26)
3590 #define   SP_FORMAT_RGBX1010102		(8<<26)
3591 #define   SP_FORMAT_RGBA1010102		(9<<26)
3592 #define   SP_FORMAT_RGBX8888		(0xe<<26)
3593 #define   SP_FORMAT_RGBA8888		(0xf<<26)
3594 #define   SP_SOURCE_KEY			(1<<22)
3595 #define   SP_YUV_BYTE_ORDER_MASK	(3<<16)
3596 #define   SP_YUV_ORDER_YUYV		(0<<16)
3597 #define   SP_YUV_ORDER_UYVY		(1<<16)
3598 #define   SP_YUV_ORDER_YVYU		(2<<16)
3599 #define   SP_YUV_ORDER_VYUY		(3<<16)
3600 #define   SP_TILED			(1<<10)
3601 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
3602 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
3603 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
3604 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
3605 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
3606 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
3607 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
3608 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
3609 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
3610 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
3611 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
3612 
3613 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
3614 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
3615 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
3616 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
3617 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
3618 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
3619 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
3620 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
3621 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
3622 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
3623 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
3624 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
3625 
3626 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3627 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3628 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3629 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3630 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3631 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3632 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3633 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3634 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3635 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3636 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3637 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3638 
3639 /* VBIOS regs */
3640 #define VGACNTRL		0x71400
3641 # define VGA_DISP_DISABLE			(1UL << 31)  /* OSOL_i915 */
3642 # define VGA_2X_MODE				(1 << 30)
3643 # define VGA_PIPE_B_SELECT			(1 << 29)
3644 
3645 #define VLV_VGACNTRL		(VLV_DISPLAY_BASE + 0x71400)
3646 
3647 /* Ironlake */
3648 
3649 #define CPU_VGACNTRL	0x41000
3650 
3651 #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
3652 #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
3653 #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
3654 #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
3655 #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
3656 #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
3657 #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
3658 #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
3659 #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
3660 
3661 /* refresh rate hardware control */
3662 #define RR_HW_CTL       0x45300
3663 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
3664 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
3665 
3666 #define FDI_PLL_BIOS_0  0x46000
3667 #define  FDI_PLL_FB_CLOCK_MASK  0xff
3668 #define FDI_PLL_BIOS_1  0x46004
3669 #define FDI_PLL_BIOS_2  0x46008
3670 #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
3671 #define DISPLAY_PORT_PLL_BIOS_1         0x46010
3672 #define DISPLAY_PORT_PLL_BIOS_2         0x46014
3673 
3674 #define PCH_3DCGDIS0		0x46020
3675 # define MARIUNIT_CLOCK_GATE_DISABLE		(1 << 18)
3676 # define SVSMUNIT_CLOCK_GATE_DISABLE		(1 << 1)
3677 
3678 #define PCH_3DCGDIS1		0x46024
3679 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
3680 
3681 #define FDI_PLL_FREQ_CTL        0x46030
3682 #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
3683 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
3684 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
3685 
3686 
3687 #define _PIPEA_DATA_M1           (dev_priv->info->display_mmio_offset + 0x60030)
3688 #define  PIPE_DATA_M1_OFFSET    0
3689 #define _PIPEA_DATA_N1           (dev_priv->info->display_mmio_offset + 0x60034)
3690 #define  PIPE_DATA_N1_OFFSET    0
3691 
3692 #define _PIPEA_DATA_M2           (dev_priv->info->display_mmio_offset + 0x60038)
3693 #define  PIPE_DATA_M2_OFFSET    0
3694 #define _PIPEA_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6003c)
3695 #define  PIPE_DATA_N2_OFFSET    0
3696 
3697 #define _PIPEA_LINK_M1           (dev_priv->info->display_mmio_offset + 0x60040)
3698 #define  PIPE_LINK_M1_OFFSET    0
3699 #define _PIPEA_LINK_N1           (dev_priv->info->display_mmio_offset + 0x60044)
3700 #define  PIPE_LINK_N1_OFFSET    0
3701 
3702 #define _PIPEA_LINK_M2           (dev_priv->info->display_mmio_offset + 0x60048)
3703 #define  PIPE_LINK_M2_OFFSET    0
3704 #define _PIPEA_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6004c)
3705 #define  PIPE_LINK_N2_OFFSET    0
3706 
3707 /* PIPEB timing regs are same start from 0x61000 */
3708 
3709 #define _PIPEB_DATA_M1           (dev_priv->info->display_mmio_offset + 0x61030)
3710 #define _PIPEB_DATA_N1           (dev_priv->info->display_mmio_offset + 0x61034)
3711 
3712 #define _PIPEB_DATA_M2           (dev_priv->info->display_mmio_offset + 0x61038)
3713 #define _PIPEB_DATA_N2           (dev_priv->info->display_mmio_offset + 0x6103c)
3714 
3715 #define _PIPEB_LINK_M1           (dev_priv->info->display_mmio_offset + 0x61040)
3716 #define _PIPEB_LINK_N1           (dev_priv->info->display_mmio_offset + 0x61044)
3717 
3718 #define _PIPEB_LINK_M2           (dev_priv->info->display_mmio_offset + 0x61048)
3719 #define _PIPEB_LINK_N2           (dev_priv->info->display_mmio_offset + 0x6104c)
3720 
3721 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3722 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3723 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3724 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3725 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3726 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3727 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3728 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3729 
3730 /* CPU panel fitter */
3731 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3732 #define _PFA_CTL_1               0x68080
3733 #define _PFB_CTL_1               0x68880
3734 #define  PF_ENABLE              (1UL<<31)  /* OSOL_i915 */
3735 #define  PF_PIPE_SEL_MASK_IVB	(3<<29)
3736 #define  PF_PIPE_SEL_IVB(pipe)	((pipe)<<29)
3737 #define  PF_FILTER_MASK		(3<<23)
3738 #define  PF_FILTER_PROGRAMMED	(0<<23)
3739 #define  PF_FILTER_MED_3x3	(1<<23)
3740 #define  PF_FILTER_EDGE_ENHANCE	(2<<23)
3741 #define  PF_FILTER_EDGE_SOFTEN	(3<<23)
3742 #define _PFA_WIN_SZ		0x68074
3743 #define _PFB_WIN_SZ		0x68874
3744 #define _PFA_WIN_POS		0x68070
3745 #define _PFB_WIN_POS		0x68870
3746 #define _PFA_VSCALE		0x68084
3747 #define _PFB_VSCALE		0x68884
3748 #define _PFA_HSCALE		0x68090
3749 #define _PFB_HSCALE		0x68890
3750 
3751 #define PF_CTL(pipe)		_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3752 #define PF_WIN_SZ(pipe)		_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3753 #define PF_WIN_POS(pipe)	_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3754 #define PF_VSCALE(pipe)		_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3755 #define PF_HSCALE(pipe)		_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3756 
3757 /* legacy palette */
3758 #define _LGC_PALETTE_A           0x4a000
3759 #define _LGC_PALETTE_B           0x4a800
3760 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3761 
3762 #define _GAMMA_MODE_A		0x4a480
3763 #define _GAMMA_MODE_B		0x4ac80
3764 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3765 #define GAMMA_MODE_MODE_MASK	(3 << 0)
3766 #define GAMMA_MODE_MODE_8BIT	(0 << 0)
3767 #define GAMMA_MODE_MODE_10BIT	(1 << 0)
3768 #define GAMMA_MODE_MODE_12BIT	(2 << 0)
3769 #define GAMMA_MODE_MODE_SPLIT	(3 << 0)
3770 
3771 /* interrupts */
3772 #define DE_MASTER_IRQ_CONTROL   (1UL << 31)  /* OSOL_i915 */
3773 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
3774 #define DE_SPRITEA_FLIP_DONE    (1 << 28)
3775 #define DE_PLANEB_FLIP_DONE     (1 << 27)
3776 #define DE_PLANEA_FLIP_DONE     (1 << 26)
3777 #define DE_PCU_EVENT            (1 << 25)
3778 #define DE_GTT_FAULT            (1 << 24)
3779 #define DE_POISON               (1 << 23)
3780 #define DE_PERFORM_COUNTER      (1 << 22)
3781 #define DE_PCH_EVENT            (1 << 21)
3782 #define DE_AUX_CHANNEL_A        (1 << 20)
3783 #define DE_DP_A_HOTPLUG         (1 << 19)
3784 #define DE_GSE                  (1 << 18)
3785 #define DE_PIPEB_VBLANK         (1 << 15)
3786 #define DE_PIPEB_EVEN_FIELD     (1 << 14)
3787 #define DE_PIPEB_ODD_FIELD      (1 << 13)
3788 #define DE_PIPEB_LINE_COMPARE   (1 << 12)
3789 #define DE_PIPEB_VSYNC          (1 << 11)
3790 #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
3791 #define DE_PIPEA_VBLANK         (1 << 7)
3792 #define DE_PIPEA_EVEN_FIELD     (1 << 6)
3793 #define DE_PIPEA_ODD_FIELD      (1 << 5)
3794 #define DE_PIPEA_LINE_COMPARE   (1 << 4)
3795 #define DE_PIPEA_VSYNC          (1 << 3)
3796 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
3797 
3798 /* More Ivybridge lolz */
3799 #define DE_ERR_INT_IVB			(1<<30)
3800 #define DE_GSE_IVB			(1<<29)
3801 #define DE_PCH_EVENT_IVB		(1<<28)
3802 #define DE_DP_A_HOTPLUG_IVB		(1<<27)
3803 #define DE_AUX_CHANNEL_A_IVB		(1<<26)
3804 #define DE_SPRITEC_FLIP_DONE_IVB	(1<<14)
3805 #define DE_PLANEC_FLIP_DONE_IVB		(1<<13)
3806 #define DE_PIPEC_VBLANK_IVB		(1<<10)
3807 #define DE_SPRITEB_FLIP_DONE_IVB	(1<<9)
3808 #define DE_PLANEB_FLIP_DONE_IVB		(1<<8)
3809 #define DE_PIPEB_VBLANK_IVB		(1<<5)
3810 #define DE_SPRITEA_FLIP_DONE_IVB	(1<<4)
3811 #define DE_PLANEA_FLIP_DONE_IVB		(1<<3)
3812 #define DE_PIPEA_VBLANK_IVB		(1<<0)
3813 
3814 #define VLV_MASTER_IER			0x4400c /* Gunit master IER */
3815 #define   MASTER_INTERRUPT_ENABLE	(1UL<<31)
3816 
3817 #define DEISR   0x44000
3818 #define DEIMR   0x44004
3819 #define DEIIR   0x44008
3820 #define DEIER   0x4400c
3821 
3822 #define GTISR   0x44010
3823 #define GTIMR   0x44014
3824 #define GTIIR   0x44018
3825 #define GTIER   0x4401c
3826 
3827 #define ILK_DISPLAY_CHICKEN2	0x42004
3828 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3829 #define  ILK_ELPIN_409_SELECT	(1 << 25)
3830 #define  ILK_DPARB_GATE	(1<<22)
3831 #define  ILK_VSDPFD_FULL	(1<<21)
3832 #define ILK_DISPLAY_CHICKEN_FUSES	0x42014
3833 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1UL<<31)
3834 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1<<30)
3835 #define  ILK_DISPLAY_DEBUG_DISABLE	(1<<29)
3836 #define  ILK_HDCP_DISABLE		(1<<25)
3837 #define  ILK_eDP_A_DISABLE		(1<<24)
3838 #define  ILK_DESKTOP			(1<<23)
3839 
3840 #define ILK_DSPCLK_GATE_D			0x42020
3841 #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	(1 << 28)
3842 #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	(1 << 9)
3843 #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	(1 << 8)
3844 #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	(1 << 7)
3845 #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	(1 << 5)
3846 
3847 #define	IVB_CHICKEN3	0x4200c
3848 #define	CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)
3849 #define	CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
3850 
3851 #define CHICKEN_PAR1_1		0x42080
3852 #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
3853 
3854 #define DISP_ARB_CTL	0x45000
3855 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
3856 #define  DISP_FBC_WM_DIS		(1<<15)
3857 #define GEN7_MSG_CTL	0x45010
3858 #define  WAIT_FOR_PCH_RESET_ACK		(1<<1)
3859 #define  WAIT_FOR_PCH_FLR_ACK		(1<<0)
3860 
3861 /* GEN7 chicken */
3862 #define GEN7_COMMON_SLICE_CHICKEN1		0x7010
3863 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
3864 
3865 #define GEN7_L3CNTLREG1				0xB01C
3866 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
3867 #define  GEN7_L3AGDIS				(1<<19)
3868 
3869 #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
3870 #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
3871 
3872 #define GEN7_L3SQCREG4				0xb034
3873 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
3874 
3875 /* WaCatErrorRejectionIssue */
3876 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
3877 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
3878 
3879 #define HSW_FUSE_STRAP		0x42014
3880 #define  HSW_CDCLK_LIMIT	(1 << 24)
3881 
3882 /* PCH */
3883 
3884 /* south display engine interrupt */
3885 #define SDE_AUDIO_POWER_D	(1 << 27)
3886 #define SDE_AUDIO_POWER_C	(1 << 26)
3887 #define SDE_AUDIO_POWER_B	(1 << 25)
3888 #define SDE_AUDIO_POWER_SHIFT	(25)
3889 #define SDE_AUDIO_POWER_MASK	(7 << SDE_AUDIO_POWER_SHIFT)
3890 #define SDE_GMBUS		(1 << 24)
3891 #define SDE_AUDIO_HDCP_TRANSB	(1 << 23)
3892 #define SDE_AUDIO_HDCP_TRANSA	(1 << 22)
3893 #define SDE_AUDIO_HDCP_MASK	(3 << 22)
3894 #define SDE_AUDIO_TRANSB	(1 << 21)
3895 #define SDE_AUDIO_TRANSA	(1 << 20)
3896 #define SDE_AUDIO_TRANS_MASK	(3 << 20)
3897 #define SDE_POISON		(1 << 19)
3898 /* 18 reserved */
3899 #define SDE_FDI_RXB		(1 << 17)
3900 #define SDE_FDI_RXA		(1 << 16)
3901 #define SDE_FDI_MASK		(3 << 16)
3902 #define SDE_AUXD		(1 << 15)
3903 #define SDE_AUXC		(1 << 14)
3904 #define SDE_AUXB		(1 << 13)
3905 #define SDE_AUX_MASK		(7 << 13)
3906 /* 12 reserved */
3907 #define SDE_CRT_HOTPLUG         (1 << 11)
3908 #define SDE_PORTD_HOTPLUG       (1 << 10)
3909 #define SDE_PORTC_HOTPLUG       (1 << 9)
3910 #define SDE_PORTB_HOTPLUG       (1 << 8)
3911 #define SDE_SDVOB_HOTPLUG       (1 << 6)
3912 #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
3913 				 SDE_SDVOB_HOTPLUG |	\
3914 				 SDE_PORTB_HOTPLUG |	\
3915 				 SDE_PORTC_HOTPLUG |	\
3916 				 SDE_PORTD_HOTPLUG)
3917 #define SDE_TRANSB_CRC_DONE	(1 << 5)
3918 #define SDE_TRANSB_CRC_ERR	(1 << 4)
3919 #define SDE_TRANSB_FIFO_UNDER	(1 << 3)
3920 #define SDE_TRANSA_CRC_DONE	(1 << 2)
3921 #define SDE_TRANSA_CRC_ERR	(1 << 1)
3922 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
3923 #define SDE_TRANS_MASK		(0x3f)
3924 /* CPT */
3925 /* south display engine interrupt: CPT/PPT */
3926 #define SDE_AUDIO_POWER_D_CPT	(1UL << 31)
3927 #define SDE_AUDIO_POWER_C_CPT	(1 << 30)
3928 #define SDE_AUDIO_POWER_B_CPT	(1 << 29)
3929 #define SDE_AUDIO_POWER_SHIFT_CPT   29
3930 #define SDE_AUDIO_POWER_MASK_CPT    (7UL << 29)
3931 #define SDE_AUXD_CPT		(1 << 27)
3932 #define SDE_AUXC_CPT		(1 << 26)
3933 #define SDE_AUXB_CPT		(1 << 25)
3934 #define SDE_AUX_MASK_CPT	(7 << 25)
3935 #define SDE_PORTD_HOTPLUG_CPT	(1 << 23)
3936 #define SDE_PORTC_HOTPLUG_CPT	(1 << 22)
3937 #define SDE_PORTB_HOTPLUG_CPT	(1 << 21)
3938 #define SDE_CRT_HOTPLUG_CPT	(1 << 19)
3939 #define SDE_SDVOB_HOTPLUG_CPT	(1 << 18)
3940 #define SDE_HOTPLUG_MASK_CPT	(SDE_CRT_HOTPLUG_CPT |		\
3941 				 SDE_SDVOB_HOTPLUG_CPT |	\
3942 				 SDE_PORTD_HOTPLUG_CPT |	\
3943 				 SDE_PORTC_HOTPLUG_CPT |	\
3944 				 SDE_PORTB_HOTPLUG_CPT)
3945 #define SDE_GMBUS_CPT		(1 << 17)
3946 #define SDE_ERROR_CPT		(1 << 16)
3947 #define SDE_AUDIO_CP_REQ_C_CPT	(1 << 10)
3948 #define SDE_AUDIO_CP_CHG_C_CPT	(1 << 9)
3949 #define SDE_FDI_RXC_CPT		(1 << 8)
3950 #define SDE_AUDIO_CP_REQ_B_CPT	(1 << 6)
3951 #define SDE_AUDIO_CP_CHG_B_CPT	(1 << 5)
3952 #define SDE_FDI_RXB_CPT		(1 << 4)
3953 #define SDE_AUDIO_CP_REQ_A_CPT	(1 << 2)
3954 #define SDE_AUDIO_CP_CHG_A_CPT	(1 << 1)
3955 #define SDE_FDI_RXA_CPT		(1 << 0)
3956 #define SDE_AUDIO_CP_REQ_CPT	(SDE_AUDIO_CP_REQ_C_CPT | \
3957 				 SDE_AUDIO_CP_REQ_B_CPT | \
3958 				 SDE_AUDIO_CP_REQ_A_CPT)
3959 #define SDE_AUDIO_CP_CHG_CPT	(SDE_AUDIO_CP_CHG_C_CPT | \
3960 				 SDE_AUDIO_CP_CHG_B_CPT | \
3961 				 SDE_AUDIO_CP_CHG_A_CPT)
3962 #define SDE_FDI_MASK_CPT	(SDE_FDI_RXC_CPT | \
3963 				 SDE_FDI_RXB_CPT | \
3964 				 SDE_FDI_RXA_CPT)
3965 
3966 #define SDEISR  0xc4000
3967 #define SDEIMR  0xc4004
3968 #define SDEIIR  0xc4008
3969 #define SDEIER  0xc400c
3970 
3971 #define SERR_INT			0xc4040
3972 #define  SERR_INT_POISON		(1UL<<31)
3973 #define  SERR_INT_TRANS_C_FIFO_UNDERRUN	(1<<6)
3974 #define  SERR_INT_TRANS_B_FIFO_UNDERRUN	(1<<3)
3975 #define  SERR_INT_TRANS_A_FIFO_UNDERRUN	(1<<0)
3976 
3977 /* digital port hotplug */
3978 #define PCH_PORT_HOTPLUG        0xc4030
3979 #define PORTD_HOTPLUG_ENABLE            (1 << 20)
3980 #define PORTD_PULSE_DURATION_2ms        (0)
3981 #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
3982 #define PORTD_PULSE_DURATION_6ms        (2 << 18)
3983 #define PORTD_PULSE_DURATION_100ms      (3 << 18)
3984 #define PORTD_PULSE_DURATION_MASK	(3 << 18)
3985 #define PORTD_HOTPLUG_STATUS_MASK	(0x3 << 16)
3986 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
3987 #define  PORTD_HOTPLUG_SHORT_DETECT	(1 << 16)
3988 #define  PORTD_HOTPLUG_LONG_DETECT	(2 << 16)
3989 #define PORTC_HOTPLUG_ENABLE            (1 << 12)
3990 #define PORTC_PULSE_DURATION_2ms        (0)
3991 #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
3992 #define PORTC_PULSE_DURATION_6ms        (2 << 10)
3993 #define PORTC_PULSE_DURATION_100ms      (3 << 10)
3994 #define PORTC_PULSE_DURATION_MASK	(3 << 10)
3995 #define PORTC_HOTPLUG_STATUS_MASK	(0x3 << 8)
3996 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
3997 #define  PORTC_HOTPLUG_SHORT_DETECT	(1 << 8)
3998 #define  PORTC_HOTPLUG_LONG_DETECT	(2 << 8)
3999 #define PORTB_HOTPLUG_ENABLE            (1 << 4)
4000 #define PORTB_PULSE_DURATION_2ms        (0)
4001 #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
4002 #define PORTB_PULSE_DURATION_6ms        (2 << 2)
4003 #define PORTB_PULSE_DURATION_100ms      (3 << 2)
4004 #define PORTB_PULSE_DURATION_MASK	(3 << 2)
4005 #define PORTB_HOTPLUG_STATUS_MASK	(0x3 << 0)
4006 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
4007 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
4008 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
4009 
4010 #define PCH_GPIOA               0xc5010
4011 #define PCH_GPIOB               0xc5014
4012 #define PCH_GPIOC               0xc5018
4013 #define PCH_GPIOD               0xc501c
4014 #define PCH_GPIOE               0xc5020
4015 #define PCH_GPIOF               0xc5024
4016 
4017 #define PCH_GMBUS0		0xc5100
4018 #define PCH_GMBUS1		0xc5104
4019 #define PCH_GMBUS2		0xc5108
4020 #define PCH_GMBUS3		0xc510c
4021 #define PCH_GMBUS4		0xc5110
4022 #define PCH_GMBUS5		0xc5120
4023 
4024 #define _PCH_DPLL_A              0xc6014
4025 #define _PCH_DPLL_B              0xc6018
4026 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4027 
4028 #define _PCH_FPA0                0xc6040
4029 #define  FP_CB_TUNE		(0x3<<22)
4030 #define _PCH_FPA1                0xc6044
4031 #define _PCH_FPB0                0xc6048
4032 #define _PCH_FPB1                0xc604c
4033 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4034 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
4035 
4036 #define PCH_DPLL_TEST           0xc606c
4037 
4038 #define PCH_DREF_CONTROL        0xC6200
4039 #define  DREF_CONTROL_MASK      0x7fc3
4040 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
4041 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
4042 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
4043 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
4044 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
4045 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
4046 #define  DREF_SSC_SOURCE_MASK			(3<<11)
4047 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
4048 #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
4049 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
4050 #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
4051 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
4052 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
4053 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
4054 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
4055 #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
4056 #define  DREF_SSC1_DISABLE                      (0<<1)
4057 #define  DREF_SSC1_ENABLE                       (1<<1)
4058 #define  DREF_SSC4_DISABLE                      (0)
4059 #define  DREF_SSC4_ENABLE                       (1)
4060 
4061 #define PCH_RAWCLK_FREQ         0xc6204
4062 #define  FDL_TP1_TIMER_SHIFT    12
4063 #define  FDL_TP1_TIMER_MASK     (3<<12)
4064 #define  FDL_TP2_TIMER_SHIFT    10
4065 #define  FDL_TP2_TIMER_MASK     (3<<10)
4066 #define  RAWCLK_FREQ_MASK       0x3ff
4067 
4068 #define PCH_DPLL_TMR_CFG        0xc6208
4069 
4070 #define PCH_SSC4_PARMS          0xc6210
4071 #define PCH_SSC4_AUX_PARMS      0xc6214
4072 
4073 #define PCH_DPLL_SEL		0xc7000
4074 #define	 TRANS_DPLLB_SEL(pipe)		(1 << (pipe * 4))
4075 #define	 TRANS_DPLLA_SEL(pipe)		0
4076 #define  TRANS_DPLL_ENABLE(pipe)	(1 << (pipe * 4 + 3))
4077 
4078 /* transcoder */
4079 
4080 #define _PCH_TRANS_HTOTAL_A		0xe0000
4081 #define  TRANS_HTOTAL_SHIFT		16
4082 #define  TRANS_HACTIVE_SHIFT		0
4083 #define _PCH_TRANS_HBLANK_A		0xe0004
4084 #define  TRANS_HBLANK_END_SHIFT		16
4085 #define  TRANS_HBLANK_START_SHIFT	0
4086 #define _PCH_TRANS_HSYNC_A		0xe0008
4087 #define  TRANS_HSYNC_END_SHIFT		16
4088 #define  TRANS_HSYNC_START_SHIFT	0
4089 #define _PCH_TRANS_VTOTAL_A		0xe000c
4090 #define  TRANS_VTOTAL_SHIFT		16
4091 #define  TRANS_VACTIVE_SHIFT		0
4092 #define _PCH_TRANS_VBLANK_A		0xe0010
4093 #define  TRANS_VBLANK_END_SHIFT		16
4094 #define  TRANS_VBLANK_START_SHIFT	0
4095 #define _PCH_TRANS_VSYNC_A		0xe0014
4096 #define  TRANS_VSYNC_END_SHIFT	 	16
4097 #define  TRANS_VSYNC_START_SHIFT	0
4098 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
4099 
4100 #define _PCH_TRANSA_DATA_M1	0xe0030
4101 #define _PCH_TRANSA_DATA_N1	0xe0034
4102 #define _PCH_TRANSA_DATA_M2	0xe0038
4103 #define _PCH_TRANSA_DATA_N2	0xe003c
4104 #define _PCH_TRANSA_LINK_M1	0xe0040
4105 #define _PCH_TRANSA_LINK_N1	0xe0044
4106 #define _PCH_TRANSA_LINK_M2	0xe0048
4107 #define _PCH_TRANSA_LINK_N2	0xe004c
4108 
4109 /* Per-transcoder DIP controls */
4110 
4111 #define	_VIDEO_DIP_CTL_A	0xe0200
4112 #define	_VIDEO_DIP_DATA_A	0xe0208
4113 #define	_VIDEO_DIP_GCP_A	0xe0210
4114 
4115 #define	_VIDEO_DIP_CTL_B	0xe1200
4116 #define	_VIDEO_DIP_DATA_B	0xe1208
4117 #define	_VIDEO_DIP_GCP_B	0xe1210
4118 
4119 #define	TVIDEO_DIP_CTL(pipe)	_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4120 #define	TVIDEO_DIP_DATA(pipe)	_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4121 #define	TVIDEO_DIP_GCP(pipe)	_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4122 
4123 #define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
4124 #define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
4125 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
4126 
4127 #define VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
4128 #define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
4129 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
4130 
4131 #define VLV_TVIDEO_DIP_CTL(pipe) \
4132 	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4133 #define VLV_TVIDEO_DIP_DATA(pipe) \
4134 	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4135 #define VLV_TVIDEO_DIP_GCP(pipe) \
4136 	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4137 
4138 /* Haswell DIP controls */
4139 #define HSW_VIDEO_DIP_CTL_A		0x60200
4140 #define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
4141 #define HSW_VIDEO_DIP_VS_DATA_A		0x60260
4142 #define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
4143 #define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
4144 #define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
4145 #define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
4146 #define HSW_VIDEO_DIP_VS_ECC_A		0x60280
4147 #define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
4148 #define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
4149 #define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
4150 #define HSW_VIDEO_DIP_GCP_A		0x60210
4151 
4152 #define HSW_VIDEO_DIP_CTL_B		0x61200
4153 #define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
4154 #define HSW_VIDEO_DIP_VS_DATA_B		0x61260
4155 #define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
4156 #define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
4157 #define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
4158 #define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
4159 #define HSW_VIDEO_DIP_VS_ECC_B		0x61280
4160 #define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
4161 #define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
4162 #define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
4163 #define HSW_VIDEO_DIP_GCP_B		0x61210
4164 
4165 #define HSW_TVIDEO_DIP_CTL(trans) \
4166 	 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
4167 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4168 	 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
4169 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4170 	 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
4171 #define HSW_TVIDEO_DIP_GCP(trans) \
4172 	_TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
4173 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4174 	 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
4175 
4176 #define _PCH_TRANS_HTOTAL_B          0xe1000
4177 #define _PCH_TRANS_HBLANK_B          0xe1004
4178 #define _PCH_TRANS_HSYNC_B           0xe1008
4179 #define _PCH_TRANS_VTOTAL_B          0xe100c
4180 #define _PCH_TRANS_VBLANK_B          0xe1010
4181 #define _PCH_TRANS_VSYNC_B           0xe1014
4182 #define _PCH_TRANS_VSYNCSHIFT_B	 0xe1028
4183 
4184 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4185 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4186 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4187 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4188 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4189 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4190 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4191 					 _PCH_TRANS_VSYNCSHIFT_B)
4192 
4193 #define _PCH_TRANSB_DATA_M1	0xe1030
4194 #define _PCH_TRANSB_DATA_N1	0xe1034
4195 #define _PCH_TRANSB_DATA_M2	0xe1038
4196 #define _PCH_TRANSB_DATA_N2	0xe103c
4197 #define _PCH_TRANSB_LINK_M1	0xe1040
4198 #define _PCH_TRANSB_LINK_N1	0xe1044
4199 #define _PCH_TRANSB_LINK_M2	0xe1048
4200 #define _PCH_TRANSB_LINK_N2	0xe104c
4201 
4202 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4203 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4204 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4205 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4206 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4207 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4208 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4209 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4210 
4211 #define _PCH_TRANSACONF              0xf0008
4212 #define _PCH_TRANSBCONF              0xf1008
4213 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4214 #define LPT_TRANSCONF		_PCH_TRANSACONF /* lpt has only one transcoder */
4215 #define  TRANS_DISABLE          (0<<31)
4216 #define  TRANS_ENABLE           (1UL<<31)  /* OSOL_i915 */
4217 #define  TRANS_STATE_MASK       (1<<30)
4218 #define  TRANS_STATE_DISABLE    (0<<30)
4219 #define  TRANS_STATE_ENABLE     (1<<30)
4220 #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
4221 #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
4222 #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
4223 #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
4224 #define  TRANS_INTERLACE_MASK   (7<<21)
4225 #define  TRANS_PROGRESSIVE      (0<<21)
4226 #define  TRANS_INTERLACED       (3<<21)
4227 #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
4228 #define  TRANS_8BPC             (0<<5)
4229 #define  TRANS_10BPC            (1<<5)
4230 #define  TRANS_6BPC             (2<<5)
4231 #define  TRANS_12BPC            (3<<5)
4232 
4233 #define _TRANSA_CHICKEN1	 0xf0060
4234 #define _TRANSB_CHICKEN1	 0xf1060
4235 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4236 #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	(1<<4)
4237 #define	_TRANSA_CHICKEN2	0xf0064
4238 #define	_TRANSB_CHICKEN2	0xf1064
4239 #define	TRANS_CHICKEN2(pipe)	_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
4240 #define  TRANS_CHICKEN2_TIMING_OVERRIDE			(1UL<<31)
4241 #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED		(1<<29)
4242 #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK		(3<<27)
4243 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	(1<<26)
4244 #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	(1<<25)
4245 
4246 #define SOUTH_CHICKEN1		0xc2000
4247 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
4248 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
4249 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4250 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4251 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
4252 #define SOUTH_CHICKEN2		0xc2004
4253 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
4254 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
4255 #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
4256 
4257 #define _FDI_RXA_CHICKEN         0xc200c
4258 #define _FDI_RXB_CHICKEN         0xc2010
4259 #define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)
4260 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1<<0)
4261 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4262 
4263 #define SOUTH_DSPCLK_GATE_D	0xc2020
4264 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4265 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
4266 
4267 /* CPU: FDI_TX */
4268 #define _FDI_TXA_CTL             0x60100
4269 #define _FDI_TXB_CTL             0x61100
4270 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4271 #define  FDI_TX_DISABLE         (0<<31)
4272 #define  FDI_TX_ENABLE          (1UL<<31)  /* OSOL_i915 */
4273 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
4274 #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
4275 #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
4276 #define  FDI_LINK_TRAIN_NONE            (3<<28)
4277 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
4278 #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
4279 #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
4280 #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
4281 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4282 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4283 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
4284 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
4285 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4286    SNB has different settings. */
4287 /* SNB A-stepping */
4288 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4289 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4290 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4291 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4292 /* SNB B-stepping */
4293 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0<<22)
4294 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a<<22)
4295 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39<<22)
4296 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38<<22)
4297 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f<<22)
4298 #define  FDI_DP_PORT_WIDTH_SHIFT		19
4299 #define  FDI_DP_PORT_WIDTH_MASK			(7 << FDI_DP_PORT_WIDTH_SHIFT)
4300 #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
4301 #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
4302 /* Ironlake: hardwired to 1 */
4303 #define  FDI_TX_PLL_ENABLE              (1<<14)
4304 
4305 /* Ivybridge has different bits for lolz */
4306 #define	FDI_LINK_TRAIN_PATTERN_1_IVB	(0<<8)
4307 #define	FDI_LINK_TRAIN_PATTERN_2_IVB	(1<<8)
4308 #define	FDI_LINK_TRAIN_PATTERN_IDLE_IVB	(2<<8)
4309 #define	FDI_LINK_TRAIN_NONE_IVB	(3<<8)
4310 
4311 /* both Tx and Rx */
4312 #define	FDI_COMPOSITE_SYNC	(1<<11)
4313 #define	FDI_LINK_TRAIN_AUTO	(1<<10)
4314 #define	FDI_SCRAMBLING_ENABLE	(0<<7)
4315 #define	FDI_SCRAMBLING_DISABLE	(1<<7)
4316 
4317 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4318 #define _FDI_RXA_CTL             0xf000c
4319 #define _FDI_RXB_CTL             0xf100c
4320 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4321 #define  FDI_RX_ENABLE          (1UL<<31)
4322 /* train, dp width same as FDI_TX */
4323 #define	FDI_FS_ERRC_ENABLE	(1<<27)
4324 #define	FDI_FE_ERRC_ENABLE	(1<<26)
4325 #define  FDI_RX_POLARITY_REVERSED_LPT	(1<<16)
4326 #define  FDI_8BPC                       (0<<16)
4327 #define  FDI_10BPC                      (1<<16)
4328 #define  FDI_6BPC                       (2<<16)
4329 #define  FDI_12BPC                      (3<<16)
4330 #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
4331 #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
4332 #define  FDI_RX_PLL_ENABLE              (1<<13)
4333 #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
4334 #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
4335 #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
4336 #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
4337 #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
4338 #define  FDI_PCDCLK	                (1<<4)
4339 /* CPT */
4340 #define  FDI_AUTO_TRAINING			(1<<10)
4341 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0<<8)
4342 #define  FDI_LINK_TRAIN_PATTERN_2_CPT		(1<<8)
4343 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
4344 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
4345 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
4346 
4347 #define _FDI_RXA_MISC			0xf0010
4348 #define _FDI_RXB_MISC			0xf1010
4349 #define  FDI_RX_PWRDN_LANE1_MASK	(3<<26)
4350 #define  FDI_RX_PWRDN_LANE1_VAL(x)	((x)<<26)
4351 #define  FDI_RX_PWRDN_LANE0_MASK	(3<<24)
4352 #define  FDI_RX_PWRDN_LANE0_VAL(x)	((x)<<24)
4353 #define  FDI_RX_TP1_TO_TP2_48		(2<<20)
4354 #define  FDI_RX_TP1_TO_TP2_64		(3<<20)
4355 #define  FDI_RX_FDI_DELAY_90		(0x90<<0)
4356 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4357 
4358 #define _FDI_RXA_TUSIZE1         0xf0030
4359 #define _FDI_RXA_TUSIZE2         0xf0038
4360 #define _FDI_RXB_TUSIZE1         0xf1030
4361 #define _FDI_RXB_TUSIZE2         0xf1038
4362 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4363 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4364 
4365 /* FDI_RX interrupt register format */
4366 #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
4367 #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
4368 #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
4369 #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
4370 #define FDI_RX_FS_CODE_ERR              (1<<6)
4371 #define FDI_RX_FE_CODE_ERR              (1<<5)
4372 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
4373 #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
4374 #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
4375 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
4376 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
4377 
4378 #define _FDI_RXA_IIR             0xf0014
4379 #define _FDI_RXA_IMR             0xf0018
4380 #define _FDI_RXB_IIR             0xf1014
4381 #define _FDI_RXB_IMR             0xf1018
4382 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4383 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4384 
4385 #define FDI_PLL_CTL_1           0xfe000
4386 #define FDI_PLL_CTL_2           0xfe004
4387 
4388 #define PCH_LVDS	0xe1180
4389 #define  LVDS_DETECTED	(1 << 1)
4390 
4391 /* vlv has 2 sets of panel control regs. */
4392 #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
4393 #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
4394 #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
4395 #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
4396 #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
4397 
4398 #define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
4399 #define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
4400 #define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
4401 #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
4402 #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
4403 
4404 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4405 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4406 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
4407 		_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4408 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4409 		_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4410 #define VLV_PIPE_PP_DIVISOR(pipe) \
4411 		_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4412 
4413 #define PCH_PP_STATUS		0xc7200
4414 #define PCH_PP_CONTROL		0xc7204
4415 #define  PANEL_UNLOCK_REGS	(0xabcdUL << 16)
4416 #define  PANEL_UNLOCK_MASK	(0xffffUL << 16)
4417 #define  EDP_FORCE_VDD		(1 << 3)
4418 #define  EDP_BLC_ENABLE		(1 << 2)
4419 #define  PANEL_POWER_RESET	(1 << 1)
4420 #define  PANEL_POWER_OFF	(0 << 0)
4421 #define  PANEL_POWER_ON		(1 << 0)
4422 #define PCH_PP_ON_DELAYS	0xc7208
4423 #define  PANEL_PORT_SELECT_MASK	(3UL << 30)
4424 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
4425 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
4426 #define  EDP_PANEL		(1 << 30)
4427 #define  PANEL_PORT_SELECT_DPC	(2UL << 30)
4428 #define  PANEL_PORT_SELECT_DPD	(3UL << 30)
4429 #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
4430 #define  PANEL_POWER_UP_DELAY_SHIFT	16
4431 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
4432 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
4433 
4434 #define PCH_PP_OFF_DELAYS	0xc720c
4435 #define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
4436 #define  PANEL_POWER_PORT_LVDS		(0 << 30)
4437 #define  PANEL_POWER_PORT_DP_A		(1 << 30)
4438 #define  PANEL_POWER_PORT_DP_C		(2 << 30)
4439 #define  PANEL_POWER_PORT_DP_D		(3UL << 30)
4440 #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
4441 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
4442 #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
4443 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
4444 
4445 #define PCH_PP_DIVISOR		0xc7210
4446 #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
4447 #define  PP_REFERENCE_DIVIDER_SHIFT	8
4448 #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
4449 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
4450 
4451 #define PCH_DP_B		0xe4100
4452 #define PCH_DPB_AUX_CH_CTL	0xe4110
4453 #define PCH_DPB_AUX_CH_DATA1	0xe4114
4454 #define PCH_DPB_AUX_CH_DATA2	0xe4118
4455 #define PCH_DPB_AUX_CH_DATA3	0xe411c
4456 #define PCH_DPB_AUX_CH_DATA4	0xe4120
4457 #define PCH_DPB_AUX_CH_DATA5	0xe4124
4458 
4459 #define PCH_DP_C		0xe4200
4460 #define PCH_DPC_AUX_CH_CTL	0xe4210
4461 #define PCH_DPC_AUX_CH_DATA1	0xe4214
4462 #define PCH_DPC_AUX_CH_DATA2	0xe4218
4463 #define PCH_DPC_AUX_CH_DATA3	0xe421c
4464 #define PCH_DPC_AUX_CH_DATA4	0xe4220
4465 #define PCH_DPC_AUX_CH_DATA5	0xe4224
4466 
4467 #define PCH_DP_D		0xe4300
4468 #define PCH_DPD_AUX_CH_CTL	0xe4310
4469 #define PCH_DPD_AUX_CH_DATA1	0xe4314
4470 #define PCH_DPD_AUX_CH_DATA2	0xe4318
4471 #define PCH_DPD_AUX_CH_DATA3	0xe431c
4472 #define PCH_DPD_AUX_CH_DATA4	0xe4320
4473 #define PCH_DPD_AUX_CH_DATA5	0xe4324
4474 
4475 /* CPT */
4476 #define  PORT_TRANS_A_SEL_CPT	0
4477 #define  PORT_TRANS_B_SEL_CPT	(1<<29)
4478 #define  PORT_TRANS_C_SEL_CPT	(2<<29)
4479 #define  PORT_TRANS_SEL_MASK	(3<<29)
4480 #define  PORT_TRANS_SEL_CPT(pipe)	((pipe) << 29)
4481 #define  PORT_TO_PIPE(val)	(((val) & (1<<30)) >> 30)
4482 #define  PORT_TO_PIPE_CPT(val)	(((val) & PORT_TRANS_SEL_MASK) >> 29)
4483 
4484 #define TRANS_DP_CTL_A		0xe0300
4485 #define TRANS_DP_CTL_B		0xe1300
4486 #define TRANS_DP_CTL_C		0xe2300
4487 #define TRANS_DP_CTL(pipe)	_PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4488 #define  TRANS_DP_OUTPUT_ENABLE	(1UL<<31)
4489 #define  TRANS_DP_PORT_SEL_B	(0<<29)
4490 #define  TRANS_DP_PORT_SEL_C	(1<<29)
4491 #define  TRANS_DP_PORT_SEL_D	(2<<29)
4492 #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
4493 #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
4494 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
4495 #define  TRANS_DP_ENH_FRAMING	(1UL<<18)
4496 #define  TRANS_DP_8BPC		(0<<9)
4497 #define  TRANS_DP_10BPC		(1<<9)
4498 #define  TRANS_DP_6BPC		(2<<9)
4499 #define  TRANS_DP_12BPC		(3<<9)
4500 #define  TRANS_DP_BPC_MASK	(3<<9)
4501 #define  TRANS_DP_VSYNC_ACTIVE_HIGH	(1<<4)
4502 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
4503 #define  TRANS_DP_HSYNC_ACTIVE_HIGH	(1<<3)
4504 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
4505 #define  TRANS_DP_SYNC_MASK	(3<<3)
4506 
4507 /* SNB eDP training params */
4508 /* SNB A-stepping */
4509 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38<<22)
4510 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02<<22)
4511 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01<<22)
4512 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0<<22)
4513 /* SNB B-stepping */
4514 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0<<22)
4515 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1<<22)
4516 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a<<22)
4517 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39<<22)
4518 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38<<22)
4519 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f<<22)
4520 
4521 /* IVB */
4522 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 <<22)
4523 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a <<22)
4524 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f <<22)
4525 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 <<22)
4526 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 <<22)
4527 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 <<22)
4528 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e <<22)
4529 
4530 /* legacy values */
4531 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 <<22)
4532 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 <<22)
4533 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 <<22)
4534 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 <<22)
4535 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 <<22)
4536 
4537 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
4538 
4539 #define  FORCEWAKE				0xA18C
4540 #define  FORCEWAKE_VLV				0x1300b0
4541 #define  FORCEWAKE_ACK_VLV			0x1300b4
4542 #define  FORCEWAKE_MEDIA_VLV			0x1300b8
4543 #define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
4544 #define  FORCEWAKE_ACK_HSW			0x130044
4545 #define  FORCEWAKE_ACK				0x130090
4546 #define  VLV_GTLC_WAKE_CTRL			0x130090
4547 #define  VLV_GTLC_PW_STATUS			0x130094
4548 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
4549 #define  FORCEWAKE_KERNEL			0x1
4550 #define  FORCEWAKE_USER				0x2
4551 #define  FORCEWAKE_MT_ACK			0x130040
4552 #define  ECOBUS					0xa180
4553 #define    FORCEWAKE_MT_ENABLE			(1<<5)
4554 
4555 #define  GTFIFODBG				0x120000
4556 #define    GT_FIFO_CPU_ERROR_MASK		7
4557 #define    GT_FIFO_OVFERR			(1<<2)
4558 #define    GT_FIFO_IAWRERR			(1<<1)
4559 #define    GT_FIFO_IARDERR			(1<<0)
4560 
4561 #define  GT_FIFO_FREE_ENTRIES			0x120008
4562 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
4563 
4564 #define GEN6_UCGCTL1				0x9400
4565 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)
4566 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
4567 
4568 #define GEN6_UCGCTL2				0x9404
4569 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
4570 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
4571 #define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
4572 #define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE	(1 << 12)
4573 #define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
4574 
4575 #define GEN7_UCGCTL4				0x940c
4576 #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE	(1<<25)
4577 
4578 #define GEN6_RPNSWREQ				0xA008
4579 #define   GEN6_TURBO_DISABLE			(1UL<<31)
4580 #define   GEN6_FREQUENCY(x)			((x)<<25)
4581 #define   HSW_FREQUENCY(x)			((x)<<24)
4582 #define   GEN6_OFFSET(x)			((x)<<19)
4583 #define   GEN6_AGGRESSIVE_TURBO			(0<<15)
4584 #define GEN6_RC_VIDEO_FREQ			0xA00C
4585 #define GEN6_RC_CONTROL				0xA090
4586 #define   GEN6_RC_CTL_RC6pp_ENABLE		(1<<16)
4587 #define   GEN6_RC_CTL_RC6p_ENABLE		(1<<17)
4588 #define   GEN6_RC_CTL_RC6_ENABLE		(1<<18)
4589 #define   GEN6_RC_CTL_RC1e_ENABLE		(1<<20)
4590 #define   GEN6_RC_CTL_RC7_ENABLE		(1<<22)
4591 #define   GEN7_RC_CTL_TO_MODE			(1<<28)
4592 #define   GEN6_RC_CTL_EI_MODE(x)		((x)<<27)
4593 #define   GEN6_RC_CTL_HW_ENABLE			(1UL<<31)
4594 #define GEN6_RP_DOWN_TIMEOUT			0xA010
4595 #define GEN6_RP_INTERRUPT_LIMITS		0xA014
4596 #define GEN6_RPSTAT1				0xA01C
4597 #define   GEN6_CAGF_SHIFT			8
4598 #define   HSW_CAGF_SHIFT			7
4599 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
4600 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
4601 #define GEN6_RP_CONTROL				0xA024
4602 #define   GEN6_RP_MEDIA_TURBO			(1<<11)
4603 #define   GEN6_RP_MEDIA_MODE_MASK		(3<<9)
4604 #define   GEN6_RP_MEDIA_HW_TURBO_MODE		(3<<9)
4605 #define   GEN6_RP_MEDIA_HW_NORMAL_MODE		(2<<9)
4606 #define   GEN6_RP_MEDIA_HW_MODE			(1<<9)
4607 #define   GEN6_RP_MEDIA_SW_MODE			(0<<9)
4608 #define   GEN6_RP_MEDIA_IS_GFX			(1<<8)
4609 #define   GEN6_RP_ENABLE			(1<<7)
4610 #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
4611 #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
4612 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
4613 #define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
4614 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
4615 #define GEN6_RP_UP_THRESHOLD			0xA02C
4616 #define GEN6_RP_DOWN_THRESHOLD			0xA030
4617 #define GEN6_RP_CUR_UP_EI			0xA050
4618 #define   GEN6_CURICONT_MASK			0xffffff
4619 #define GEN6_RP_CUR_UP				0xA054
4620 #define   GEN6_CURBSYTAVG_MASK			0xffffff
4621 #define GEN6_RP_PREV_UP				0xA058
4622 #define GEN6_RP_CUR_DOWN_EI			0xA05C
4623 #define   GEN6_CURIAVG_MASK			0xffffff
4624 #define GEN6_RP_CUR_DOWN			0xA060
4625 #define GEN6_RP_PREV_DOWN			0xA064
4626 #define GEN6_RP_UP_EI				0xA068
4627 #define GEN6_RP_DOWN_EI				0xA06C
4628 #define GEN6_RP_IDLE_HYSTERSIS			0xA070
4629 #define GEN6_RC_STATE				0xA094
4630 #define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
4631 #define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
4632 #define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
4633 #define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
4634 #define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
4635 #define GEN6_RC_SLEEP				0xA0B0
4636 #define GEN6_RC1e_THRESHOLD			0xA0B4
4637 #define GEN6_RC6_THRESHOLD			0xA0B8
4638 #define GEN6_RC6p_THRESHOLD			0xA0BC
4639 #define GEN6_RC6pp_THRESHOLD			0xA0C0
4640 #define GEN6_PMINTRMSK				0xA168
4641 
4642 #define GEN6_PMISR				0x44020
4643 #define GEN6_PMIMR				0x44024 /* rps_lock */
4644 #define GEN6_PMIIR				0x44028
4645 #define GEN6_PMIER				0x4402C
4646 #define  GEN6_PM_MBOX_EVENT			(1<<25)
4647 #define  GEN6_PM_THERMAL_EVENT			(1<<24)
4648 #define  GEN6_PM_RP_DOWN_TIMEOUT		(1<<6)
4649 #define  GEN6_PM_RP_UP_THRESHOLD		(1<<5)
4650 #define  GEN6_PM_RP_DOWN_THRESHOLD		(1<<4)
4651 #define  GEN6_PM_RP_UP_EI_EXPIRED		(1<<2)
4652 #define  GEN6_PM_RP_DOWN_EI_EXPIRED		(1<<1)
4653 #define  GEN6_PM_RPS_EVENTS			(GEN6_PM_RP_UP_THRESHOLD | \
4654 						 GEN6_PM_RP_DOWN_THRESHOLD | \
4655 						 GEN6_PM_RP_DOWN_TIMEOUT)
4656 
4657 #define GEN6_GT_GFX_RC6_LOCKED			0x138104
4658 #define GEN6_GT_GFX_RC6				0x138108
4659 #define GEN6_GT_GFX_RC6p			0x13810C
4660 #define GEN6_GT_GFX_RC6pp			0x138110
4661 
4662 #define GEN6_PCODE_MAILBOX			0x138124
4663 #define   GEN6_PCODE_READY			(1UL<<31)
4664 #define   GEN6_READ_OC_PARAMS			0xc
4665 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
4666 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
4667 #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
4668 #define	  GEN6_PCODE_READ_RC6VIDS		0x5
4669 #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
4670 #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
4671 #define GEN6_PCODE_DATA				0x138128
4672 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
4673 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
4674 
4675 #define GEN6_GT_CORE_STATUS		0x138060
4676 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
4677 #define   GEN6_RCn_MASK			7
4678 #define   GEN6_RC0			0
4679 #define   GEN6_RC3			2
4680 #define   GEN6_RC6			3
4681 #define   GEN6_RC7			4
4682 
4683 #define GEN7_MISCCPCTL			(0x9424)
4684 #define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
4685 
4686 /* IVYBRIDGE DPF */
4687 #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
4688 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
4689 #define   GEN7_PARITY_ERROR_VALID	(1<<13)
4690 #define   GEN7_L3CDERRST1_BANK_MASK	(3<<11)
4691 #define   GEN7_L3CDERRST1_SUBBANK_MASK	(7<<8)
4692 #define GEN7_PARITY_ERROR_ROW(reg) \
4693 		((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4694 #define GEN7_PARITY_ERROR_BANK(reg) \
4695 		((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4696 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4697 		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4698 #define   GEN7_L3CDERRST1_ENABLE	(1<<7)
4699 
4700 #define GEN7_L3LOG_BASE			0xB070
4701 #define GEN7_L3LOG_SIZE			0x80
4702 
4703 #define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
4704 #define GEN7_HALF_SLICE_CHICKEN1_GT2	0xf100
4705 #define   GEN7_MAX_PS_THREAD_DEP		(8UL<<12)
4706 #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
4707 
4708 #define GEN7_ROW_CHICKEN2		0xe4f4
4709 #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
4710 #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
4711 
4712 #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
4713 #define INTEL_AUDIO_DEVCL		0x808629FB
4714 #define INTEL_AUDIO_DEVBLC		0x80862801
4715 #define INTEL_AUDIO_DEVCTG		0x80862802
4716 
4717 #define G4X_AUD_CNTL_ST			0x620B4
4718 #define G4X_ELDV_DEVCL_DEVBLC		(1 << 13)
4719 #define G4X_ELDV_DEVCTG			(1 << 14)
4720 #define G4X_ELD_ADDR			(0xf << 5)
4721 #define G4X_ELD_ACK			(1 << 4)
4722 #define G4X_HDMIW_HDMIEDID		0x6210C
4723 
4724 #define IBX_HDMIW_HDMIEDID_A		0xE2050
4725 #define IBX_HDMIW_HDMIEDID_B		0xE2150
4726 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4727 					IBX_HDMIW_HDMIEDID_A, \
4728 					IBX_HDMIW_HDMIEDID_B)
4729 #define IBX_AUD_CNTL_ST_A		0xE20B4
4730 #define IBX_AUD_CNTL_ST_B		0xE21B4
4731 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4732 					IBX_AUD_CNTL_ST_A, \
4733 					IBX_AUD_CNTL_ST_B)
4734 #define IBX_ELD_BUFFER_SIZE		(0x1f << 10)
4735 #define IBX_ELD_ADDRESS			(0x1f << 5)
4736 #define IBX_ELD_ACK			(1 << 4)
4737 #define IBX_AUD_CNTL_ST2		0xE20C0
4738 #define IBX_ELD_VALIDB			(1 << 0)
4739 #define IBX_CP_READYB			(1 << 1)
4740 
4741 #define CPT_HDMIW_HDMIEDID_A		0xE5050
4742 #define CPT_HDMIW_HDMIEDID_B		0xE5150
4743 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4744 					CPT_HDMIW_HDMIEDID_A, \
4745 					CPT_HDMIW_HDMIEDID_B)
4746 #define CPT_AUD_CNTL_ST_A		0xE50B4
4747 #define CPT_AUD_CNTL_ST_B		0xE51B4
4748 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4749 					CPT_AUD_CNTL_ST_A, \
4750 					CPT_AUD_CNTL_ST_B)
4751 #define CPT_AUD_CNTRL_ST2		0xE50C0
4752 
4753 /* These are the 4 32-bit write offset registers for each stream
4754  * output buffer.  It determines the offset from the
4755  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4756  */
4757 #define GEN7_SO_WRITE_OFFSET(n)		(0x5280 + (n) * 4)
4758 
4759 #define IBX_AUD_CONFIG_A			0xe2000
4760 #define IBX_AUD_CONFIG_B			0xe2100
4761 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4762 					IBX_AUD_CONFIG_A, \
4763 					IBX_AUD_CONFIG_B)
4764 #define CPT_AUD_CONFIG_A			0xe5000
4765 #define CPT_AUD_CONFIG_B			0xe5100
4766 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4767 					CPT_AUD_CONFIG_A, \
4768 					CPT_AUD_CONFIG_B)
4769 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
4770 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
4771 #define   AUD_CONFIG_UPPER_N_SHIFT		20
4772 #define   AUD_CONFIG_UPPER_N_VALUE		(0xff << 20)
4773 #define   AUD_CONFIG_LOWER_N_SHIFT		4
4774 #define   AUD_CONFIG_LOWER_N_VALUE		(0xfff << 4)
4775 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16
4776 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
4777 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
4778 
4779 /* HSW Audio */
4780 #define   HSW_AUD_CONFIG_A		0x65000 /* Audio Configuration Transcoder A */
4781 #define   HSW_AUD_CONFIG_B		0x65100 /* Audio Configuration Transcoder B */
4782 #define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
4783 					HSW_AUD_CONFIG_A, \
4784 					HSW_AUD_CONFIG_B)
4785 
4786 #define   HSW_AUD_MISC_CTRL_A		0x65010 /* Audio Misc Control Convert 1 */
4787 #define   HSW_AUD_MISC_CTRL_B		0x65110 /* Audio Misc Control Convert 2 */
4788 #define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4789 					HSW_AUD_MISC_CTRL_A, \
4790 					HSW_AUD_MISC_CTRL_B)
4791 
4792 #define   HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4793 #define   HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4794 #define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4795 					HSW_AUD_DIP_ELD_CTRL_ST_A, \
4796 					HSW_AUD_DIP_ELD_CTRL_ST_B)
4797 
4798 /* Audio Digital Converter */
4799 #define   HSW_AUD_DIG_CNVT_1		0x65080 /* Audio Converter 1 */
4800 #define   HSW_AUD_DIG_CNVT_2		0x65180 /* Audio Converter 1 */
4801 #define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4802 					HSW_AUD_DIG_CNVT_1, \
4803 					HSW_AUD_DIG_CNVT_2)
4804 #define   DIP_PORT_SEL_MASK		0x3
4805 
4806 #define   HSW_AUD_EDID_DATA_A		0x65050
4807 #define   HSW_AUD_EDID_DATA_B		0x65150
4808 #define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4809 					HSW_AUD_EDID_DATA_A, \
4810 					HSW_AUD_EDID_DATA_B)
4811 
4812 #define   HSW_AUD_PIPE_CONV_CFG		0x6507c /* Audio pipe and converter configs */
4813 #define   HSW_AUD_PIN_ELD_CP_VLD	0x650c0 /* Audio ELD and CP Ready Status */
4814 #define   AUDIO_INACTIVE_C		(1<<11)
4815 #define   AUDIO_INACTIVE_B		(1<<7)
4816 #define   AUDIO_INACTIVE_A		(1<<3)
4817 #define   AUDIO_OUTPUT_ENABLE_A		(1<<2)
4818 #define   AUDIO_OUTPUT_ENABLE_B		(1<<6)
4819 #define   AUDIO_OUTPUT_ENABLE_C		(1<<10)
4820 #define   AUDIO_ELD_VALID_A		(1<<0)
4821 #define   AUDIO_ELD_VALID_B		(1<<4)
4822 #define   AUDIO_ELD_VALID_C		(1<<8)
4823 #define   AUDIO_CP_READY_A		(1<<1)
4824 #define   AUDIO_CP_READY_B		(1<<5)
4825 #define   AUDIO_CP_READY_C		(1<<9)
4826 
4827 /* HSW Power Wells */
4828 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
4829 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
4830 #define HSW_PWR_WELL_KVMR			0x45408 /* CTL3 */
4831 #define HSW_PWR_WELL_DEBUG			0x4540C /* CTL4 */
4832 #define   HSW_PWR_WELL_ENABLE			(1UL<<31)
4833 #define   HSW_PWR_WELL_STATE			(1<<30)
4834 #define HSW_PWR_WELL_CTL5			0x45410
4835 #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1UL<<31)
4836 #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
4837 #define   HSW_PWR_WELL_FORCE_ON			(1<<19)
4838 #define HSW_PWR_WELL_CTL6			0x45414
4839 
4840 /* Per-pipe DDI Function Control */
4841 #define TRANS_DDI_FUNC_CTL_A		0x60400
4842 #define TRANS_DDI_FUNC_CTL_B		0x61400
4843 #define TRANS_DDI_FUNC_CTL_C		0x62400
4844 #define TRANS_DDI_FUNC_CTL_EDP		0x6F400
4845 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4846 						   TRANS_DDI_FUNC_CTL_B)
4847 #define  TRANS_DDI_FUNC_ENABLE		(1UL<<31)
4848 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4849 #define  TRANS_DDI_PORT_MASK		(7<<28)
4850 #define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
4851 #define  TRANS_DDI_PORT_NONE		(0<<28)
4852 #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
4853 #define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
4854 #define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)
4855 #define  TRANS_DDI_MODE_SELECT_DP_SST	(2<<24)
4856 #define  TRANS_DDI_MODE_SELECT_DP_MST	(3<<24)
4857 #define  TRANS_DDI_MODE_SELECT_FDI	(4<<24)
4858 #define  TRANS_DDI_BPC_MASK		(7<<20)
4859 #define  TRANS_DDI_BPC_8		(0<<20)
4860 #define  TRANS_DDI_BPC_10		(1<<20)
4861 #define  TRANS_DDI_BPC_6		(2<<20)
4862 #define  TRANS_DDI_BPC_12		(3<<20)
4863 #define  TRANS_DDI_PVSYNC		(1<<17)
4864 #define  TRANS_DDI_PHSYNC		(1<<16)
4865 #define  TRANS_DDI_EDP_INPUT_MASK	(7<<12)
4866 #define  TRANS_DDI_EDP_INPUT_A_ON	(0<<12)
4867 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4<<12)
4868 #define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)
4869 #define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)
4870 #define  TRANS_DDI_BFI_ENABLE		(1<<4)
4871 
4872 /* DisplayPort Transport Control */
4873 #define DP_TP_CTL_A			0x64040
4874 #define DP_TP_CTL_B			0x64140
4875 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4876 #define  DP_TP_CTL_ENABLE			(1UL<<31)
4877 #define  DP_TP_CTL_MODE_SST			(0<<27)
4878 #define  DP_TP_CTL_MODE_MST			(1<<27)
4879 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
4880 #define  DP_TP_CTL_FDI_AUTOTRAIN		(1<<15)
4881 #define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
4882 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
4883 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
4884 #define  DP_TP_CTL_LINK_TRAIN_PAT3		(4<<8)
4885 #define  DP_TP_CTL_LINK_TRAIN_IDLE		(2<<8)
4886 #define  DP_TP_CTL_LINK_TRAIN_NORMAL		(3<<8)
4887 #define  DP_TP_CTL_SCRAMBLE_DISABLE		(1<<7)
4888 
4889 /* DisplayPort Transport Status */
4890 #define DP_TP_STATUS_A			0x64044
4891 #define DP_TP_STATUS_B			0x64144
4892 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4893 #define  DP_TP_STATUS_IDLE_DONE		(1<<25)
4894 #define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
4895 
4896 /* DDI Buffer Control */
4897 #define DDI_BUF_CTL_A				0x64000
4898 #define DDI_BUF_CTL_B				0x64100
4899 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4900 #define  DDI_BUF_CTL_ENABLE			(1UL<<31)
4901 #define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
4902 #define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
4903 #define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
4904 #define  DDI_BUF_EMP_400MV_9_5DB_HSW		(3<<24)   /* Sel3 */
4905 #define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
4906 #define  DDI_BUF_EMP_600MV_3_5DB_HSW		(5<<24)   /* Sel5 */
4907 #define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
4908 #define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
4909 #define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
4910 #define  DDI_BUF_EMP_MASK			(0xf<<24)
4911 #define  DDI_BUF_PORT_REVERSAL			(1<<16)
4912 #define  DDI_BUF_IS_IDLE			(1<<7)
4913 #define  DDI_A_4_LANES				(1<<4)
4914 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
4915 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
4916 
4917 /* DDI Buffer Translations */
4918 #define DDI_BUF_TRANS_A				0x64E00
4919 #define DDI_BUF_TRANS_B				0x64E60
4920 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4921 
4922 /* Sideband Interface (SBI) is programmed indirectly, via
4923  * SBI_ADDR, which contains the register offset; and SBI_DATA,
4924  * which contains the payload */
4925 #define SBI_ADDR			0xC6000
4926 #define SBI_DATA			0xC6004
4927 #define SBI_CTL_STAT			0xC6008
4928 #define  SBI_CTL_DEST_ICLK		(0x0<<16)
4929 #define  SBI_CTL_DEST_MPHY		(0x1<<16)
4930 #define  SBI_CTL_OP_IORD		(0x2<<8)
4931 #define  SBI_CTL_OP_IOWR		(0x3<<8)
4932 #define  SBI_CTL_OP_CRRD		(0x6<<8)
4933 #define  SBI_CTL_OP_CRWR		(0x7<<8)
4934 #define  SBI_RESPONSE_FAIL		(0x1<<1)
4935 #define  SBI_RESPONSE_SUCCESS		(0x0<<1)
4936 #define  SBI_BUSY			(0x1<<0)
4937 #define  SBI_READY			(0x0<<0)
4938 
4939 /* SBI offsets */
4940 #define  SBI_SSCDIVINTPHASE6			0x0600
4941 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
4942 #define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
4943 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
4944 #define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
4945 #define   SBI_SSCDIVINTPHASE_DIR(x)		((x)<<15)
4946 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
4947 #define  SBI_SSCCTL				0x020c
4948 #define  SBI_SSCCTL6				0x060C
4949 #define   SBI_SSCCTL_PATHALT			(1<<3)
4950 #define   SBI_SSCCTL_DISABLE			(1<<0)
4951 #define  SBI_SSCAUXDIV6				0x0610
4952 #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
4953 #define  SBI_DBUFF0				0x2a00
4954 #define   SBI_DBUFF0_ENABLE			(1<<0)
4955 
4956 /* LPT PIXCLK_GATE */
4957 #define PIXCLK_GATE			0xC6020
4958 #define  PIXCLK_GATE_UNGATE		(1<<0)
4959 #define  PIXCLK_GATE_GATE		(0<<0)
4960 
4961 /* SPLL */
4962 #define SPLL_CTL			0x46020
4963 #define  SPLL_PLL_ENABLE		(1UL<<31)
4964 #define  SPLL_PLL_SSC			(1<<28)
4965 #define  SPLL_PLL_NON_SSC		(2<<28)
4966 #define  SPLL_PLL_FREQ_810MHz		(0<<26)
4967 #define  SPLL_PLL_FREQ_1350MHz		(1<<26)
4968 
4969 /* WRPLL */
4970 #define WRPLL_CTL1			0x46040
4971 #define WRPLL_CTL2			0x46060
4972 #define  WRPLL_PLL_ENABLE		(1UL<<31)
4973 #define  WRPLL_PLL_SELECT_SSC		(0x01<<28)
4974 #define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)
4975 #define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
4976 /* WRPLL divider programming */
4977 #define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)
4978 #define  WRPLL_DIVIDER_POST(x)		((x)<<8)
4979 #define  WRPLL_DIVIDER_FEEDBACK(x)	((x)<<16)
4980 
4981 /* Port clock selection */
4982 #define PORT_CLK_SEL_A			0x46100
4983 #define PORT_CLK_SEL_B			0x46104
4984 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4985 #define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
4986 #define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
4987 #define  PORT_CLK_SEL_LCPLL_810		(2<<29)
4988 #define  PORT_CLK_SEL_SPLL		(3<<29)
4989 #define  PORT_CLK_SEL_WRPLL1		(4UL<<29)
4990 #define  PORT_CLK_SEL_WRPLL2		(5UL<<29)
4991 #define  PORT_CLK_SEL_NONE		(7UL<<29)
4992 
4993 /* Transcoder clock selection */
4994 #define TRANS_CLK_SEL_A			0x46140
4995 #define TRANS_CLK_SEL_B			0x46144
4996 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4997 /* For each transcoder, we need to select the corresponding port clock */
4998 #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
4999 #define  TRANS_CLK_SEL_PORT(x)		((x+1)<<29)
5000 
5001 #define _TRANSA_MSA_MISC		0x60410
5002 #define _TRANSB_MSA_MISC		0x61410
5003 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
5004 					       _TRANSB_MSA_MISC)
5005 #define  TRANS_MSA_SYNC_CLK		(1<<0)
5006 #define  TRANS_MSA_6_BPC		(0<<5)
5007 #define  TRANS_MSA_8_BPC		(1<<5)
5008 #define  TRANS_MSA_10_BPC		(2<<5)
5009 #define  TRANS_MSA_12_BPC		(3<<5)
5010 #define  TRANS_MSA_16_BPC		(4<<5)
5011 
5012 /* LCPLL Control */
5013 #define LCPLL_CTL			0x130040
5014 #define  LCPLL_PLL_DISABLE		(1UL<<31)
5015 #define  LCPLL_PLL_LOCK			(1<<30)
5016 #define  LCPLL_CLK_FREQ_MASK		(3<<26)
5017 #define  LCPLL_CLK_FREQ_450		(0<<26)
5018 #define  LCPLL_CD_CLOCK_DISABLE		(1<<25)
5019 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
5020 #define  LCPLL_CD_SOURCE_FCLK		(1<<21)
5021 
5022 /* Pipe WM_LINETIME - watermark line time */
5023 #define PIPE_WM_LINETIME_A		0x45270
5024 #define PIPE_WM_LINETIME_B		0x45274
5025 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5026 					   PIPE_WM_LINETIME_B)
5027 #define   PIPE_WM_LINETIME_MASK			(0x1ff)
5028 #define   PIPE_WM_LINETIME_TIME(x)		((x))
5029 #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
5030 #define   PIPE_WM_LINETIME_IPS_LINETIME(x)	((x)<<16)
5031 
5032 /* SFUSE_STRAP */
5033 #define SFUSE_STRAP			0xc2014
5034 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
5035 #define  SFUSE_STRAP_DDIC_DETECTED	(1<<1)
5036 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
5037 
5038 #define WM_MISC				0x45260
5039 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
5040 
5041 #define WM_DBG				0x45280
5042 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1<<0)
5043 #define  WM_DBG_DISALLOW_MAXFIFO	(1<<1)
5044 #define  WM_DBG_DISALLOW_SPRITE		(1<<2)
5045 
5046 /* pipe CSC */
5047 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
5048 #define _PIPE_A_CSC_COEFF_BY	0x49014
5049 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
5050 #define _PIPE_A_CSC_COEFF_BU	0x4901c
5051 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
5052 #define _PIPE_A_CSC_COEFF_BV	0x49024
5053 #define _PIPE_A_CSC_MODE	0x49028
5054 #define   CSC_BLACK_SCREEN_OFFSET	(1 << 2)
5055 #define   CSC_POSITION_BEFORE_GAMMA	(1 << 1)
5056 #define   CSC_MODE_YUV_TO_RGB		(1 << 0)
5057 #define _PIPE_A_CSC_PREOFF_HI	0x49030
5058 #define _PIPE_A_CSC_PREOFF_ME	0x49034
5059 #define _PIPE_A_CSC_PREOFF_LO	0x49038
5060 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
5061 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
5062 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
5063 
5064 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
5065 #define _PIPE_B_CSC_COEFF_BY	0x49114
5066 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
5067 #define _PIPE_B_CSC_COEFF_BU	0x4911c
5068 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
5069 #define _PIPE_B_CSC_COEFF_BV	0x49124
5070 #define _PIPE_B_CSC_MODE	0x49128
5071 #define _PIPE_B_CSC_PREOFF_HI	0x49130
5072 #define _PIPE_B_CSC_PREOFF_ME	0x49134
5073 #define _PIPE_B_CSC_PREOFF_LO	0x49138
5074 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
5075 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
5076 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
5077 
5078 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5079 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5080 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5081 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5082 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5083 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5084 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5085 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5086 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5087 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5088 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5089 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5090 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5091 
5092 //For gpu top
5093 #define _RING_TAIL      0x00
5094 #define _RING_HEAD      0x04
5095 #define _RING_LEN       0x0C
5096 
5097 #define INST_DONE                0x2090
5098 # define IDCT_DONE			(1UL << 30)
5099 # define IQ_DONE			(1 << 29)
5100 # define PR_DONE			(1 << 28)
5101 # define VLD_DONE			(1 << 27)
5102 # define IP_DONE			(1 << 26)
5103 # define FBC_DONE			(1 << 25)
5104 # define BINNER_DONE			(1 << 24)
5105 # define SF_DONE			(1 << 23)
5106 # define SE_DONE			(1 << 22)
5107 # define WM_DONE			(1 << 21)
5108 # define IZ_DONE			(1 << 20)
5109 # define PERSPECTIVE_INTERP_DONE	(1 << 19)
5110 # define DISPATCHER_DONE		(1 << 18)
5111 # define PROJECTION_DONE		(1 << 17)
5112 # define DEPENDENT_ADDRESS_DONE		(1 << 16)
5113 # define QUAD_CACHE_DONE		(1 << 15)
5114 # define TEXTURE_FETCH_DONE		(1 << 14)
5115 # define TEXTURE_DECOMPRESS_DONE	(1 << 13)
5116 # define SAMPLER_CACHE_DONE		(1 << 12)
5117 # define FILTER_DONE			(1 << 11)
5118 # define BYPASS_FIFO_DONE		(1 << 10)
5119 # define PS_DONE			(1 << 9)
5120 # define CC_DONE			(1 << 8)
5121 # define MAP_FILTER_DONE		(1 << 7)
5122 # define MAP_L2_IDLE			(1 << 6)
5123 # define RING_2_ENABLE			(1 << 2)
5124 # define RING_1_ENABLE			(1 << 1)
5125 # define RING_0_ENABLE			(1 << 0)
5126 
5127 # define I830_GMBUS_DONE		(1 << 26)
5128 # define I830_FBC_DONE			(1 << 25)
5129 # define I830_BINNER_DONE		(1 << 24)
5130 # define I830_MPEG_DONE			(1 << 23)
5131 # define I830_MECO_DONE			(1 << 22)
5132 # define I830_MCD_DONE			(1 << 21)
5133 # define I830_MCSTP_DONE		(1 << 20)
5134 # define I830_CC_DONE			(1 << 19)
5135 # define I830_DG_DONE			(1 << 18)
5136 # define I830_DCMP_DONE			(1 << 17)
5137 # define I830_FTCH_DONE			(1 << 16)
5138 # define I830_IT_DONE			(1 << 15)
5139 # define I830_MG_DONE			(1 << 14)
5140 # define I830_MEC_DONE			(1 << 13)
5141 # define I830_PC_DONE			(1 << 12)
5142 # define I830_QCC_DONE			(1 << 11)
5143 # define I830_TB_DONE			(1 << 10)
5144 # define I830_WM_DONE			(1 << 9)
5145 # define I830_EF_DONE			(1 << 8)
5146 # define I830_BLITTER_DONE		(1 << 7)
5147 # define I830_MAP_L2_DONE		(1 << 6)
5148 # define I830_SECONDARY_RING_3_DONE	(1 << 5)
5149 # define I830_SECONDARY_RING_2_DONE	(1 << 4)
5150 # define I830_SECONDARY_RING_1_DONE	(1 << 3)
5151 # define I830_SECONDARY_RING_0_DONE	(1 << 2)
5152 # define I830_PRIMARY_RING_1_DONE	(1 << 1)
5153 # define I830_PRIMARY_RING_0_DONE	(1 << 0)
5154 
5155 #define INST_DONE_I965              0x206c
5156 # define I965_ROW_0_EU_0_DONE		(1UL << 31)
5157 # define I965_ROW_0_EU_1_DONE		(1UL << 30)
5158 # define I965_ROW_0_EU_2_DONE		(1 << 29)
5159 # define I965_ROW_0_EU_3_DONE		(1 << 28)
5160 # define I965_ROW_1_EU_0_DONE		(1 << 27)
5161 # define I965_ROW_1_EU_1_DONE		(1 << 26)
5162 # define I965_ROW_1_EU_2_DONE		(1 << 25)
5163 # define I965_ROW_1_EU_3_DONE		(1 << 24)
5164 # define I965_SF_DONE			(1 << 23)
5165 # define I965_SE_DONE			(1 << 22)
5166 # define I965_WM_DONE			(1 << 21)
5167 # define I965_DISPATCHER_DONE		(1 << 18)
5168 # define I965_PROJECTION_DONE		(1 << 17)
5169 # define I965_DG_DONE			(1 << 16)
5170 # define I965_QUAD_CACHE_DONE		(1 << 15)
5171 # define I965_TEXTURE_FETCH_DONE	(1 << 14)
5172 # define I965_TEXTURE_DECOMPRESS_DONE	(1 << 13)
5173 # define I965_SAMPLER_CACHE_DONE	(1 << 12)
5174 # define I965_FILTER_DONE		(1 << 11)
5175 # define I965_BYPASS_DONE		(1 << 10)
5176 # define I965_PS_DONE			(1 << 9)
5177 # define I965_CC_DONE			(1 << 8)
5178 # define I965_MAP_FILTER_DONE		(1 << 7)
5179 # define I965_MAP_L2_IDLE		(1 << 6)
5180 # define I965_MA_ROW_0_DONE		(1 << 5)
5181 # define I965_MA_ROW_1_DONE		(1 << 4)
5182 # define I965_IC_ROW_0_DONE		(1 << 3)
5183 # define I965_IC_ROW_1_DONE		(1 << 2)
5184 # define I965_CP_DONE			(1 << 1)
5185 # define I965_RING_0_ENABLE		(1 << 0)
5186 
5187 # define ILK_ROW_0_EU_0_DONE		(1UL << 31)
5188 # define ILK_ROW_0_EU_1_DONE		(1UL << 30)
5189 # define ILK_ROW_0_EU_2_DONE		(1 << 29)
5190 # define ILK_ROW_0_EU_3_DONE		(1 << 28)
5191 # define ILK_ROW_1_EU_0_DONE		(1 << 27)
5192 # define ILK_ROW_1_EU_1_DONE		(1 << 26)
5193 # define ILK_ROW_1_EU_2_DONE		(1 << 25)
5194 # define ILK_ROW_1_EU_3_DONE		(1 << 24)
5195 # define ILK_ROW_2_EU_0_DONE		(1 << 23)
5196 # define ILK_ROW_2_EU_1_DONE		(1 << 22)
5197 # define ILK_ROW_2_EU_2_DONE		(1 << 21)
5198 # define ILK_ROW_2_EU_3_DONE		(1 << 20)
5199 # define ILK_VCP_DONE			(1 << 19)
5200 # define ILK_ROW_0_MATH_DONE		(1 << 18)
5201 # define ILK_ROW_1_MATH_DONE		(1 << 17)
5202 # define ILK_ROW_2_MATH_DONE		(1 << 16)
5203 # define ILK_VC1_DONE			(1 << 15)
5204 # define ILK_ROW_0_MA_DONE		(1 << 14)
5205 # define ILK_ROW_1_MA_DONE		(1 << 13)
5206 # define ILK_ROW_2_MA_DONE		(1 << 12)
5207 # define ILK_ROW_0_ISC_DONE		(1 << 11)
5208 # define ILK_ROW_1_ISC_DONE		(1 << 10)
5209 # define ILK_ROW_2_ISC_DONE		(1 << 9)
5210 # define ILK_VFE_DONE			(1 << 8)
5211 # define ILK_TD_DONE			(1 << 7)
5212 # define ILK_SVTS_DONE			(1 << 6)
5213 # define ILK_TS_DONE			(1 << 5)
5214 # define ILK_GW_DONE			(1 << 4)
5215 # define ILK_AI_DONE			(1 << 3)
5216 # define ILK_AC_DONE			(1 << 2)
5217 # define ILK_AM_DONE			(1 << 1)
5218 
5219 #define GEN6_INSTDONE_1		0x206c
5220 # define GEN6_MA_3_DONE			(1UL << 31)
5221 # define GEN6_EU_32_DONE		(1UL << 30)
5222 # define GEN6_EU_31_DONE		(1 << 29)
5223 # define GEN6_EU_30_DONE		(1 << 28)
5224 # define GEN6_MA_2_DONE			(1 << 27)
5225 # define GEN6_EU_22_DONE		(1 << 26)
5226 # define GEN6_EU_21_DONE		(1 << 25)
5227 # define GEN6_EU_20_DONE		(1 << 24)
5228 # define GEN6_MA_1_DONE			(1 << 23)
5229 # define GEN6_EU_12_DONE		(1 << 22)
5230 # define GEN6_EU_11_DONE		(1 << 21)
5231 # define GEN6_EU_10_DONE		(1 << 20)
5232 # define GEN6_MA_0_DONE			(1 << 19)
5233 # define GEN6_EU_02_DONE		(1 << 18)
5234 # define GEN6_EU_01_DONE		(1 << 17)
5235 # define GEN6_EU_00_DONE		(1 << 16)
5236 # define GEN6_IC_3_DONE			(1 << 15)
5237 # define GEN6_IC_2_DONE			(1 << 14)
5238 # define GEN6_IC_1_DONE			(1 << 13)
5239 # define GEN6_IC_0_DONE			(1 << 12)
5240 # define GEN6_ISC_10_DONE		(1 << 11)
5241 # define GEN6_ISC_32_DONE		(1 << 10)
5242 # define GEN6_VSC_DONE			(1 << 9)
5243 # define GEN6_IEF_DONE			(1 << 8)
5244 # define GEN6_VFE_DONE			(1 << 7)
5245 # define GEN6_TD_DONE			(1 << 6)
5246 # define GEN6_TS_DONE			(1 << 4)
5247 # define GEN6_GW_DONE			(1 << 3)
5248 # define GEN6_HIZ_DONE			(1 << 2)
5249 # define GEN6_AVS_DONE			(1 << 1)
5250 
5251 
5252 /* Current primary/secondary DMA fetch addresses:
5253  */
5254 #define DMA_FADD_P             0x2078
5255 #define DMA_FADD_S               0x20d4
5256 #define INST_DONE_1              0x207c
5257 # define I965_GW_CS_DONE_CR		(1 << 19)
5258 # define I965_SVSM_CS_DONE_CR		(1 << 18)
5259 # define I965_SVDW_CS_DONE_CR		(1 << 17)
5260 # define I965_SVDR_CS_DONE_CR		(1 << 16)
5261 # define I965_SVRW_CS_DONE_CR		(1 << 15)
5262 # define I965_SVRR_CS_DONE_CR		(1 << 14)
5263 # define I965_SVTW_CS_DONE_CR		(1 << 13)
5264 # define I965_MASM_CS_DONE_CR		(1 << 12)
5265 # define I965_MASF_CS_DONE_CR		(1 << 11)
5266 # define I965_MAW_CS_DONE_CR		(1 << 10)
5267 # define I965_EM1_CS_DONE_CR		(1 << 9)
5268 # define I965_EM0_CS_DONE_CR		(1 << 8)
5269 # define I965_UC1_CS_DONE		(1 << 7)
5270 # define I965_UC0_CS_DONE		(1 << 6)
5271 # define I965_URB_CS_DONE		(1 << 5)
5272 # define I965_ISC_CS_DONE		(1 << 4)
5273 # define I965_CL_CS_DONE		(1 << 3)
5274 # define I965_GS_CS_DONE		(1 << 2)
5275 # define I965_VS0_CS_DONE		(1 << 1)
5276 # define I965_VF_CS_DONE		(1 << 0)
5277 
5278 # define G4X_BCS_DONE			(1UL << 31)
5279 # define G4X_CS_DONE			(1UL << 30)
5280 # define G4X_MASF_DONE			(1 << 29)
5281 # define G4X_SVDW_DONE			(1 << 28)
5282 # define G4X_SVDR_DONE			(1 << 27)
5283 # define G4X_SVRW_DONE			(1 << 26)
5284 # define G4X_SVRR_DONE			(1 << 25)
5285 # define G4X_ISC_DONE			(1 << 24)
5286 # define G4X_MT_DONE			(1 << 23)
5287 # define G4X_RC_DONE			(1 << 22)
5288 # define G4X_DAP_DONE			(1 << 21)
5289 # define G4X_MAWB_DONE			(1 << 20)
5290 # define G4X_MT_IDLE			(1 << 19)
5291 # define G4X_GBLT_BUSY			(1 << 18)
5292 # define G4X_SVSM_DONE			(1 << 17)
5293 # define G4X_MASM_DONE			(1 << 16)
5294 # define G4X_QC_DONE			(1 << 15)
5295 # define G4X_FL_DONE			(1 << 14)
5296 # define G4X_SC_DONE			(1 << 13)
5297 # define G4X_DM_DONE			(1 << 12)
5298 # define G4X_FT_DONE			(1 << 11)
5299 # define G4X_DG_DONE			(1 << 10)
5300 # define G4X_SI_DONE			(1 << 9)
5301 # define G4X_SO_DONE			(1 << 8)
5302 # define G4X_PL_DONE			(1 << 7)
5303 # define G4X_WIZ_DONE			(1 << 6)
5304 # define G4X_URB_DONE			(1 << 5)
5305 # define G4X_SF_DONE			(1 << 4)
5306 # define G4X_CL_DONE			(1 << 3)
5307 # define G4X_GS_DONE			(1 << 2)
5308 # define G4X_VS0_DONE			(1 << 1)
5309 # define G4X_VF_DONE			(1 << 0)
5310 
5311 #define GEN6_INSTDONE_2		0x207c
5312 # define GEN6_GAM_DONE			(1UL << 31)
5313 # define GEN6_CS_DONE			(1UL << 30)
5314 # define GEN6_WMBE_DONE			(1 << 29)
5315 # define GEN6_SVRW_DONE			(1 << 28)
5316 # define GEN6_RCC_DONE			(1 << 27)
5317 # define GEN6_SVG_DONE			(1 << 26)
5318 # define GEN6_ISC_DONE			(1 << 25)
5319 # define GEN6_MT_DONE			(1 << 24)
5320 # define GEN6_RCPFE_DONE		(1 << 23)
5321 # define GEN6_RCPBE_DONE		(1 << 22)
5322 # define GEN6_VDI_DONE			(1 << 21)
5323 # define GEN6_RCZ_DONE			(1 << 20)
5324 # define GEN6_DAP_DONE			(1 << 19)
5325 # define GEN6_PSD_DONE			(1 << 18)
5326 # define GEN6_IZ_DONE			(1 << 17)
5327 # define GEN6_WMFE_DONE			(1 << 16)
5328 # define GEN6_SVSM_DONE			(1 << 15)
5329 # define GEN6_QC_DONE			(1 << 14)
5330 # define GEN6_FL_DONE			(1 << 13)
5331 # define GEN6_SC_DONE			(1 << 12)
5332 # define GEN6_DM_DONE			(1 << 11)
5333 # define GEN6_FT_DONE			(1 << 10)
5334 # define GEN6_DG_DONE			(1 << 9)
5335 # define GEN6_SI_DONE			(1 << 8)
5336 # define GEN6_SO_DONE			(1 << 7)
5337 # define GEN6_PL_DONE			(1 << 6)
5338 # define GEN6_VME_DONE			(1 << 5)
5339 # define GEN6_SF_DONE			(1 << 4)
5340 # define GEN6_CL_DONE			(1 << 3)
5341 # define GEN6_GS_DONE			(1 << 2)
5342 # define GEN6_VS0_DONE			(1 << 1)
5343 # define GEN6_VF_DONE			(1 << 0)
5344 
5345 #define IA_VERTICES_COUNT_QW   0x2310
5346 #define IA_PRIMITIVES_COUNT_QW 0x2318
5347 #define VS_INVOCATION_COUNT_QW 0x2320
5348 #define GS_INVOCATION_COUNT_QW 0x2328
5349 #define GS_PRIMITIVES_COUNT_QW 0x2330
5350 #define CL_INVOCATION_COUNT_QW 0x2338
5351 #define CL_PRIMITIVES_COUNT_QW 0x2340
5352 #define PS_INVOCATION_COUNT_QW 0x2348
5353 #define PS_DEPTH_COUNT_QW      0x2350
5354 #define TIMESTAMP_QW           0x2358
5355 #define CLKCMP_QW              0x2360
5356 
5357 #define I915_GCFGC			0xf0
5358 
5359 
5360 /* Special gtt memory types */
5361 #define AGP_DCACHE_MEMORY	1
5362 #define AGP_PHYS_MEMORY		2
5363 
5364 /* New caching attributes for gen6/sandybridge */
5365 #define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
5366 #define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
5367 
5368 /* flag for GFDT type */
5369 #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
5370 
5371 #endif /* _I915_REG_H_ */
5372