xref: /illumos-gate/usr/src/uts/common/io/arn/arn_ath9k.h (revision c0c93480)
1 /*
2  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2008 Atheros Communications Inc.
8  *
9  * Permission to use, copy, modify, and/or distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  */
21 
22 #ifndef	_ARN_ATH9K_H
23 #define	_ARN_ATH9K_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 #define	FUDGE	2
30 
31 enum ath9k_band {
32 	ATH9K_BAND_2GHZ,
33 	ATH9K_BAND_5GHZ,
34 	ATH9K_NUM_BANDS
35 };
36 
37 #define	ATHEROS_VENDOR_ID	0x168c
38 
39 #define	AR5416_DEVID_PCI	0x0023
40 #define	AR5416_DEVID_PCIE	0x0024
41 #define	AR9160_DEVID_PCI	0x0027
42 #define	AR9280_DEVID_PCI	0x0029
43 #define	AR9280_DEVID_PCIE	0x002a
44 #define	AR9285_DEVID_PCIE	0x002b
45 
46 #define	AR5416_AR9100_DEVID	0x000b
47 
48 #define	AR_SUBVENDOR_ID_NOG	0x0e11
49 #define	AR_SUBVENDOR_ID_NEW_A	0x7065
50 
51 #define	ATH9K_TXERR_XRETRY		0x01
52 #define	ATH9K_TXERR_FILT		0x02
53 #define	ATH9K_TXERR_FIFO		0x04
54 #define	ATH9K_TXERR_XTXOP		0x08
55 #define	ATH9K_TXERR_TIMER_EXPIRED	0x10
56 
57 #define	ATH9K_TX_BA		0x01
58 #define	ATH9K_TX_PWRMGMT	0x02
59 #define	ATH9K_TX_DESC_CFG_ERR	0x04
60 #define	ATH9K_TX_DATA_UNDERRUN	0x08
61 #define	ATH9K_TX_DELIM_UNDERRUN	0x10
62 #define	ATH9K_TX_SW_ABORTED	0x40
63 #define	ATH9K_TX_SW_FILTERED	0x80
64 
65 /* should be changed later */
66 #define	BIT(n)	(1UL << (n))
67 
68 struct ath_tx_status {
69 	uint32_t ts_tstamp;
70 	uint16_t ts_seqnum;
71 	uint8_t ts_status;
72 	uint8_t ts_ratecode;
73 	uint8_t ts_rateindex;
74 	int8_t ts_rssi;
75 	uint8_t ts_shortretry;
76 	uint8_t ts_longretry;
77 	uint8_t ts_virtcol;
78 	uint8_t ts_antenna;
79 	uint8_t ts_flags;
80 	int8_t ts_rssi_ctl0;
81 	int8_t ts_rssi_ctl1;
82 	int8_t ts_rssi_ctl2;
83 	int8_t ts_rssi_ext0;
84 	int8_t ts_rssi_ext1;
85 	int8_t ts_rssi_ext2;
86 	uint8_t pad[3];
87 	uint32_t ba_low;
88 	uint32_t ba_high;
89 	uint32_t evm0;
90 	uint32_t evm1;
91 	uint32_t evm2;
92 };
93 
94 struct ath_rx_status {
95 	uint32_t rs_tstamp;
96 	uint16_t rs_datalen;
97 	uint8_t rs_status;
98 	uint8_t rs_phyerr;
99 	int8_t rs_rssi;
100 	uint8_t rs_keyix;
101 	uint8_t rs_rate;
102 	uint8_t rs_antenna;
103 	uint8_t rs_more;
104 	int8_t rs_rssi_ctl0;
105 	int8_t rs_rssi_ctl1;
106 	int8_t rs_rssi_ctl2;
107 	int8_t rs_rssi_ext0;
108 	int8_t rs_rssi_ext1;
109 	int8_t rs_rssi_ext2;
110 	uint8_t rs_isaggr;
111 	uint8_t rs_moreaggr;
112 	uint8_t rs_num_delims;
113 	uint8_t rs_flags;
114 	uint32_t evm0;
115 	uint32_t evm1;
116 	uint32_t evm2;
117 };
118 
119 #define	ATH9K_RXERR_CRC		0x01
120 #define	ATH9K_RXERR_PHY		0x02
121 #define	ATH9K_RXERR_FIFO	0x04
122 #define	ATH9K_RXERR_DECRYPT	0x08
123 #define	ATH9K_RXERR_MIC		0x10
124 
125 #define	ATH9K_RX_MORE		0x01
126 #define	ATH9K_RX_MORE_AGGR	0x02
127 #define	ATH9K_RX_GI		0x04
128 #define	ATH9K_RX_2040		0x08
129 #define	ATH9K_RX_DELIM_CRC_PRE	0x10
130 #define	ATH9K_RX_DELIM_CRC_POST	0x20
131 #define	ATH9K_RX_DECRYPT_BUSY	0x40
132 
133 #define	ATH9K_RXKEYIX_INVALID	((uint8_t)-1)
134 #define	ATH9K_TXKEYIX_INVALID	((uint32_t)-1)
135 
136 #pragma pack(1)
137 struct ath_desc {
138 	uint32_t ds_link;
139 	uint32_t ds_data;
140 	uint32_t ds_ctl0;
141 	uint32_t ds_ctl1;
142 	uint32_t ds_hw[20];
143 	union {
144 		struct ath_tx_status tx;
145 		struct ath_rx_status rx;
146 		void *stats;
147 	} ds_us;
148 	void *ds_vdata;
149 };
150 #pragma pack()
151 
152 #define	ds_txstat	ds_us.tx
153 #define	ds_rxstat	ds_us.rx
154 #define	ds_stat		ds_us.stats
155 
156 #define	ATH9K_TXDESC_CLRDMASK		0x0001
157 #define	ATH9K_TXDESC_NOACK		0x0002
158 #define	ATH9K_TXDESC_RTSENA		0x0004
159 #define	ATH9K_TXDESC_CTSENA		0x0008
160 /*
161  * ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
162  * the descriptor its marked on.  We take a tx interrupt to reap
163  * descriptors when the h/w hits an EOL condition or
164  * when the descriptor is specifically marked to generate
165  * an interrupt with this flag. Descriptors should be
166  * marked periodically to insure timely replenishing of the
167  * supply needed for sending frames. Defering interrupts
168  * reduces system load and potentially allows more concurrent
169  * work to be done but if done to aggressively can cause
170  * senders to backup. When the hardware queue is left too
171  * large rate control information may also be too out of
172  * date. An Alternative for this is TX interrupt mitigation
173  * but this needs more testing.
174  */
175 #define	ATH9K_TXDESC_INTREQ		0x0010
176 #define	ATH9K_TXDESC_VEOL		0x0020
177 #define	ATH9K_TXDESC_EXT_ONLY		0x0040
178 #define	ATH9K_TXDESC_EXT_AND_CTL	0x0080
179 #define	ATH9K_TXDESC_VMF		0x0100
180 #define	ATH9K_TXDESC_FRAG_IS_ON 	0x0200
181 #define	ATH9K_TXDESC_CAB		0x0400
182 
183 #define	ATH9K_RXDESC_INTREQ		0x0020
184 
185 enum wireless_mode {
186 	ATH9K_MODE_11A = 0,
187 	ATH9K_MODE_11B = 2,
188 	ATH9K_MODE_11G = 3,
189 	ATH9K_MODE_11NA_HT20 = 6,
190 	ATH9K_MODE_11NG_HT20 = 7,
191 	ATH9K_MODE_11NA_HT40PLUS = 8,
192 	ATH9K_MODE_11NA_HT40MINUS = 9,
193 	ATH9K_MODE_11NG_HT40PLUS = 10,
194 	ATH9K_MODE_11NG_HT40MINUS = 11,
195 	ATH9K_MODE_MAX
196 };
197 
198 enum ath9k_hw_caps {
199 	ATH9K_HW_CAP_CHAN_SPREAD		= BIT(0),
200 	ATH9K_HW_CAP_MIC_AESCCM			= BIT(1),
201 	ATH9K_HW_CAP_MIC_CKIP			= BIT(2),
202 	ATH9K_HW_CAP_MIC_TKIP			= BIT(3),
203 	ATH9K_HW_CAP_CIPHER_AESCCM		= BIT(4),
204 	ATH9K_HW_CAP_CIPHER_CKIP		= BIT(5),
205 	ATH9K_HW_CAP_CIPHER_TKIP		= BIT(6),
206 	ATH9K_HW_CAP_VEOL			= BIT(7),
207 	ATH9K_HW_CAP_BSSIDMASK			= BIT(8),
208 	ATH9K_HW_CAP_MCAST_KEYSEARCH		= BIT(9),
209 	ATH9K_HW_CAP_CHAN_HALFRATE		= BIT(10),
210 	ATH9K_HW_CAP_CHAN_QUARTERRATE		= BIT(11),
211 	ATH9K_HW_CAP_HT				= BIT(12),
212 	ATH9K_HW_CAP_GTT			= BIT(13),
213 	ATH9K_HW_CAP_FASTCC			= BIT(14),
214 	ATH9K_HW_CAP_RFSILENT			= BIT(15),
215 	ATH9K_HW_CAP_WOW			= BIT(16),
216 	ATH9K_HW_CAP_CST			= BIT(17),
217 	ATH9K_HW_CAP_ENHANCEDPM			= BIT(18),
218 	ATH9K_HW_CAP_AUTOSLEEP			= BIT(19),
219 	ATH9K_HW_CAP_4KB_SPLITTRANS		= BIT(20),
220 	ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT	= BIT(21),
221 };
222 
223 enum ath9k_capability_type {
224 	ATH9K_CAP_CIPHER = 0,
225 	ATH9K_CAP_TKIP_MIC,
226 	ATH9K_CAP_TKIP_SPLIT,
227 	ATH9K_CAP_PHYCOUNTERS,
228 	ATH9K_CAP_DIVERSITY,
229 	ATH9K_CAP_TXPOW,
230 	ATH9K_CAP_PHYDIAG,
231 	ATH9K_CAP_MCAST_KEYSRCH,
232 	ATH9K_CAP_TSF_ADJUST,
233 	ATH9K_CAP_WME_TKIPMIC,
234 	ATH9K_CAP_RFSILENT,
235 	ATH9K_CAP_ANT_CFG_2GHZ,
236 	ATH9K_CAP_ANT_CFG_5GHZ
237 };
238 
239 struct ath9k_hw_capabilities {
240 	uint32_t hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
241 	uint8_t	 wireless_modes[4]; /* ATH9K_MODE_* */
242 	uint16_t total_queues;
243 	uint16_t keycache_size;
244 	uint16_t low_5ghz_chan, high_5ghz_chan;
245 	uint16_t low_2ghz_chan, high_2ghz_chan;
246 	uint16_t num_mr_retries;
247 	uint16_t rts_aggr_limit;
248 	uint8_t tx_chainmask;
249 	uint8_t rx_chainmask;
250 	uint16_t tx_triglevel_max;
251 	uint16_t reg_cap;
252 	uint8_t num_gpio_pins;
253 	uint8_t num_antcfg_2ghz;
254 	uint8_t num_antcfg_5ghz;
255 };
256 
257 struct ath9k_ops_config {
258 	int dma_beacon_response_time;
259 	int sw_beacon_response_time;
260 	int additional_swba_backoff;
261 	int ack_6mb;
262 	int cwm_ignore_extcca;
263 	uint8_t pcie_powersave_enable;
264 	uint8_t pcie_l1skp_enable;
265 	uint8_t pcie_clock_req;
266 	uint32_t pcie_waen;
267 	int pcie_power_reset;
268 	uint8_t pcie_restore;
269 	uint8_t analog_shiftreg;
270 	uint8_t ht_enable;
271 	uint32_t ofdm_trig_low;
272 	uint32_t ofdm_trig_high;
273 	uint32_t cck_trig_high;
274 	uint32_t cck_trig_low;
275 	uint32_t enable_ani;
276 	uint8_t noise_immunity_level;
277 	uint32_t ofdm_weaksignal_det;
278 	uint32_t cck_weaksignal_thr;
279 	uint8_t spur_immunity_level;
280 	uint8_t firstep_level;
281 	int8_t rssi_thr_high;
282 	int8_t rssi_thr_low;
283 	uint16_t diversity_control;
284 	uint16_t antenna_switch_swap;
285 	int serialize_regmode;
286 	int intr_mitigation;
287 #define	SPUR_DISABLE		0
288 #define	SPUR_ENABLE_IOCTL	1
289 #define	SPUR_ENABLE_EEPROM	2
290 #define	AR_EEPROM_MODAL_SPURS	5
291 #define	AR_SPUR_5413_1		1640
292 #define	AR_SPUR_5413_2		1200
293 #define	AR_NO_SPUR		0x8000
294 #define	AR_BASE_FREQ_2GHZ	2300
295 #define	AR_BASE_FREQ_5GHZ	4900
296 #define	AR_SPUR_FEEQ_BOUND_HT40	19
297 #define	AR_SPUR_FEEQ_BOUND_HT20	10
298 	int spurmode;
299 	uint16_t spurchans[AR_EEPROM_MODAL_SPURS][2];
300 };
301 
302 enum ath9k_tx_queue {
303 	ATH9K_TX_QUEUE_INACTIVE = 0,
304 	ATH9K_TX_QUEUE_DATA,
305 	ATH9K_TX_QUEUE_BEACON,
306 	ATH9K_TX_QUEUE_CAB,
307 	ATH9K_TX_QUEUE_UAPSD,
308 	ATH9K_TX_QUEUE_PSPOLL
309 };
310 
311 #define	ATH9K_NUM_TX_QUEUES 10
312 
313 enum ath9k_tx_queue_subtype {
314 	ATH9K_WME_AC_BK = 0,
315 	ATH9K_WME_AC_BE,
316 	ATH9K_WME_AC_VI,
317 	ATH9K_WME_AC_VO,
318 	ATH9K_WME_UPSD
319 };
320 
321 enum ath9k_tx_queue_flags {
322 	TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
323 	TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
324 	TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
325 	TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
326 	TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
327 	TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
328 	TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
329 	TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
330 	TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
331 };
332 
333 #define	ATH9K_TXQ_USEDEFAULT	((uint32_t)(-1))
334 
335 #define	ATH9K_DECOMP_MASK_SIZE		128
336 #define	ATH9K_READY_TIME_LO_BOUND	50
337 #define	ATH9K_READY_TIME_HI_BOUND	96
338 
339 enum ath9k_pkt_type {
340 	ATH9K_PKT_TYPE_NORMAL = 0,
341 	ATH9K_PKT_TYPE_ATIM,
342 	ATH9K_PKT_TYPE_PSPOLL,
343 	ATH9K_PKT_TYPE_BEACON,
344 	ATH9K_PKT_TYPE_PROBE_RESP,
345 	ATH9K_PKT_TYPE_CHIRP,
346 	ATH9K_PKT_TYPE_GRP_POLL,
347 };
348 
349 struct ath9k_tx_queue_info {
350 	uint32_t tqi_ver;
351 	enum ath9k_tx_queue tqi_type;
352 	enum ath9k_tx_queue_subtype tqi_subtype;
353 	enum ath9k_tx_queue_flags tqi_qflags;
354 	uint32_t tqi_priority;
355 	uint32_t tqi_aifs;
356 	uint32_t tqi_cwmin;
357 	uint32_t tqi_cwmax;
358 	uint16_t tqi_shretry;
359 	uint16_t tqi_lgretry;
360 	uint32_t tqi_cbrPeriod;
361 	uint32_t tqi_cbrOverflowLimit;
362 	uint32_t tqi_burstTime;
363 	uint32_t tqi_readyTime;
364 	uint32_t tqi_physCompBuf;
365 	uint32_t tqi_intFlags;
366 };
367 
368 enum ath9k_rx_filter {
369 	ATH9K_RX_FILTER_UCAST = 0x00000001,
370 	ATH9K_RX_FILTER_MCAST = 0x00000002,
371 	ATH9K_RX_FILTER_BCAST = 0x00000004,
372 	ATH9K_RX_FILTER_CONTROL = 0x00000008,
373 	ATH9K_RX_FILTER_BEACON = 0x00000010,
374 	ATH9K_RX_FILTER_PROM = 0x00000020,
375 	ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
376 	ATH9K_RX_FILTER_PSPOLL = 0x00004000,
377 	ATH9K_RX_FILTER_PHYERR = 0x00000100,
378 	ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
379 };
380 
381 enum ath9k_int {
382 	ATH9K_INT_RX = 0x00000001,
383 	ATH9K_INT_RXDESC = 0x00000002,
384 	ATH9K_INT_RXNOFRM = 0x00000008,
385 	ATH9K_INT_RXEOL = 0x00000010,
386 	ATH9K_INT_RXORN = 0x00000020,
387 	ATH9K_INT_TX = 0x00000040,
388 	ATH9K_INT_TXDESC = 0x00000080,
389 	ATH9K_INT_TIM_TIMER = 0x00000100,
390 	ATH9K_INT_TXURN = 0x00000800,
391 	ATH9K_INT_MIB = 0x00001000,
392 	ATH9K_INT_RXPHY = 0x00004000,
393 	ATH9K_INT_RXKCM = 0x00008000,
394 	ATH9K_INT_SWBA = 0x00010000,
395 	ATH9K_INT_BMISS = 0x00040000,
396 	ATH9K_INT_BNR = 0x00100000,
397 	ATH9K_INT_TIM = 0x00200000,
398 	ATH9K_INT_DTIM = 0x00400000,
399 	ATH9K_INT_DTIMSYNC = 0x00800000,
400 	ATH9K_INT_GPIO = 0x01000000,
401 	ATH9K_INT_CABEND = 0x02000000,
402 	ATH9K_INT_CST = 0x10000000,
403 	ATH9K_INT_GTT = 0x20000000,
404 	ATH9K_INT_FATAL = 0x40000000,
405 	ATH9K_INT_GLOBAL = INT_MIN,
406 	ATH9K_INT_BMISC = ATH9K_INT_TIM |
407 		ATH9K_INT_DTIM |
408 		ATH9K_INT_DTIMSYNC |
409 		ATH9K_INT_CABEND,
410 	ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
411 		ATH9K_INT_RXDESC |
412 		ATH9K_INT_RXEOL |
413 		ATH9K_INT_RXORN |
414 		ATH9K_INT_TXURN |
415 		ATH9K_INT_TXDESC |
416 		ATH9K_INT_MIB |
417 		ATH9K_INT_RXPHY |
418 		ATH9K_INT_RXKCM |
419 		ATH9K_INT_SWBA |
420 		ATH9K_INT_BMISS |
421 		ATH9K_INT_GPIO,
422 	ATH9K_INT_NOCARD = -1
423 };
424 
425 #define	ATH9K_RATESERIES_RTS_CTS	0x0001
426 #define	ATH9K_RATESERIES_2040		0x0002
427 #define	ATH9K_RATESERIES_HALFGI		0x0004
428 
429 struct ath9k_11n_rate_series {
430 	uint32_t Tries;
431 	uint32_t Rate;
432 	uint32_t PktDuration;
433 	uint32_t ChSel;
434 	uint32_t RateFlags;
435 };
436 
437 #define	CHANNEL_CW_INT		0x00002
438 #define	CHANNEL_CCK		0x00020
439 #define	CHANNEL_OFDM		0x00040
440 #define	CHANNEL_2GHZ		0x00080
441 #define	CHANNEL_5GHZ		0x00100
442 #define	CHANNEL_PASSIVE		0x00200
443 #define	CHANNEL_DYN		0x00400
444 #define	CHANNEL_HALF		0x04000
445 #define	CHANNEL_QUARTER		0x08000
446 #define	CHANNEL_HT20		0x10000
447 #define	CHANNEL_HT40PLUS	0x20000
448 #define	CHANNEL_HT40MINUS	0x40000
449 
450 #define	CHANNEL_INTERFERENCE	0x01
451 #define	CHANNEL_DFS		0x02
452 #define	CHANNEL_4MS_LIMIT	0x04
453 #define	CHANNEL_DFS_CLEAR	0x08
454 #define	CHANNEL_DISALLOW_ADHOC	0x10
455 #define	CHANNEL_PER_11D_ADHOC	0x20
456 
457 #define	CHANNEL_A		(CHANNEL_5GHZ|CHANNEL_OFDM)
458 #define	CHANNEL_B		(CHANNEL_2GHZ|CHANNEL_CCK)
459 #define	CHANNEL_G		(CHANNEL_2GHZ|CHANNEL_OFDM)
460 #define	CHANNEL_G_HT20		(CHANNEL_2GHZ|CHANNEL_HT20)
461 #define	CHANNEL_A_HT20		(CHANNEL_5GHZ|CHANNEL_HT20)
462 #define	CHANNEL_G_HT40PLUS	(CHANNEL_2GHZ|CHANNEL_HT40PLUS)
463 #define	CHANNEL_G_HT40MINUS	(CHANNEL_2GHZ|CHANNEL_HT40MINUS)
464 #define	CHANNEL_A_HT40PLUS	(CHANNEL_5GHZ|CHANNEL_HT40PLUS)
465 #define	CHANNEL_A_HT40MINUS	(CHANNEL_5GHZ|CHANNEL_HT40MINUS)
466 #define	CHANNEL_ALL		\
467 	(CHANNEL_OFDM|		\
468 	CHANNEL_CCK|		\
469 	CHANNEL_2GHZ |		\
470 	CHANNEL_5GHZ |		\
471 	CHANNEL_HT20 |		\
472 	CHANNEL_HT40PLUS |	\
473 	CHANNEL_HT40MINUS)
474 
475 struct ath9k_channel {
476 	uint16_t channel;
477 	uint32_t channelFlags;
478 	uint8_t privFlags;
479 	int8_t maxRegTxPower;
480 	int8_t maxTxPower;
481 	int8_t minTxPower;
482 	uint32_t chanmode;
483 	int32_t CalValid;
484 	boolean_t oneTimeCalsDone;
485 	int8_t iCoff;
486 	int8_t qCoff;
487 	int16_t rawNoiseFloor;
488 	int8_t antennaMax;
489 	uint32_t regDmnFlags;
490 	uint32_t conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
491 #ifdef ARN_NF_PER_CHAN
492 	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
493 #endif
494 };
495 
496 #define	IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
497 	(((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
498 	(((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
499 	(((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
500 #define	IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
501 	(((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
502 	(((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
503 	(((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
504 #define	IS_CHAN_OFDM(_c)	(((_c)->channelFlags & CHANNEL_OFDM) != 0)
505 #define	IS_CHAN_5GHZ(_c)	(((_c)->channelFlags & CHANNEL_5GHZ) != 0)
506 #define	IS_CHAN_2GHZ(_c)	(((_c)->channelFlags & CHANNEL_2GHZ) != 0)
507 #define	IS_CHAN_PASSIVE(_c)	(((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
508 #define	IS_CHAN_HALF_RATE(_c)	(((_c)->channelFlags & CHANNEL_HALF) != 0)
509 #define	IS_CHAN_QUARTER_RATE(_c) \
510 	(((_c)->channelFlags & CHANNEL_QUARTER) != 0)
511 
512 /* These macros check chanmode and not channelFlags */
513 #define	IS_CHAN_B(_c)	((_c)->chanmode == CHANNEL_B)
514 #define	IS_CHAN_HT20(_c)	(((_c)->chanmode == CHANNEL_A_HT20) ||	\
515 	((_c)->chanmode == CHANNEL_G_HT20))
516 #define	IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||	\
517 	((_c)->chanmode == CHANNEL_A_HT40MINUS) ||	\
518 	((_c)->chanmode == CHANNEL_G_HT40PLUS) ||	\
519 	((_c)->chanmode == CHANNEL_G_HT40MINUS))
520 #define	IS_CHAN_HT(_c)	(IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
521 
522 #define	IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c)	((_c) > 4940 && (_c) < 4990)
523 #define	IS_CHAN_A_5MHZ_SPACED(_c)			\
524 	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&	\
525 	(((_c)->channel % 20) != 0) &&			\
526 	(((_c)->channel % 10) != 0))
527 
528 struct ath9k_keyval {
529 	uint8_t kv_type;
530 	uint8_t kv_pad;
531 	uint16_t kv_len;
532 	uint8_t kv_val[16];
533 	uint8_t kv_mic[8];
534 	uint8_t kv_txmic[8];
535 };
536 
537 enum ath9k_key_type {
538 	ATH9K_KEY_TYPE_CLEAR,
539 	ATH9K_KEY_TYPE_WEP,
540 	ATH9K_KEY_TYPE_AES,
541 	ATH9K_KEY_TYPE_TKIP,
542 };
543 
544 enum ath9k_cipher {
545 	ATH9K_CIPHER_WEP = 0,
546 	ATH9K_CIPHER_AES_OCB = 1,
547 	ATH9K_CIPHER_AES_CCM = 2,
548 	ATH9K_CIPHER_CKIP = 3,
549 	ATH9K_CIPHER_TKIP = 4,
550 	ATH9K_CIPHER_CLR = 5,
551 	ATH9K_CIPHER_MIC = 127
552 };
553 
554 #define	AR_EEPROM_EEPCAP_COMPRESS_DIS	0x0001
555 #define	AR_EEPROM_EEPCAP_AES_DIS	0x0002
556 #define	AR_EEPROM_EEPCAP_FASTFRAME_DIS	0x0004
557 #define	AR_EEPROM_EEPCAP_BURST_DIS	0x0008
558 #define	AR_EEPROM_EEPCAP_MAXQCU		0x01F0
559 #define	AR_EEPROM_EEPCAP_MAXQCU_S	4
560 #define	AR_EEPROM_EEPCAP_HEAVY_CLIP_EN	0x0200
561 #define	AR_EEPROM_EEPCAP_KC_ENTRIES	0xF000
562 #define	AR_EEPROM_EEPCAP_KC_ENTRIES_S	12
563 
564 #define	AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND	0x0040
565 #define	AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN	0x0080
566 #define	AR_EEPROM_EEREGCAP_EN_KK_U2		0x0100
567 #define	AR_EEPROM_EEREGCAP_EN_KK_MIDBAND	0x0200
568 #define	AR_EEPROM_EEREGCAP_EN_KK_U1_ODD		0x0400
569 #define	AR_EEPROM_EEREGCAP_EN_KK_NEW_11A	0x0800
570 
571 #define	AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 	0x4000
572 #define	AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0	0x8000
573 
574 #define	SD_NO_CTL	0xE0
575 #define	NO_CTL		0xff
576 #define	CTL_MODE_M	7
577 #define	CTL_11A		0
578 #define	CTL_11B		1
579 #define	CTL_11G		2
580 #define	CTL_2GHT20	5
581 #define	CTL_5GHT20	6
582 #define	CTL_2GHT40	7
583 #define	CTL_5GHT40	8
584 
585 #define	AR_EEPROM_MAC(i)	(0x1d+(i))
586 
587 #define	AR_EEPROM_RFSILENT_GPIO_SEL	0x001c
588 #define	AR_EEPROM_RFSILENT_GPIO_SEL_S	2
589 #define	AR_EEPROM_RFSILENT_POLARITY	0x0002
590 #define	AR_EEPROM_RFSILENT_POLARITY_S	1
591 
592 #define	CTRY_DEBUG	0x1ff
593 #define	CTRY_DEFAULT	0
594 
595 enum reg_ext_bitmap {
596 	REG_EXT_JAPAN_MIDBAND = 1,
597 	REG_EXT_FCC_DFS_HT40 = 2,
598 	REG_EXT_JAPAN_NONDFS_HT40 = 3,
599 	REG_EXT_JAPAN_DFS_HT40 = 4
600 };
601 
602 struct ath9k_country_entry {
603 	uint16_t countryCode;
604 	uint16_t regDmnEnum;
605 	uint16_t regDmn5G;
606 	uint16_t regDmn2G;
607 	uint8_t isMultidomain;
608 	uint8_t iso[3];
609 };
610 
611 /* Register read/write primitives */
612 #define	REG_WRITE(_ah, _reg, _val)	arn_iowrite32((_ah), (_reg), (_val))
613 #define	REG_READ(_ah, _reg)	arn_ioread32((_ah), (_reg))
614 #define	FLASH_READ(_ah, _reg)					\
615 	ddi_get16((_ah->ah_sc)->sc_io_handle,			\
616 	    (uint16_t *)((uintptr_t)(_ah)->ah_sh + (_reg)))
617 
618 #define	SM(_v, _f)	(((_v) << _f##_S) & _f)
619 #define	MS(_v, _f)	(((_v) & _f) >> _f##_S)
620 #define	REG_RMW(_a, _r, _set, _clr)	\
621 	REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
622 #define	REG_RMW_FIELD(_a, _r, _f, _v) \
623 	REG_WRITE(_a, _r, \
624 	(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
625 #define	REG_SET_BIT(_a, _r, _f) \
626 	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
627 #define	REG_CLR_BIT(_a, _r, _f) \
628 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
629 
630 #define	ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS	0x00000001
631 
632 #define	INIT_AIFS	2
633 #define	INIT_CWMIN	15
634 #define	INIT_CWMIN_11B	31
635 #define	INIT_CWMAX	1023
636 #define	INIT_SH_RETRY	10
637 #define	INIT_LG_RETRY	10
638 #define	INIT_SSH_RETRY	32
639 #define	INIT_SLG_RETRY	32
640 
641 #define	WLAN_CTRL_FRAME_SIZE	(2+2+6+4)
642 
643 #define	ATH_AMPDU_LIMIT_MAX	(64 * 1024 - 1)
644 #define	ATH_AMPDU_LIMIT_DEFAULT	ATH_AMPDU_LIMIT_MAX
645 
646 #define	FCS_LEN	4
647 #define	IEEE80211_WEP_IVLEN	3
648 #define	IEEE80211_WEP_KIDLEN	1
649 #define	IEEE80211_WEP_CRCLEN	4
650 #define	IEEE80211_MAX_MPDU_LEN	(3840 + FCS_LEN +	\
651 	(IEEE80211_WEP_IVLEN +	\
652 	IEEE80211_WEP_KIDLEN +	\
653 	IEEE80211_WEP_CRCLEN))
654 #define	MAX_RATE_POWER	63
655 
656 enum ath9k_power_mode {
657 	ATH9K_PM_AWAKE = 0,
658 	ATH9K_PM_FULL_SLEEP,
659 	ATH9K_PM_NETWORK_SLEEP,
660 	ATH9K_PM_UNDEFINED
661 };
662 
663 struct ath9k_mib_stats {
664 	uint32_t ackrcv_bad;
665 	uint32_t rts_bad;
666 	uint32_t rts_good;
667 	uint32_t fcs_bad;
668 	uint32_t beacons;
669 };
670 
671 enum ath9k_ant_setting {
672 	ATH9K_ANT_VARIABLE = 0,
673 	ATH9K_ANT_FIXED_A,
674 	ATH9K_ANT_FIXED_B
675 };
676 
677 
678 enum ath9k_opmode {
679 	ATH9K_M_STA = 1,
680 	ATH9K_M_IBSS = 0,
681 	ATH9K_M_HOSTAP = 6,
682 	ATH9K_M_MONITOR = 8
683 };
684 
685 
686 #define	ATH9K_SLOT_TIME_6	6
687 #define	ATH9K_SLOT_TIME_9	9
688 #define	ATH9K_SLOT_TIME_20	20
689 
690 enum ath9k_ht_macmode {
691 	ATH9K_HT_MACMODE_20 = 0,
692 	ATH9K_HT_MACMODE_2040 = 1,
693 };
694 
695 enum ath9k_ht_extprotspacing {
696 	ATH9K_HT_EXTPROTSPACING_20 = 0,
697 	ATH9K_HT_EXTPROTSPACING_25 = 1,
698 };
699 
700 struct ath9k_ht_cwm {
701 	enum ath9k_ht_macmode ht_macmode;
702 	enum ath9k_ht_extprotspacing ht_extprotspacing;
703 };
704 
705 enum ath9k_ani_cmd {
706 	ATH9K_ANI_PRESENT = 0x1,
707 	ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
708 	ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
709 	ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
710 	ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
711 	ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
712 	ATH9K_ANI_MODE = 0x40,
713 	ATH9K_ANI_PHYERR_RESET = 0x80,
714 	ATH9K_ANI_ALL = 0xff
715 };
716 
717 enum ath9k_tp_scale {
718 	ATH9K_TP_SCALE_MAX = 0,
719 	ATH9K_TP_SCALE_50,
720 	ATH9K_TP_SCALE_25,
721 	ATH9K_TP_SCALE_12,
722 	ATH9K_TP_SCALE_MIN
723 };
724 
725 enum ser_reg_mode {
726 	SER_REG_MODE_OFF = 0,
727 	SER_REG_MODE_ON = 1,
728 	SER_REG_MODE_AUTO = 2,
729 };
730 
731 #define	AR_PHY_CCA_MAX_GOOD_VALUE		-85
732 #define	AR_PHY_CCA_MAX_HIGH_VALUE		-62
733 #define	AR_PHY_CCA_MIN_BAD_VALUE		-121
734 #define	AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT	3
735 #define	AR_PHY_CCA_FILTERWINDOW_LENGTH		5
736 
737 #define	ATH9K_NF_CAL_HIST_MAX		5
738 #define	NUM_NF_READINGS			6
739 
740 struct ath9k_nfcal_hist {
741 	int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
742 	uint8_t currIndex;
743 	int16_t privNF;
744 	uint8_t invalidNFcount;
745 };
746 
747 struct ath9k_beacon_state {
748 	uint32_t bs_nexttbtt;
749 	uint32_t bs_nextdtim;
750 	uint32_t bs_intval;
751 #define	ATH9K_BEACON_PERIOD	0x0000ffff
752 #define	ATH9K_BEACON_ENA	0x00800000
753 #define	ATH9K_BEACON_RESET_TSF	0x01000000
754 #define	ATH9K_TSFOOR_THRESHOLD	0x00004240 /* 16k us */
755 	uint32_t bs_dtimperiod;
756 	uint16_t bs_cfpperiod;
757 	uint16_t bs_cfpmaxduration;
758 	uint32_t bs_cfpnext;
759 	uint16_t bs_timoffset;
760 	uint16_t bs_bmissthreshold;
761 	uint32_t bs_sleepduration;
762 	uint32_t bs_tsfoor_threshold;
763 };
764 
765 struct ath9k_node_stats {
766 	uint32_t ns_avgbrssi;
767 	uint32_t ns_avgrssi;
768 	uint32_t ns_avgtxrssi;
769 	uint32_t ns_avgtxrate;
770 };
771 
772 #define	ATH9K_RSSI_EP_MULTIPLIER			(1<<7)
773 
774 #define	AR_GPIO_OUTPUT_MUX_AS_OUTPUT			0
775 #define	AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED	1
776 #define	AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED		2
777 #define	AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED		5
778 #define	AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED		6
779 
780 enum {
781 	ATH9K_RESET_POWER_ON,
782 	ATH9K_RESET_WARM,
783 	ATH9K_RESET_COLD,
784 };
785 
786 #define	AH_USE_EEPROM	0x1
787 
788 struct ath_hal {
789 	uint32_t ah_magic;
790 	uint16_t ah_devid;
791 	uint16_t ah_subvendorid;
792 	uint32_t ah_macVersion;
793 	uint16_t ah_macRev;
794 	uint16_t ah_phyRev;
795 	uint16_t ah_analog5GhzRev;
796 	uint16_t ah_analog2GhzRev;
797 
798 	caddr_t	 ah_sh;
799 	struct arn_softc *ah_sc;
800 	enum ath9k_opmode ah_opmode;
801 	struct ath9k_ops_config ah_config;
802 	struct ath9k_hw_capabilities ah_caps;
803 
804 	uint16_t ah_countryCode;
805 	uint32_t ah_flags;
806 	int16_t ah_powerLimit;
807 	uint16_t ah_maxPowerLevel;
808 	uint32_t ah_tpScale;
809 	uint16_t ah_currentRD;
810 	uint16_t ah_currentRDExt;
811 	uint16_t ah_currentRDInUse;
812 	uint16_t ah_currentRD5G;
813 	uint16_t ah_currentRD2G;
814 	char ah_iso[4];
815 
816 	struct ath9k_channel ah_channels[150];
817 	struct ath9k_channel *ah_curchan;
818 	uint32_t ah_nchan;
819 
820 	boolean_t ah_isPciExpress;
821 	uint16_t ah_txTrigLevel;
822 	uint16_t ah_rfsilent;
823 	uint32_t ah_rfkill_gpio;
824 	uint32_t ah_rfkill_polarity;
825 
826 	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
827 };
828 
829 struct chan_centers {
830 	uint16_t synth_center;
831 	uint16_t ctl_center;
832 	uint16_t ext_center;
833 };
834 
835 struct ath_rate_table;
836 
837 /* Helpers */
838 
839 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
840     const struct ath9k_channel *chan);
841 boolean_t ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask,
842     uint32_t val);
843 uint32_t ath9k_hw_reverse_bits(uint32_t val, uint32_t n);
844 boolean_t ath9k_get_channel_edges(struct ath_hal *ah,
845     uint16_t flags, uint16_t *low, uint16_t *high);
846 uint16_t ath9k_hw_computetxtime(struct ath_hal *ah,
847     struct ath_rate_table *rates,
848     uint32_t frameLen, uint16_t rateix,
849     boolean_t shortPreamble);
850 uint32_t ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags);
851 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
852     struct ath9k_channel *chan,
853     struct chan_centers *centers);
854 
855 /* Attach, Detach */
856 
857 const char *ath9k_hw_probe(uint16_t vendorid, uint16_t devid);
858 void ath9k_hw_detach(struct ath_hal *ah);
859 struct ath_hal *ath9k_hw_attach(uint16_t devid, struct arn_softc *sc,
860     caddr_t mem, int *error);
861 void ath9k_hw_rfdetach(struct ath_hal *ah);
862 
863 
864 /* HW Reset */
865 
866 boolean_t ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
867     enum ath9k_ht_macmode macmode,
868     uint8_t txchainmask, uint8_t rxchainmask,
869     enum ath9k_ht_extprotspacing extprotspacing,
870     boolean_t bChannelChange, int *status);
871 
872 /* Key Cache Management */
873 
874 boolean_t ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry);
875 boolean_t ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry,
876     const uint8_t *mac);
877 boolean_t ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry,
878     const struct ath9k_keyval *k, const uint8_t *mac, int xorKey);
879 boolean_t ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry);
880 
881 /* Power Management */
882 
883 boolean_t ath9k_hw_setpower(struct ath_hal *ah,
884     enum ath9k_power_mode mode);
885 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
886 
887 /* Beacon timers */
888 
889 void ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon,
890     uint32_t beacon_period);
891 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
892     const struct ath9k_beacon_state *bs);
893 /* HW Capabilities */
894 
895 boolean_t ath9k_hw_fill_cap_info(struct ath_hal *ah);
896 boolean_t ath9k_hw_getcapability(struct ath_hal *ah,
897     enum ath9k_capability_type type,
898     uint32_t capability, uint32_t *result);
899 boolean_t ath9k_hw_setcapability(struct ath_hal *ah,
900     enum ath9k_capability_type type,
901     uint32_t capability, uint32_t setting,
902     int *status);
903 
904 /* GPIO / RFKILL / Antennae */
905 
906 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio);
907 uint32_t ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio);
908 void ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio,
909     uint32_t ah_signal_type);
910 void ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val);
911 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
912 void ath9k_enable_rfkill(struct ath_hal *ah);
913 #endif
914 int ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg);
915 uint32_t ath9k_hw_getdefantenna(struct ath_hal *ah);
916 void ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna);
917 boolean_t ath9k_hw_setantennaswitch(struct ath_hal *ah,
918     enum ath9k_ant_setting settings,
919     struct ath9k_channel *chan,
920     uint8_t *tx_chainmask,
921     uint8_t *rx_chainmask,
922     uint8_t *antenna_cfgd);
923 
924 /* General Operation */
925 
926 uint32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
927 void ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits);
928 boolean_t ath9k_hw_phy_disable(struct ath_hal *ah);
929 boolean_t ath9k_hw_disable(struct ath_hal *ah);
930 boolean_t ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit);
931 void ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac);
932 boolean_t ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac);
933 void ath9k_hw_setopmode(struct ath_hal *ah);
934 void ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0,
935     uint32_t filter1);
936 void ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask);
937 boolean_t ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask);
938 void ath9k_hw_write_associd(struct ath_hal *ah, const uint8_t *bssid,
939     uint16_t assocId);
940 uint64_t ath9k_hw_gettsf64(struct ath_hal *ah);
941 void ath9k_hw_reset_tsf(struct ath_hal *ah);
942 boolean_t ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting);
943 boolean_t ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us);
944 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
945 
946 /* Regulatory */
947 
948 boolean_t ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
949 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
950     const struct ath9k_channel *c);
951 uint32_t ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
952 uint32_t ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
953     struct ath9k_channel *chan);
954 boolean_t ath9k_regd_init_channels(struct ath_hal *ah,
955     uint32_t maxchans, uint32_t *nchans, uint8_t *regclassids,
956     uint32_t maxregids, uint32_t *nregids, uint16_t cc,
957     boolean_t enableOutdoor, boolean_t enableExtendedChannels);
958 
959 /* ANI */
960 
961 void ath9k_ani_reset(struct ath_hal *ah);
962 void ath9k_hw_ani_monitor(struct ath_hal *ah,
963     const struct ath9k_node_stats *stats,
964     struct ath9k_channel *chan);
965 boolean_t ath9k_hw_phycounters(struct ath_hal *ah);
966 void ath9k_enable_mib_counters(struct ath_hal *ah);
967 void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
968 uint32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
969     uint32_t *rxc_pcnt,
970     uint32_t *rxf_pcnt,
971     uint32_t *txf_pcnt);
972 void ath9k_hw_procmibevent(struct ath_hal *ah,
973     const struct ath9k_node_stats *stats);
974 void ath9k_hw_ani_setup(struct ath_hal *ah);
975 void ath9k_hw_ani_attach(struct ath_hal *ah);
976 void ath9k_hw_ani_detach(struct ath_hal *ah);
977 
978 /* Calibration */
979 
980 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
981     boolean_t *isCalDone);
982 void ath9k_hw_start_nfcal(struct ath_hal *ah);
983 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
984 int16_t ath9k_hw_getnf(struct ath_hal *ah, struct ath9k_channel *chan);
985 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
986 signed short ath9k_hw_getchan_noise(struct ath_hal *ah,
987     struct ath9k_channel *chan);
988 boolean_t ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
989     uint8_t rxchainmask, boolean_t longcal, boolean_t *isCalDone);
990 boolean_t ath9k_hw_init_cal(struct ath_hal *ah,
991     struct ath9k_channel *chan);
992 
993 
994 /* EEPROM */
995 
996 int ath9k_hw_set_txpower(struct ath_hal *ah,
997     struct ath9k_channel *chan,
998     uint16_t cfgCtl,
999     uint8_t twiceAntennaReduction,
1000     uint8_t twiceMaxRegulatoryPower,
1001     uint8_t powerLimit);
1002 void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
1003 boolean_t ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
1004     struct ath9k_channel *chan,
1005     int16_t *ratesArray,
1006     uint16_t cfgCtl,
1007     uint8_t AntennaReduction,
1008     uint8_t twiceMaxRegulatoryPower,
1009     uint8_t powerLimit);
1010 boolean_t ath9k_hw_set_power_cal_table(struct ath_hal *ah,
1011     struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset);
1012 boolean_t ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
1013     struct ath9k_channel *chan);
1014 int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
1015     struct ath9k_channel *chan, uint8_t index, uint16_t *config);
1016 
1017 uint8_t ath9k_hw_get_num_ant_config(struct ath_hal *ah,
1018     enum ath9k_band freq_band);
1019 
1020 uint16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, uint16_t i,
1021     boolean_t is2GHz);
1022 int ath9k_hw_eeprom_attach(struct ath_hal *ah);
1023 
1024 /* Interrupt Handling */
1025 
1026 boolean_t ath9k_hw_intrpend(struct ath_hal *ah);
1027 boolean_t ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
1028 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
1029 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
1030 
1031 /* MAC (PCU/QCU) */
1032 
1033 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1034 uint32_t ath9k_hw_gettxbuf(struct ath_hal *ah, uint32_t q);
1035 boolean_t ath9k_hw_puttxbuf(struct ath_hal *ah, uint32_t q, uint32_t txdp);
1036 boolean_t ath9k_hw_txstart(struct ath_hal *ah, uint32_t q);
1037 uint32_t ath9k_hw_numtxpending(struct ath_hal *ah, uint32_t q);
1038 boolean_t ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
1039     boolean_t bIncTrigLevel);
1040 boolean_t ath9k_hw_stoptxdma(struct ath_hal *ah, uint32_t q);
1041 boolean_t ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1042     uint32_t segLen, boolean_t firstSeg,
1043     boolean_t lastSeg, const struct ath_desc *ds0);
1044 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1045 int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1046 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1047     uint32_t pktLen, enum ath9k_pkt_type type, uint32_t txPower,
1048     uint32_t keyIx, enum ath9k_key_type keyType, uint32_t flags);
1049 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1050     struct ath_desc *lastds,
1051     uint32_t durUpdateEn, uint32_t rtsctsRate,
1052     uint32_t rtsctsDuration,
1053     struct ath9k_11n_rate_series series[],
1054     uint32_t nseries, uint32_t flags);
1055 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1056     uint32_t aggrLen);
1057 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1058     uint32_t numDelims);
1059 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1060 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1061 void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
1062     uint32_t burstDuration);
1063 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
1064     uint32_t vmf);
1065 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, uint32_t *txqs);
1066 boolean_t ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
1067     const struct ath9k_tx_queue_info *qinfo);
1068 boolean_t ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
1069     struct ath9k_tx_queue_info *qinfo);
1070 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1071     const struct ath9k_tx_queue_info *qinfo);
1072 boolean_t ath9k_hw_releasetxqueue(struct ath_hal *ah, uint32_t q);
1073 boolean_t ath9k_hw_resettxqueue(struct ath_hal *ah, uint32_t q);
1074 int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
1075     uint32_t pa, struct ath_desc *nds, uint64_t tsf);
1076 boolean_t ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1077     uint32_t size, uint32_t flags);
1078 boolean_t ath9k_hw_setrxabort(struct ath_hal *ah, boolean_t set);
1079 void ath9k_hw_putrxbuf(struct ath_hal *ah, uint32_t rxdp);
1080 void ath9k_hw_rxena(struct ath_hal *ah);
1081 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1082 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1083 boolean_t ath9k_hw_stopdmarecv(struct ath_hal *ah);
1084 
1085 #ifdef __cplusplus
1086 }
1087 #endif
1088 
1089 #endif /* _ARN_ATH9K_H */
1090