xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi_mac.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _NPI_MAC_H
27 #define	_NPI_MAC_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <npi.h>
34 #include <nxge_mac_hw.h>
35 #include <nxge_mii.h>
36 
37 typedef struct _npi_mac_addr {
38 	uint16_t	w0;
39 	uint16_t	w1;
40 	uint16_t	w2;
41 } npi_mac_addr_t;
42 
43 typedef enum npi_mac_attr {
44 	MAC_PORT_MODE = 0,
45 	MAC_PORT_FRAME_SIZE,
46 	MAC_PORT_ADDR,
47 	MAC_PORT_ADDR_FILTER,
48 	MAC_PORT_ADDR_FILTER_MASK,
49 	XMAC_PORT_IPG,
50 	XMAC_10G_PORT_IPG,
51 	BMAC_PORT_MAX_BURST_SIZE,
52 	BMAC_PORT_PA_SIZE,
53 	BMAC_PORT_CTRL_TYPE
54 } npi_mac_attr_t;
55 
56 /* MAC Mode options */
57 
58 typedef enum npi_mac_mode_e {
59 	MAC_MII_MODE = 0,
60 	MAC_GMII_MODE,
61 	MAC_XGMII_MODE
62 } npi_mac_mode_t;
63 
64 typedef enum npi_mac_reset_e {
65 	TX_MAC_RESET = 1,
66 	RX_MAC_RESET,
67 	XTX_MAC_REG_RESET,
68 	XRX_MAC_REG_RESET,
69 	XTX_MAC_LOGIC_RESET,
70 	XRX_MAC_LOGIC_RESET,
71 	XTX_MAC_RESET_ALL,
72 	XRX_MAC_RESET_ALL,
73 	BMAC_RESET_ALL,
74 	XMAC_RESET_ALL
75 } npi_mac_reset_t;
76 
77 typedef enum xmac_tx_iconfig_e {
78 	ICFG_XMAC_TX_FRAME_XMIT 	= XMAC_TX_FRAME_XMIT,
79 	ICFG_XMAC_TX_UNDERRUN		= XMAC_TX_UNDERRUN,
80 	ICFG_XMAC_TX_MAX_PACKET_ERR	= XMAC_TX_MAX_PACKET_ERR,
81 	ICFG_XMAC_TX_OVERFLOW		= XMAC_TX_OVERFLOW,
82 	ICFG_XMAC_TX_FIFO_XFR_ERR	= XMAC_TX_FIFO_XFR_ERR,
83 	ICFG_XMAC_TX_BYTE_CNT_EXP	= XMAC_TX_BYTE_CNT_EXP,
84 	ICFG_XMAC_TX_FRAME_CNT_EXP	= XMAC_TX_FRAME_CNT_EXP,
85 	ICFG_XMAC_TX_ALL = (XMAC_TX_FRAME_XMIT | XMAC_TX_UNDERRUN |
86 				XMAC_TX_MAX_PACKET_ERR | XMAC_TX_OVERFLOW |
87 				XMAC_TX_FIFO_XFR_ERR |  XMAC_TX_BYTE_CNT_EXP |
88 				XMAC_TX_FRAME_CNT_EXP)
89 } xmac_tx_iconfig_t;
90 
91 typedef enum xmac_rx_iconfig_e {
92 	ICFG_XMAC_RX_FRAME_RCVD		= XMAC_RX_FRAME_RCVD,
93 	ICFG_XMAC_RX_OVERFLOW		= XMAC_RX_OVERFLOW,
94 	ICFG_XMAC_RX_UNDERFLOW		= XMAC_RX_UNDERFLOW,
95 	ICFG_XMAC_RX_CRC_ERR_CNT_EXP	= XMAC_RX_CRC_ERR_CNT_EXP,
96 	ICFG_XMAC_RX_LEN_ERR_CNT_EXP	= XMAC_RX_LEN_ERR_CNT_EXP,
97 	ICFG_XMAC_RX_VIOL_ERR_CNT_EXP	= XMAC_RX_VIOL_ERR_CNT_EXP,
98 	ICFG_XMAC_RX_OCT_CNT_EXP	= XMAC_RX_OCT_CNT_EXP,
99 	ICFG_XMAC_RX_HST_CNT1_EXP	= XMAC_RX_HST_CNT1_EXP,
100 	ICFG_XMAC_RX_HST_CNT2_EXP	= XMAC_RX_HST_CNT2_EXP,
101 	ICFG_XMAC_RX_HST_CNT3_EXP	= XMAC_RX_HST_CNT3_EXP,
102 	ICFG_XMAC_RX_HST_CNT4_EXP	= XMAC_RX_HST_CNT4_EXP,
103 	ICFG_XMAC_RX_HST_CNT5_EXP	= XMAC_RX_HST_CNT5_EXP,
104 	ICFG_XMAC_RX_HST_CNT6_EXP	= XMAC_RX_HST_CNT6_EXP,
105 	ICFG_XMAC_RX_BCAST_CNT_EXP	= XMAC_RX_BCAST_CNT_EXP,
106 	ICFG_XMAC_RX_MCAST_CNT_EXP	= XMAC_RX_MCAST_CNT_EXP,
107 	ICFG_XMAC_RX_FRAG_CNT_EXP	= XMAC_RX_FRAG_CNT_EXP,
108 	ICFG_XMAC_RX_ALIGNERR_CNT_EXP	= XMAC_RX_ALIGNERR_CNT_EXP,
109 	ICFG_XMAC_RX_LINK_FLT_CNT_EXP	= XMAC_RX_LINK_FLT_CNT_EXP,
110 	ICFG_XMAC_RX_HST_CNT7_EXP	= XMAC_RX_HST_CNT7_EXP,
111 	ICFG_XMAC_RX_REMOTE_FLT_DET	= XMAC_RX_REMOTE_FLT_DET,
112 	ICFG_XMAC_RX_LOCAL_FLT_DET	= XMAC_RX_LOCAL_FLT_DET,
113 	ICFG_XMAC_RX_ALL = (XMAC_RX_FRAME_RCVD | XMAC_RX_OVERFLOW |
114 				XMAC_RX_UNDERFLOW | XMAC_RX_CRC_ERR_CNT_EXP |
115 				XMAC_RX_LEN_ERR_CNT_EXP |
116 				XMAC_RX_VIOL_ERR_CNT_EXP |
117 				XMAC_RX_OCT_CNT_EXP | XMAC_RX_HST_CNT1_EXP |
118 				XMAC_RX_HST_CNT2_EXP | XMAC_RX_HST_CNT3_EXP |
119 				XMAC_RX_HST_CNT4_EXP | XMAC_RX_HST_CNT5_EXP |
120 				XMAC_RX_HST_CNT6_EXP | XMAC_RX_BCAST_CNT_EXP |
121 				XMAC_RX_MCAST_CNT_EXP | XMAC_RX_FRAG_CNT_EXP |
122 				XMAC_RX_ALIGNERR_CNT_EXP |
123 				XMAC_RX_LINK_FLT_CNT_EXP |
124 				XMAC_RX_HST_CNT7_EXP |
125 				XMAC_RX_REMOTE_FLT_DET | XMAC_RX_LOCAL_FLT_DET)
126 } xmac_rx_iconfig_t;
127 
128 typedef enum xmac_ctl_iconfig_e {
129 	ICFG_XMAC_CTRL_PAUSE_RCVD	= XMAC_CTRL_PAUSE_RCVD,
130 	ICFG_XMAC_CTRL_PAUSE_STATE	= XMAC_CTRL_PAUSE_STATE,
131 	ICFG_XMAC_CTRL_NOPAUSE_STATE	= XMAC_CTRL_NOPAUSE_STATE,
132 	ICFG_XMAC_CTRL_ALL = (XMAC_CTRL_PAUSE_RCVD | XMAC_CTRL_PAUSE_STATE |
133 				XMAC_CTRL_NOPAUSE_STATE)
134 } xmac_ctl_iconfig_t;
135 
136 
137 typedef enum bmac_tx_iconfig_e {
138 	ICFG_BMAC_TX_FRAME_SENT 	= MAC_TX_FRAME_XMIT,
139 	ICFG_BMAC_TX_UNDERFLOW		= MAC_TX_UNDERRUN,
140 	ICFG_BMAC_TX_MAXPKTSZ_ERR	= MAC_TX_MAX_PACKET_ERR,
141 	ICFG_BMAC_TX_BYTE_CNT_EXP	= MAC_TX_BYTE_CNT_EXP,
142 	ICFG_BMAC_TX_FRAME_CNT_EXP	= MAC_TX_FRAME_CNT_EXP,
143 	ICFG_BMAC_TX_ALL = (MAC_TX_FRAME_XMIT | MAC_TX_UNDERRUN |
144 				MAC_TX_MAX_PACKET_ERR | MAC_TX_BYTE_CNT_EXP |
145 				MAC_TX_FRAME_CNT_EXP)
146 } bmac_tx_iconfig_t;
147 
148 typedef enum bmac_rx_iconfig_e {
149 	ICFG_BMAC_RX_FRAME_RCVD		= MAC_RX_FRAME_RECV,
150 	ICFG_BMAC_RX_OVERFLOW		= MAC_RX_OVERFLOW,
151 	ICFG_BMAC_RX_FRAME_CNT_EXP	= MAC_RX_FRAME_COUNT,
152 	ICFG_BMAC_RX_CRC_ERR_CNT_EXP	= MAC_RX_ALIGN_ERR,
153 	ICFG_BMAC_RX_LEN_ERR_CNT_EXP	= MAC_RX_CRC_ERR,
154 	ICFG_BMAC_RX_VIOL_ERR_CNT_EXP	= MAC_RX_LEN_ERR,
155 	ICFG_BMAC_RX_BYTE_CNT_EXP	= MAC_RX_VIOL_ERR,
156 	ICFG_BMAC_RX_ALIGNERR_CNT_EXP	= MAC_RX_BYTE_CNT_EXP,
157 	ICFG_BMAC_RX_ALL = (MAC_RX_FRAME_RECV | MAC_RX_OVERFLOW |
158 				MAC_RX_FRAME_COUNT | MAC_RX_ALIGN_ERR |
159 				MAC_RX_CRC_ERR | MAC_RX_LEN_ERR |
160 				MAC_RX_VIOL_ERR | MAC_RX_BYTE_CNT_EXP)
161 } bmac_rx_iconfig_t;
162 
163 typedef enum bmac_ctl_iconfig_e {
164 	ICFG_BMAC_CTL_RCVPAUSE		= MAC_CTRL_PAUSE_RECEIVED,
165 	ICFG_BMAC_CTL_INPAUSE_ST	= MAC_CTRL_PAUSE_STATE,
166 	ICFG_BMAC_CTL_INNOTPAUSE_ST	= MAC_CTRL_NOPAUSE_STATE,
167 	ICFG_BMAC_CTL_ALL = (MAC_CTRL_PAUSE_RECEIVED | MAC_CTRL_PAUSE_STATE |
168 				MAC_CTRL_NOPAUSE_STATE)
169 } bmac_ctl_iconfig_t;
170 
171 typedef	enum xmac_tx_config_e {
172 	CFG_XMAC_TX			= 0x00000001,
173 	CFG_XMAC_TX_STRETCH_MODE	= 0x00000002,
174 	CFG_XMAC_VAR_IPG		= 0x00000004,
175 	CFG_XMAC_TX_CRC			= 0x00000008,
176 	CFG_XMAC_TX_ALL			= 0x0000000F
177 } xmac_tx_config_t;
178 
179 typedef enum xmac_rx_config_e {
180 	CFG_XMAC_RX			= 0x00000001,
181 	CFG_XMAC_RX_PROMISCUOUS		= 0x00000002,
182 	CFG_XMAC_RX_PROMISCUOUSGROUP	= 0x00000004,
183 	CFG_XMAC_RX_ERRCHK		= 0x00000008,
184 	CFG_XMAC_RX_CRC_CHK		= 0x00000010,
185 	CFG_XMAC_RX_RESV_MULTICAST	= 0x00000020,
186 	CFG_XMAC_RX_CODE_VIO_CHK	= 0x00000040,
187 	CFG_XMAC_RX_HASH_FILTER		= 0x00000080,
188 	CFG_XMAC_RX_ADDR_FILTER		= 0x00000100,
189 	CFG_XMAC_RX_STRIP_CRC		= 0x00000200,
190 	CFG_XMAC_RX_PAUSE		= 0x00000400,
191 	CFG_XMAC_RX_PASS_FC_FRAME	= 0x00000800,
192 	CFG_XMAC_RX_MAC2IPP_PKT_CNT	= 0x00001000,
193 	CFG_XMAC_RX_ALL			= 0x00001FFF
194 } xmac_rx_config_t;
195 
196 typedef	enum xmac_xif_config_e {
197 	CFG_XMAC_XIF_LED_FORCE		= 0x00000001,
198 	CFG_XMAC_XIF_LED_POLARITY	= 0x00000002,
199 	CFG_XMAC_XIF_SEL_POR_CLK_SRC	= 0x00000004,
200 	CFG_XMAC_XIF_TX_OUTPUT		= 0x00000008,
201 	CFG_XMAC_XIF_LOOPBACK		= 0x00000010,
202 	CFG_XMAC_XIF_LFS		= 0x00000020,
203 	CFG_XMAC_XIF_XPCS_BYPASS	= 0x00000040,
204 	CFG_XMAC_XIF_1G_PCS_BYPASS	= 0x00000080,
205 	CFG_XMAC_XIF_SEL_CLK_25MHZ	= 0x00000100,
206 	CFG_XMAC_XIF_ALL		= 0x000001FF
207 } xmac_xif_config_t;
208 
209 typedef	enum bmac_tx_config_e {
210 	CFG_BMAC_TX			= 0x00000001,
211 	CFG_BMAC_TX_CRC			= 0x00000002,
212 	CFG_BMAC_TX_ALL			= 0x00000003
213 } bmac_tx_config_t;
214 
215 typedef enum bmac_rx_config_e {
216 	CFG_BMAC_RX			= 0x00000001,
217 	CFG_BMAC_RX_STRIP_PAD		= 0x00000002,
218 	CFG_BMAC_RX_STRIP_CRC		= 0x00000004,
219 	CFG_BMAC_RX_PROMISCUOUS		= 0x00000008,
220 	CFG_BMAC_RX_PROMISCUOUSGROUP	= 0x00000010,
221 	CFG_BMAC_RX_HASH_FILTER		= 0x00000020,
222 	CFG_BMAC_RX_ADDR_FILTER		= 0x00000040,
223 	CFG_BMAC_RX_DISCARD_ON_ERR	= 0x00000080,
224 	CFG_BMAC_RX_ALL			= 0x000000FF
225 } bmac_rx_config_t;
226 
227 typedef	enum bmac_xif_config_e {
228 	CFG_BMAC_XIF_TX_OUTPUT		= 0x00000001,
229 	CFG_BMAC_XIF_LOOPBACK		= 0x00000002,
230 	CFG_BMAC_XIF_GMII_MODE		= 0x00000008,
231 	CFG_BMAC_XIF_LINKLED		= 0x00000020,
232 	CFG_BMAC_XIF_LED_POLARITY	= 0x00000040,
233 	CFG_BMAC_XIF_SEL_CLK_25MHZ	= 0x00000080,
234 	CFG_BMAC_XIF_ALL		= 0x000000FF
235 } bmac_xif_config_t;
236 
237 
238 typedef enum xmac_ipg_e {
239 	XGMII_IPG_12_15 = 0,
240 	XGMII_IPG_16_19,
241 	XGMII_IPG_20_23,
242 	MII_GMII_IPG_12,
243 	MII_GMII_IPG_13,
244 	MII_GMII_IPG_14,
245 	MII_GMII_IPG_15,
246 	MII_GMII_IPG_16
247 } xmac_ipg_t;
248 
249 typedef	enum xpcs_reg_e {
250 	XPCS_REG_CONTROL1,
251 	XPCS_REG_STATUS1,
252 	XPCS_REG_DEVICE_ID,
253 	XPCS_REG_SPEED_ABILITY,
254 	XPCS_REG_DEVICE_IN_PKG,
255 	XPCS_REG_CONTROL2,
256 	XPCS_REG_STATUS2,
257 	XPCS_REG_PKG_ID,
258 	XPCS_REG_STATUS,
259 	XPCS_REG_TEST_CONTROL,
260 	XPCS_REG_CONFIG_VENDOR1,
261 	XPCS_REG_DIAG_VENDOR2,
262 	XPCS_REG_MASK1,
263 	XPCS_REG_PACKET_COUNTER,
264 	XPCS_REG_TX_STATEMACHINE,
265 	XPCS_REG_DESCWERR_COUNTER,
266 	XPCS_REG_SYMBOL_ERR_L0_1_COUNTER,
267 	XPCS_REG_SYMBOL_ERR_L2_3_COUNTER,
268 	XPCS_REG_TRAINING_VECTOR
269 } xpcs_reg_t;
270 
271 #define	IS_XMAC_PORT_NUM_VALID(portn)\
272 	((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1))
273 
274 #define	IS_BMAC_PORT_NUM_VALID(portn)\
275 	((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1))
276 
277 #define	XMAC_REG_WR(handle, portn, reg, val)\
278 	NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val))
279 
280 #define	XMAC_REG_RD(handle, portn, reg, val_p)\
281 	NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
282 
283 #define	BMAC_REG_WR(handle, portn, reg, val)\
284 	NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val))
285 
286 #define	BMAC_REG_RD(handle, portn, reg, val_p)\
287 	NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
288 
289 #define	PCS_REG_WR(handle, portn, reg, val)\
290 	NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val))
291 
292 #define	PCS_REG_RD(handle, portn, reg, val_p)\
293 	NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
294 
295 #define	XPCS_REG_WR(handle, portn, reg, val)\
296 	NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val))
297 
298 #define	XPCS_REG_RD(handle, portn, reg, val_p)\
299 	NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
300 
301 #define	MIF_REG_WR(handle, reg, val)\
302 	NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val))
303 
304 #define	MIF_REG_RD(handle, reg, val_p)\
305 	NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
306 
307 
308 /*
309  * When MIF_REG_RD is called inside a poll loop and if the poll takes
310  * very long time to complete, then each poll will print a rt_show_reg
311  * result on the screen and the rtrace "register show" result may
312  * become too messy to read.  The solution is to call MIF_REG_RD_NO_SHOW
313  * instead of MIF_REG_RD in a polling loop. When COSIM or REG_SHOW is
314  * not defined, this macro is the same as MIF_REG_RD.  When both COSIM
315  * and REG_SHOW are defined, this macro calls NXGE_REG_RD64_NO_SHOW
316  * which does not call rt_show_reg.
317  */
318 #if defined(COSIM) && defined(REG_SHOW)
319 #define	MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
320 	NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p))
321 #else
322 	/*	If not COSIM or REG_SHOW, still show */
323 #define	MIF_REG_RD_NO_SHOW(handle, reg, val_p)\
324 	NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
325 #endif
326 
327 #define	ESR_REG_WR(handle, reg, val)\
328 	NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
329 
330 #define	ESR_REG_RD(handle, reg, val_p)\
331 	NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
332 
333 /* Macros to read/modify MAC attributes */
334 
335 #define	SET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\
336 	p.type = attr;\
337 	p.idata[0] = (uint32_t)val;\
338 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
339 }
340 
341 #define	SET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\
342 	p.type = attr;\
343 	p.idata[0] = (uint32_t)val0;\
344 	p.idata[1] = (uint32_t)val1;\
345 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
346 }
347 
348 #define	SET_MAC_ATTR3(handle, p, portn, attr, val0, val1, val2, stat) {\
349 	p.type = attr;\
350 	p.idata[0] = (uint32_t)val0;\
351 	p.idata[1] = (uint32_t)val1;\
352 	p.idata[2] = (uint32_t)val2;\
353 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
354 }
355 
356 #define	SET_MAC_ATTR4(handle, p, portn, attr, val0, val1, val2, val3, stat) {\
357 	p.type = attr;\
358 	p.idata[0] = (uint32_t)val0;\
359 	p.idata[1] = (uint32_t)val1;\
360 	p.idata[2] = (uint32_t)val2;\
361 	p.idata[3] = (uint32_t)val3;\
362 	stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\
363 }
364 
365 #define	GET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\
366 	p.type = attr;\
367 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
368 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
369 		val = p.odata[0];\
370 	}\
371 }
372 
373 #define	GET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\
374 	p.type = attr;\
375 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
376 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
377 		val0 = p.odata[0];\
378 		val1 = p.odata[1];\
379 	}\
380 }
381 
382 #define	GET_MAC_ATTR3(handle, p, portn, attr, val0, val1, \
383 			val2, stat) {\
384 	p.type = attr;\
385 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
386 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
387 		val0 = p.odata[0];\
388 		val1 = p.odata[1];\
389 		val2 = p.odata[2];\
390 	}\
391 }
392 
393 #define	GET_MAC_ATTR4(handle, p, portn, attr, val0, val1, \
394 			val2, val3, stat) {\
395 	p.type = attr;\
396 	if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \
397 					(npi_attr_t *)&p)) == NPI_SUCCESS) {\
398 		val0 = p.odata[0];\
399 		val1 = p.odata[1];\
400 		val2 = p.odata[2];\
401 		val3 = p.odata[3];\
402 	}\
403 }
404 
405 /* MAC specific errors */
406 
407 #define	MAC_PORT_ATTR_INVALID		0x50
408 #define	MAC_RESET_MODE_INVALID		0x51
409 #define	MAC_HASHTAB_ENTRY_INVALID	0x52
410 #define	MAC_HOSTINFO_ENTRY_INVALID	0x53
411 #define	MAC_ALT_ADDR_ENTRY_INVALID	0x54
412 
413 /* MAC error return macros */
414 
415 #define	NPI_MAC_PORT_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
416 					PORT_INVALID | IS_PORT | (portn << 12))
417 #define	NPI_MAC_OPCODE_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
418 					OPCODE_INVALID |\
419 					IS_PORT | (portn << 12))
420 #define	NPI_MAC_HASHTAB_ENTRY_INVALID(portn)\
421 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
422 					MAC_HASHTAB_ENTRY_INVALID |\
423 					IS_PORT | (portn << 12))
424 #define	NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)\
425 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
426 					MAC_HOSTINFO_ENTRY_INVALID |\
427 					IS_PORT | (portn << 12))
428 #define	NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)\
429 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
430 					MAC_ALT_ADDR_ENTRY_INVALID |\
431 					IS_PORT | (portn << 12))
432 #define	NPI_MAC_PORT_ATTR_INVALID(portn)\
433 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
434 					MAC_PORT_ATTR_INVALID |\
435 					IS_PORT | (portn << 12))
436 #define	NPI_MAC_RESET_MODE_INVALID(portn)\
437 					((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
438 					MAC_RESET_MODE_INVALID |\
439 					IS_PORT | (portn << 12))
440 #define	NPI_MAC_PCS_REG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
441 					REGISTER_INVALID |\
442 					IS_PORT | (portn << 12))
443 #define	NPI_TXMAC_RESET_FAILED(portn)	((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
444 					RESET_FAILED | IS_PORT | (portn << 12))
445 #define	NPI_RXMAC_RESET_FAILED(portn)	((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
446 					RESET_FAILED | IS_PORT | (portn << 12))
447 #define	NPI_MAC_CONFIG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
448 					CONFIG_INVALID |\
449 					IS_PORT | (portn << 12))
450 #define	NPI_MAC_REG_INVALID(portn)	((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
451 					REGISTER_INVALID |\
452 					IS_PORT | (portn << 12))
453 #define	NPI_MAC_MII_READ_FAILED(portn)	((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
454 					READ_FAILED | IS_PORT | (portn << 12))
455 #define	NPI_MAC_MII_WRITE_FAILED(portn)	((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
456 					WRITE_FAILED | IS_PORT | (portn << 12))
457 
458 /* library functions prototypes */
459 
460 /* general mac functions */
461 npi_status_t npi_mac_hashtab_entry(npi_handle_t, io_op_t,
462 				uint8_t, uint8_t, uint16_t *);
463 npi_status_t npi_mac_hostinfo_entry(npi_handle_t, io_op_t,
464 				uint8_t, uint8_t,
465 				hostinfo_t *);
466 npi_status_t npi_mac_altaddr_enable(npi_handle_t, uint8_t,
467 				uint8_t);
468 npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t,
469 				uint8_t);
470 npi_status_t npi_mac_altaddr_entry(npi_handle_t, io_op_t,
471 				uint8_t, uint8_t,
472 				npi_mac_addr_t *);
473 npi_status_t npi_mac_port_attr(npi_handle_t, io_op_t, uint8_t,
474 				npi_attr_t *);
475 npi_status_t npi_mac_get_link_status(npi_handle_t, uint8_t,
476 				boolean_t *);
477 npi_status_t npi_mac_get_10g_link_status(npi_handle_t, uint8_t,
478 				boolean_t *);
479 npi_status_t npi_mac_mif_mii_read(npi_handle_t, uint8_t,
480 				uint8_t, uint16_t *);
481 npi_status_t npi_mac_mif_mii_write(npi_handle_t, uint8_t,
482 				uint8_t, uint16_t);
483 npi_status_t npi_mac_mif_link_intr_enable(npi_handle_t, uint8_t,
484 				uint8_t, uint16_t);
485 npi_status_t npi_mac_mif_mdio_read(npi_handle_t, uint8_t,
486 				uint8_t, uint16_t,
487 				uint16_t *);
488 npi_status_t npi_mac_mif_mdio_write(npi_handle_t, uint8_t,
489 				uint8_t, uint16_t,
490 				uint16_t);
491 npi_status_t npi_mac_mif_mdio_link_intr_enable(npi_handle_t,
492 				uint8_t, uint8_t,
493 				uint16_t, uint16_t);
494 npi_status_t npi_mac_mif_link_intr_disable(npi_handle_t, uint8_t);
495 npi_status_t npi_mac_pcs_mii_read(npi_handle_t, uint8_t,
496 				uint8_t, uint16_t *);
497 npi_status_t npi_mac_pcs_mii_write(npi_handle_t, uint8_t,
498 				uint8_t, uint16_t);
499 npi_status_t npi_mac_pcs_link_intr_enable(npi_handle_t, uint8_t);
500 npi_status_t npi_mac_pcs_link_intr_disable(npi_handle_t, uint8_t);
501 npi_status_t npi_mac_pcs_reset(npi_handle_t, uint8_t);
502 
503 /* xmac functions */
504 npi_status_t npi_xmac_reset(npi_handle_t, uint8_t,
505 				npi_mac_reset_t);
506 npi_status_t npi_xmac_xif_config(npi_handle_t, config_op_t,
507 				uint8_t, xmac_xif_config_t);
508 npi_status_t npi_xmac_tx_config(npi_handle_t, config_op_t,
509 				uint8_t, xmac_tx_config_t);
510 npi_status_t npi_xmac_rx_config(npi_handle_t, config_op_t,
511 				uint8_t, xmac_rx_config_t);
512 npi_status_t npi_xmac_tx_iconfig(npi_handle_t, config_op_t,
513 				uint8_t, xmac_tx_iconfig_t);
514 npi_status_t npi_xmac_rx_iconfig(npi_handle_t, config_op_t,
515 				uint8_t, xmac_rx_iconfig_t);
516 npi_status_t npi_xmac_ctl_iconfig(npi_handle_t, config_op_t,
517 				uint8_t, xmac_ctl_iconfig_t);
518 npi_status_t npi_xmac_tx_get_istatus(npi_handle_t, uint8_t,
519 				xmac_tx_iconfig_t *);
520 npi_status_t npi_xmac_rx_get_istatus(npi_handle_t, uint8_t,
521 				xmac_rx_iconfig_t *);
522 npi_status_t npi_xmac_ctl_get_istatus(npi_handle_t, uint8_t,
523 				xmac_ctl_iconfig_t *);
524 npi_status_t npi_xmac_xpcs_reset(npi_handle_t, uint8_t);
525 npi_status_t npi_xmac_xpcs_enable(npi_handle_t, uint8_t);
526 npi_status_t npi_xmac_xpcs_disable(npi_handle_t, uint8_t);
527 npi_status_t npi_xmac_xpcs_read(npi_handle_t, uint8_t,
528 				uint8_t, uint32_t *);
529 npi_status_t npi_xmac_xpcs_write(npi_handle_t, uint8_t,
530 				uint8_t, uint32_t);
531 npi_status_t npi_xmac_xpcs_link_intr_enable(npi_handle_t, uint8_t);
532 npi_status_t npi_xmac_xpcs_link_intr_disable(npi_handle_t,
533 				uint8_t);
534 npi_status_t npi_xmac_xif_led(npi_handle_t, uint8_t,
535 				boolean_t);
536 npi_status_t npi_xmac_zap_tx_counters(npi_handle_t, uint8_t);
537 npi_status_t npi_xmac_zap_rx_counters(npi_handle_t, uint8_t);
538 
539 /* bmac functions */
540 npi_status_t npi_bmac_reset(npi_handle_t, uint8_t,
541 				npi_mac_reset_t mode);
542 npi_status_t npi_bmac_tx_config(npi_handle_t, config_op_t,
543 				uint8_t, bmac_tx_config_t);
544 npi_status_t npi_bmac_rx_config(npi_handle_t, config_op_t,
545 				uint8_t, bmac_rx_config_t);
546 npi_status_t npi_bmac_rx_iconfig(npi_handle_t, config_op_t,
547 				uint8_t, bmac_rx_iconfig_t);
548 npi_status_t npi_bmac_xif_config(npi_handle_t, config_op_t,
549 				uint8_t, bmac_xif_config_t);
550 npi_status_t npi_bmac_tx_iconfig(npi_handle_t, config_op_t,
551 				uint8_t, bmac_tx_iconfig_t);
552 npi_status_t npi_bmac_ctl_iconfig(npi_handle_t, config_op_t,
553 				uint8_t, bmac_ctl_iconfig_t);
554 npi_status_t npi_bmac_tx_get_istatus(npi_handle_t, uint8_t,
555 				bmac_tx_iconfig_t *);
556 npi_status_t npi_bmac_rx_get_istatus(npi_handle_t, uint8_t,
557 				bmac_rx_iconfig_t *);
558 npi_status_t npi_bmac_ctl_get_istatus(npi_handle_t, uint8_t,
559 				bmac_ctl_iconfig_t *);
560 npi_status_t npi_bmac_send_pause(npi_handle_t, uint8_t,
561 				uint16_t);
562 npi_status_t npi_mac_dump_regs(npi_handle_t, uint8_t);
563 
564 /* MIF common functions */
565 void npi_mac_mif_set_indirect_mode(npi_handle_t, boolean_t);
566 void npi_mac_mif_set_atca_mode(npi_handle_t, boolean_t);
567 
568 #ifdef	__cplusplus
569 }
570 #endif
571 
572 #endif	/* _NPI_MAC_H */
573