1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 #ifndef CHELSIO_T1_COMPAT_H
27 #define	CHELSIO_T1_COMPAT_H
28 
29 #ifndef ETH_ALEN
30 #define	ETH_ALEN 6
31 #endif
32 
33 /* MAC and PHY link speeds */
34 enum { SPEED_10, SPEED_100, SPEED_1000, SPEED_10000 };
35 
36 /* MAC and PHY link duplex */
37 enum { DUPLEX_HALF, DUPLEX_FULL };
38 
39 /* Autonegotiation settings */
40 enum { AUTONEG_DISABLE, AUTONEG_ENABLE };
41 
42 #ifndef MII_BMCR
43 
44 /* Generic MII registers and register fields. */
45 #define	MII_BMCR	0x00	/* Basic mode control register	*/
46 #define	MII_BMSR	0x01	/* Basic mode status register	*/
47 #define	MII_PHYSID1	0x02	/* PHYS ID 1			*/
48 #define	MII_PHYSID2	0x03	/* PHYS ID 2			*/
49 #define	MII_ADVERTISE	0x04	/* Advertisement control reg	*/
50 #define	MII_LPA		0x05	/* Link partner ability reg	*/
51 
52 /* Basic mode control register. */
53 #define	BMCR_RESV	0x007f	/* Unused...			*/
54 #define	BMCR_CTST	0x0080	/* Collision test		*/
55 #define	BMCR_FULLDPLX	0x0100	/* Full duplex			*/
56 #define	BMCR_ANRESTART	0x0200	/* Auto negotiation restart	*/
57 #define	BMCR_ISOLATE	0x0400	/* Disconnect DP83840 from MII	*/
58 #define	BMCR_PDOWN	0x0800	/* Powerdown the DP83840	*/
59 #define	BMCR_ANENABLE	0x1000	/* Enable auto negotiation	*/
60 #define	BMCR_SPEED100	0x2000	/* Select 100Mbps		*/
61 #define	BMCR_LOOPBACK	0x4000	/* TXD loopback bits		*/
62 #define	BMCR_RESET	0x8000	/* Reset the DP83840		*/
63 
64 /* Basic mode status register. */
65 #define	BMSR_ERCAP		0x0001	/* Ext-reg capability		*/
66 #define	BMSR_JCD		0x0002	/* Jabber detected		*/
67 #define	BMSR_LSTATUS		0x0004	/* Link status			*/
68 #define	BMSR_ANEGCAPABLE	0x0008	/* Able to do auto-negotiation	*/
69 #define	BMSR_RFAULT		0x0010	/* Remote fault detected	*/
70 #define	BMSR_ANEGCOMPLETE	0x0020	/* Auto-negotiation complete	*/
71 #define	BMSR_RESV		0x07c0	/* Unused...			*/
72 #define	BMSR_10HALF		0x0800	/* Can do 10mbps, half-duplex	*/
73 #define	BMSR_10FULL		0x1000	/* Can do 10mbps, full-duplex	*/
74 #define	BMSR_100HALF		0x2000	/* Can do 100mbps, half-duplex	*/
75 #define	BMSR_100FULL		0x4000	/* Can do 100mbps, full-duplex	*/
76 #define	BMSR_100BASE4		0x8000	/* Can do 100mbps, 4k packets	*/
77 
78 /* Advertisement control register. */
79 #define	ADVERTISE_SLCT		0x001f	/* Selector bits		*/
80 #define	ADVERTISE_CSMA		0x0001	/* Only selector supported	*/
81 #define	ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex	*/
82 #define	ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex	*/
83 #define	ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex	*/
84 #define	ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex	*/
85 #define	ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets	*/
86 #define	ADVERTISE_RESV		0x1c00	/* Unused...			*/
87 #define	ADVERTISE_RFAULT	0x2000	/* Say we can detect faults	*/
88 #define	ADVERTISE_LPACK		0x4000	/* Ack link partners response	*/
89 #define	ADVERTISE_NPAGE		0x8000	/* Next page bit		*/
90 #endif
91 
92 /* MAC and PHY supported features */
93 #define	SUPPORTED_10baseT_Half		(1 << 0)
94 #define	SUPPORTED_10baseT_Full		(1 << 1)
95 #define	SUPPORTED_100baseT_Half		(1 << 2)
96 #define	SUPPORTED_100baseT_Full		(1 << 3)
97 #define	SUPPORTED_1000baseT_Half	(1 << 4)
98 #define	SUPPORTED_1000baseT_Full	(1 << 5)
99 #define	SUPPORTED_10000baseT_Full	(1 << 6)
100 #define	SUPPORTED_Autoneg		(1 << 7)
101 #define	SUPPORTED_TP			(1 << 8)
102 #define	SUPPORTED_FIBRE			(1 << 9)
103 #define	SUPPORTED_PAUSE			(1 << 10)
104 #define	SUPPORTED_LOOPBACK		(1 << 11)
105 
106 /* Features advertised by PHY */
107 #define	ADVERTISED_10baseT_Half		(1 << 0)
108 #define	ADVERTISED_10baseT_Full		(1 << 1)
109 #define	ADVERTISED_100baseT_Half	(1 << 2)
110 #define	ADVERTISED_100baseT_Full	(1 << 3)
111 #define	ADVERTISED_1000baseT_Half	(1 << 4)
112 #define	ADVERTISED_1000baseT_Full	(1 << 5)
113 #define	ADVERTISED_10000baseT_Full	(1 << 6)
114 #define	ADVERTISED_Autoneg		(1 << 7)
115 #define	ADVERTISED_PAUSE		(1 << 10)
116 #define	ADVERTISED_ASYM_PAUSE		(1 << 12)
117 
118 /* diagnostic message categories */
119 enum { LINK = 1, INTR = 2, HW = 4 };
120 
121 /* diagnostic message levels */
122 /* enum { INFO, DEBUG }; */
123 
124 #ifndef __devinit
125 #define	__devinit
126 #endif
127 
128 #ifndef CH_DEVICE
129 struct pci_device_id {
130 	unsigned short devid;
131 	unsigned short ssid;
132 	unsigned short board_info_index;
133 };
134 
135 #define	CH_DEVICE_COMMON(devid, ssid, idx) { devid, ssid, idx }
136 #define	CH_DEVICE(devid, ssid, idx) CH_DEVICE_COMMON(devid, ssid, idx)
137 #endif
138 
139 #endif
140