Lines Matching refs:cpu
50 #define SOCKET_BUS(cpu) (MAX_BUS_NUMBER - (cpu)) argument
51 #define CPU_ID_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0) argument
52 #define MC_CONTROL_RD(cpu) \ argument
53 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0)
54 #define MC_STATUS_RD(cpu) \ argument
55 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0)
56 #define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \ argument
57 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0)
58 #define MC_CPU_RAS_RD(cpu) \ argument
59 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0)
60 #define MC_SCRUB_CONTROL_RD(cpu) \ argument
61 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0)
62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
64 #define MC_SSR_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0) argument
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
67 #define MC_SSR_SCRUB_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \ argument
69 #define MC_RAS_ENABLES_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0) argument
70 #define MC_RAS_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0) argument
71 #define MC_SSR_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0) argument
72 #define MC_CHANNEL_MAPPER_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \ argument
74 #define MC_COR_ECC_CNT_RD(cpu, select) \ argument
75 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0)
76 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \ argument
77 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0)
78 #define MC_DOD_RD(cpu, channel, select) \ argument
79 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0)
80 #define MC_SAG_RD(cpu, channel, select) \ argument
81 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0)
82 #define MC_RIR_LIMIT_RD(cpu, channel, select) \ argument
83 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0)
84 #define MC_RIR_WAY_RD(cpu, channel, select) \ argument
85 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0)
86 #define MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \ argument
87 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0)
88 #define SAD_DRAM_RULE_RD(cpu, rule) \ argument
89 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0)
90 #define SAD_INTERLEAVE_LIST_RD(cpu, rule) \ argument
91 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0)
92 #define TAD_DRAM_RULE_RD(cpu, rule) \ argument
93 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0)
94 #define TAD_INTERLEAVE_LIST_RD(cpu, rule) \ argument
95 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0)
96 #define MC_DIMM_CLK_RATIO_STATUS(cpu) \ argument
97 nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0)