Lines Matching defs:val

745 #define	FERR_GLOBAL_WR(val) \  argument
753 #define NERR_GLOBAL_WR(val) nb_pci_putl(0, 16, 2, 0x44, val) argument
754 #define FERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ argument
757 #define FERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ argument
760 #define NERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ argument
763 #define NERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ argument
766 #define EMASK_FSB_WR(fsb, val) \ argument
774 #define ERR0_FSB_WR(fsb, val) \ argument
782 #define ERR1_FSB_WR(fsb, val) \ argument
790 #define ERR2_FSB_WR(fsb, val) \ argument
798 #define MCERR_FSB_WR(fsb, val) \ argument
853 #define FERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
860 #define FERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
867 #define NERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
874 #define NERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
881 #define EMASK_5000_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val) argument
882 #define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val) argument
883 #define EMASK_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
888 #define ERR0_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
893 #define ERR1_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
898 #define ERR2_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
903 #define MCERR_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ argument
930 #define FERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x98, val) argument
931 #define NERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x9c, val) argument
932 #define FERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa0, val) argument
933 #define NERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa4, val) argument
934 #define EMASK_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa8, val) argument
935 #define ERR0_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xac, val) argument
936 #define ERR1_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb0, val) argument
937 #define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val) argument
938 #define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val) argument
1122 #define FERR_NF_MEM_WR(val) \ argument
1124 #define NERR_NF_MEM_WR(val) \ argument
1126 #define EMASK_MEM_WR(val) \ argument
1128 #define ERR0_MEM_WR(val) \ argument
1130 #define ERR1_MEM_WR(val) \ argument
1132 #define ERR2_MEM_WR(val) \ argument
1134 #define MCERR_MEM_WR(val) \ argument
1166 #define MC_WR(val) nb_pci_putl(0, 16, 1, 0x40, val) argument
1275 #define UERRCNT_WR(branch, val) ((branch) == 0) ? \ argument
1280 #define CERRCNT_WR(branch, val) ((branch) == 0) ? \ argument
1284 #define BADRAMA_WR(branch, val) ((branch) == 0) ? \ argument
1288 #define BADRAMB_WR(branch, val) ((branch) == 0) ? \ argument
1292 #define BADCNT_WR(branch, val) ((branch) == 0) ? \ argument
1308 #define SPDCMD1_1_WR(val) nb_pci_putl(0, 21, 0, 0x7c, val) argument
1309 #define SPDCMD_WR(branch, channel, val) \ argument
1330 #define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val) argument
1331 #define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val) argument
1332 #define PEX_FAT_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x154, val) argument
1333 #define PEX_FAT_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x15c, val) argument
1334 #define PEX_NF_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x158, val) argument
1335 #define PEX_NF_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x160, val) argument
1336 #define PEX_ERR_DOCMD_WR(pex, val) ((nb_chipset == INTEL_NB_5400) ? \ argument
1338 #define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val) argument
1339 #define EMASK_UNCOR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x148, val) argument
1340 #define EMASK_COR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x14c, val) argument
1341 #define EMASK_RP_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x150, val) argument
1355 #define PEX_FAT_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x154, val) argument
1356 #define PEX_FAT_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x15c, val) argument
1357 #define PEX_NF_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x158, val) argument
1358 #define PEX_NF_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x160, val) argument
1359 #define CORERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x110, val) argument
1360 #define UNCERRSEV_WR(pex, val) nb_pci_putl(0, pex, 0, 0x10c, val) argument
1361 #define RPERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x130, val) argument
1362 #define PEXDEVSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x76, val) argument
1363 #define PEXROOTCTL_WR(pex, val) nb_pci_putw(0, pex, 0, 0x88, val) argument
1367 #define PCISTS_WR(val) nb_pci_putw(0, 8, 0, 0x6, val) argument
1368 #define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val) argument
1410 #define FERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf0, val) argument
1411 #define FERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf1, val) argument
1412 #define NERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf2, val) argument
1413 #define NERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf3, val) argument
1414 #define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val) argument
1415 #define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val) argument
1416 #define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val) argument
1417 #define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val) argument
1418 #define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val) argument
1419 #define CTSTS_WR(val) nb_pci_putb(0, 16, 4, 0xee, val) argument
1420 #define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val) argument