Lines Matching refs:uint32_t
106 uint32_t in_param0;
107 uint32_t in_param1;
108 uint32_t input_modifier;
109 uint32_t out_param0;
110 uint32_t out_param1;
111 uint32_t token;
112 uint32_t cmd;
139 uint32_t rsrv0[4];
141 uint32_t log_max_scqs :4;
142 uint32_t :4;
143 uint32_t num_rsvd_scqs :6;
144 uint32_t :2;
145 uint32_t log_max_srq :5;
146 uint32_t :7;
147 uint32_t log_rsvd_srq :4;
149 uint32_t log_max_qp :5;
150 uint32_t :3;
151 uint32_t log_rsvd_qp :4;
152 uint32_t :4;
153 uint32_t log_max_qp_sz :8;
154 uint32_t log_max_srq_sz :8;
156 uint32_t log_max_eq :4;
157 uint32_t :4;
158 uint32_t num_rsvd_eq :4;
159 uint32_t :4;
160 uint32_t log_max_dmpt :6;
161 uint32_t :2;
162 uint32_t log_max_eq_sz :8;
164 uint32_t log_max_cq :5;
165 uint32_t :3;
166 uint32_t log_rsvd_cq :4;
167 uint32_t :4;
168 uint32_t log_max_cq_sz :8;
169 uint32_t :8;
172 uint32_t :32;
174 uint32_t log_max_mtt :6;
175 uint32_t :2;
176 uint32_t log_rsvd_dmpt :4;
177 uint32_t :4;
178 uint32_t log_max_mrw_sz :7;
179 uint32_t :5;
180 uint32_t log_rsvd_mtt :4;
182 uint32_t log_max_ra_glob :6;
183 uint32_t :2;
184 uint32_t log_max_rss_tbl_sz :4;
185 uint32_t rss_toep :1; /* rss toeplitz hashing */
186 uint32_t rss_xor :1; /* rss xor hashing */
187 uint32_t :2;
188 uint32_t log_max_gso_sz :5; /* Lge Send Offload */
189 uint32_t :11; /* new w/ 0.35, RSS info */
191 uint32_t log_max_ra_res_qp :6;
192 uint32_t :10;
193 uint32_t log_max_ra_req_qp :6;
194 uint32_t :10;
196 uint32_t num_ports :4;
197 uint32_t :12;
198 uint32_t ca_ack_delay :5;
199 uint32_t cqmep :3; /* cq moderation policies */
200 uint32_t :4;
201 uint32_t :1;
202 uint32_t :3;
204 uint32_t mod_wr_srq :1; /* resize SRQ supported */
205 uint32_t :31;
207 uint32_t :16;
208 uint32_t stat_rate_sup :16;
210 uint32_t :8;
211 uint32_t :4;
212 uint32_t :4;
213 uint32_t :8;
214 uint32_t log_max_msg :5;
215 uint32_t :3;
217 uint32_t rc :1; /* 0x44 */
218 uint32_t uc :1;
219 uint32_t ud :1;
220 uint32_t xrc :1;
221 uint32_t rcm :1;
222 uint32_t fcoib :1;
223 uint32_t srq :1;
224 uint32_t ipoib_cksm :1;
225 uint32_t pkey_v :1;
226 uint32_t qkey_v :1;
227 uint32_t vmm :1;
228 uint32_t fcoe :1;
229 uint32_t dpdp :1; /* dual port diff protocol */
230 uint32_t raw_etype :1;
231 uint32_t raw_ipv4 :1;
232 uint32_t blh :1; /* big LSO header, bit in WQE */
233 uint32_t mem_win :1;
234 uint32_t apm :1;
235 uint32_t atomic :1;
236 uint32_t raw_multi :1;
237 uint32_t avp :1;
238 uint32_t ud_multi :1;
239 uint32_t udm_ipv4 :1;
240 uint32_t dif :1; /* DIF supported */
241 uint32_t pg_on_demand :1;
242 uint32_t router :1;
243 uint32_t l2mc :1; /* lev 2 enet multicast */
244 uint32_t :1;
245 uint32_t ud_swp :1; /* sw parse for UD xport */
246 uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */
247 uint32_t lle :1; /* low latency enet */
248 uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */
251 uint32_t eth_uc_lb :1; /* enet unicast loopback */
252 uint32_t :3;
253 uint32_t hdr_split :1;
254 uint32_t hdr_lookahead :1;
255 uint32_t :2;
256 uint32_t rss_udp :1;
257 uint32_t :7;
258 uint32_t :16;
260 uint32_t log_max_bf_page :6; /* 0x4c */
261 uint32_t :2;
262 uint32_t log_max_bf_req_ppg :6;
263 uint32_t :2;
264 uint32_t log_bf_reg_sz :5;
265 uint32_t :10;
266 uint32_t blu_flm :1;
268 uint32_t log_pg_sz :8; /* 0x48 */
269 uint32_t :8;
270 uint32_t log_max_uar_sz :6;
271 uint32_t :6;
272 uint32_t num_rsvd_uar :4;
274 uint32_t max_desc_sz_rq :16; /* 0x54 */
275 uint32_t max_sg_rq :8;
276 uint32_t :8;
278 uint32_t max_desc_sz_sq :16; /* 0x50 */
279 uint32_t max_sg_sq :8;
280 uint32_t :8;
283 uint32_t rsvd_fcoib; /* 0x5C */
285 uint32_t :1; /* 0x58 */
286 uint32_t fexch_base_mpt :7; /* FC exch base mpt num */
287 uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */
288 uint32_t fexch_base_qp :8; /* FC exch base qp num */
291 uint32_t log_max_xrcd :5; /* 0x64 */
292 uint32_t :7;
293 uint32_t num_rsvd_xrcds :4;
294 uint32_t log_max_pd :5;
295 uint32_t :7;
296 uint32_t num_rsvd_pd :4;
298 uint32_t log_max_mcg :8; /* 0x60 */
299 uint32_t num_rsvd_mcg :4;
300 uint32_t :4;
301 uint32_t log_max_qp_mcg :8;
302 uint32_t :8;
304 uint32_t rsrv2[6];
306 uint32_t altc_entry_sz :16; /* 0x84 */
307 uint32_t aux_entry_sz :16;
309 uint32_t qpc_entry_sz :16; /* 0x80 */
310 uint32_t rdmardc_entry_sz :16;
312 uint32_t cmpt_entry_sz :16; /* 0x8C */
313 uint32_t srq_entry_sz :16;
315 uint32_t cqc_entry_sz :16; /* 0x88 */
316 uint32_t eqc_entry_sz :16;
318 uint32_t bmme :1; /* 0x94 */
319 uint32_t win_type :1;
320 uint32_t mps :1;
321 uint32_t bl :1;
322 uint32_t zb :1;
323 uint32_t lif :1;
324 uint32_t local_inv :1;
325 uint32_t remote_inv :1;
326 uint32_t :1;
327 uint32_t win_type2 :1;
328 uint32_t reserved_lkey :1;
329 uint32_t fast_reg_wr :1;
330 uint32_t :20;
332 uint32_t dmpt_entry_sz :16; /* 0x90 */
333 uint32_t mtt_entry_sz :16;
335 uint32_t :32;
337 uint32_t rsv_lkey;
341 uint32_t rsrv3[22];
347 uint32_t rsrv0[4];
349 uint32_t log_max_srq_sz :8;
350 uint32_t log_max_qp_sz :8;
351 uint32_t :4;
352 uint32_t log_rsvd_qp :4;
353 uint32_t :3;
354 uint32_t log_max_qp :5;
356 uint32_t log_rsvd_srq :4;
357 uint32_t :7;
358 uint32_t log_max_srq :5;
359 uint32_t :2;
360 uint32_t num_rsvd_scqs :6;
361 uint32_t :4;
362 uint32_t log_max_scqs :4;
364 uint32_t :8;
365 uint32_t log_max_cq_sz :8;
366 uint32_t :4;
367 uint32_t log_rsvd_cq :4;
368 uint32_t :3;
369 uint32_t log_max_cq :5;
371 uint32_t log_max_eq_sz :8;
372 uint32_t :2;
373 uint32_t log_max_dmpt :6;
374 uint32_t :4;
375 uint32_t num_rsvd_eq :4;
376 uint32_t :4;
377 uint32_t log_max_eq :4;
379 uint32_t log_rsvd_mtt :4;
380 uint32_t :5;
381 uint32_t log_max_mrw_sz :7;
382 uint32_t :4;
383 uint32_t log_rsvd_dmpt :4;
384 uint32_t :2;
385 uint32_t log_max_mtt :6;
387 uint32_t :32;
389 uint32_t :10;
390 uint32_t log_max_ra_req_qp :6;
391 uint32_t :10;
392 uint32_t log_max_ra_res_qp :6;
394 uint32_t :11; /* new w/ 0.35, RSS info */
395 uint32_t log_max_gso_sz :5; /* Lge Send Offload */
396 uint32_t :2;
397 uint32_t rss_xor :1; /* rss xor hashing */
398 uint32_t rss_toep :1; /* rss toeplitz hashing */
399 uint32_t log_max_rss_tbl_sz :4;
400 uint32_t :2;
401 uint32_t log_max_ra_glob :6;
403 uint32_t :31;
404 uint32_t mod_wr_srq :1; /* resize SRQ supported */
406 uint32_t :3;
407 uint32_t :1;
408 uint32_t :4;
409 uint32_t cqmep :3; /* cq moderation policies */
410 uint32_t ca_ack_delay :5;
411 uint32_t :12;
412 uint32_t num_ports :4;
414 uint32_t :3;
415 uint32_t log_max_msg :5;
416 uint32_t :8;
417 uint32_t :4;
418 uint32_t :4;
419 uint32_t :8;
421 uint32_t stat_rate_sup :16;
422 uint32_t :16;
424 uint32_t :16; /* 0x40 */
425 uint32_t :7;
426 uint32_t rss_udp :1;
427 uint32_t :2;
428 uint32_t hdr_lookahead :1;
429 uint32_t hdr_split :1;
430 uint32_t :3;
431 uint32_t eth_uc_lb :1; /* enet unicast loopback */
433 uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */
434 uint32_t lle :1; /* low latency enet */
435 uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */
436 uint32_t ud_swp :1; /* sw parse for UD xport */
437 uint32_t :1;
438 uint32_t l2mc :1; /* lev 2 enet multicast */
439 uint32_t router :1;
440 uint32_t pg_on_demand :1;
441 uint32_t dif :1; /* DIF supported */
442 uint32_t udm_ipv4 :1;
443 uint32_t ud_multi :1;
444 uint32_t avp :1;
445 uint32_t raw_multi :1;
446 uint32_t atomic :1;
447 uint32_t apm :1;
448 uint32_t mem_win :1;
449 uint32_t blh :1; /* big LSO header, bit in WQE */
450 uint32_t raw_ipv4 :1;
451 uint32_t raw_etype :1;
452 uint32_t dpdp :1; /* dual port diff protocol */
453 uint32_t fcoe :1;
454 uint32_t vmm :1;
455 uint32_t qkey_v :1;
456 uint32_t pkey_v :1;
457 uint32_t ipoib_cksm :1;
458 uint32_t srq :1;
459 uint32_t fcoib :1;
460 uint32_t rcm :1;
461 uint32_t xrc :1;
462 uint32_t ud :1;
463 uint32_t uc :1;
464 uint32_t rc :1;
466 uint32_t num_rsvd_uar :4; /* 0x48 */
467 uint32_t :6;
468 uint32_t log_max_uar_sz :6;
469 uint32_t :8;
470 uint32_t log_pg_sz :8;
472 uint32_t blu_flm :1; /* 0x4c */
473 uint32_t :10;
474 uint32_t log_bf_reg_sz :5;
475 uint32_t :2;
476 uint32_t log_max_bf_req_ppg :6;
477 uint32_t :2;
478 uint32_t log_max_bf_page :6;
480 uint32_t :8; /* 0x50 */
481 uint32_t max_sg_sq :8;
482 uint32_t max_desc_sz_sq :16;
484 uint32_t :8; /* 0x54 */
485 uint32_t max_sg_rq :8;
486 uint32_t max_desc_sz_rq :16;
489 uint32_t fexch_base_qp :8; /* FC exch base qp num */
490 uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */
491 uint32_t fexch_base_mpt :7; /* FC exch base mpt num */
492 uint32_t :1;
494 uint32_t rsvd_fcoib; /* 0x5C */
496 uint32_t :8; /* 0x60 */
497 uint32_t log_max_qp_mcg :8;
498 uint32_t :4;
499 uint32_t num_rsvd_mcg :4;
500 uint32_t log_max_mcg :8;
502 uint32_t num_rsvd_pd :4; /* 0x64 */
503 uint32_t :7;
504 uint32_t log_max_pd :5;
505 uint32_t num_rsvd_xrcds :4;
506 uint32_t :7;
507 uint32_t log_max_xrcd :5;
509 uint32_t rsrv2[6];
511 uint32_t rdmardc_entry_sz :16; /* 0x80 */
512 uint32_t qpc_entry_sz :16;
514 uint32_t aux_entry_sz :16; /* 0x84 */
515 uint32_t altc_entry_sz :16;
517 uint32_t eqc_entry_sz :16; /* 0x88 */
518 uint32_t cqc_entry_sz :16;
520 uint32_t srq_entry_sz :16; /* 0x8C */
521 uint32_t cmpt_entry_sz :16;
523 uint32_t mtt_entry_sz :16; /* 0x90 */
524 uint32_t dmpt_entry_sz :16;
526 uint32_t :20; /* 0x94 */
527 uint32_t fast_reg_wr :1;
528 uint32_t reserved_lkey :1;
529 uint32_t win_type2 :1;
530 uint32_t :1;
531 uint32_t remote_inv :1;
532 uint32_t local_inv :1;
533 uint32_t lif :1;
534 uint32_t zb :1;
535 uint32_t bl :1;
536 uint32_t mps :1;
537 uint32_t win_type :1;
538 uint32_t bmme :1;
540 uint32_t rsv_lkey;
542 uint32_t :32;
546 uint32_t rsrv3[22];
563 uint32_t fw_rev_minor :16;
564 uint32_t fw_rev_subminor :16;
566 uint32_t fw_rev_major :16;
567 uint32_t fw_pages :16;
569 uint32_t log_max_cmd :8;
570 uint32_t :23;
571 uint32_t dbg_trace :1;
573 uint32_t cmd_intf_rev :16;
574 uint32_t :16;
576 uint32_t fw_day :8;
577 uint32_t fw_month :8;
578 uint32_t fw_year :16;
580 uint32_t :1;
581 uint32_t ccq :1; /* currently not def'd */
582 uint32_t :6;
583 uint32_t fw_sec :8;
584 uint32_t fw_min :8;
585 uint32_t fw_hour :8;
587 uint32_t rsrv0[2];
591 uint32_t :32;
593 uint32_t :30;
594 uint32_t clr_int_bar :2;
598 uint32_t :30;
599 uint32_t err_buf_bar :2;
601 uint32_t error_buf_sz;
605 uint32_t :32;
607 uint32_t :30;
608 uint32_t vf_com_ch_bar :2;
610 uint32_t rsrv2[44];
614 uint32_t fw_pages :16;
615 uint32_t fw_rev_major :16;
617 uint32_t fw_rev_subminor :16;
618 uint32_t fw_rev_minor :16;
620 uint32_t :16;
621 uint32_t cmd_intf_rev :16;
623 uint32_t dbg_trace :1;
624 uint32_t :23;
625 uint32_t log_max_cmd :8;
627 uint32_t fw_hour :8;
628 uint32_t fw_min :8;
629 uint32_t fw_sec :8;
630 uint32_t :6;
631 uint32_t ccq :1; /* currently not def'd */
632 uint32_t :1;
634 uint32_t fw_year :16;
635 uint32_t fw_month :8;
636 uint32_t fw_day :8;
638 uint32_t rsrv1[2];
642 uint32_t clr_int_bar :2;
643 uint32_t :30;
645 uint32_t :32;
649 uint32_t error_buf_sz;
651 uint32_t err_buf_bar :2;
652 uint32_t :30;
656 uint32_t vf_com_ch_bar :2;
657 uint32_t :30;
659 uint32_t :32;
661 uint32_t rsrv2[44];
687 uint32_t rsrv0[4];
689 uint32_t :32;
691 uint32_t :24;
692 uint32_t inta_pin :8;
694 uint32_t vsd_vend_id :16; /* added v35 hermon */
695 uint32_t :16;
697 uint32_t :32;
699 uint32_t vsd[52];
700 uint32_t psid[4];
704 uint32_t rsrv0[4];
706 uint32_t inta_pin :8;
707 uint32_t :24;
709 uint32_t :32;
711 uint32_t :32;
713 uint32_t :16;
714 uint32_t vsd_vend_id :16; /* added v35 hermon */
716 uint32_t vsd[52];
717 uint32_t psid[4];
730 uint32_t :12;
731 uint32_t vaddr_l :20;
733 uint32_t vaddr_h;
735 uint32_t log2sz :5; /* in 4KB pages */
736 uint32_t :7;
737 uint32_t paddr_l :20;
739 uint32_t paddr_h;
743 uint32_t vaddr_h;
745 uint32_t vaddr_l :20;
746 uint32_t :12;
748 uint32_t paddr_h;
750 uint32_t paddr_l :20;
751 uint32_t :7;
752 uint32_t log2sz :5; /* in 4KB pages */
786 uint32_t rsrv0[4];
788 uint32_t log_num_qp :5;
789 uint32_t qpc_baseaddr_l :27;
790 uint32_t qpc_baseaddr_h;
792 uint32_t rsrv1[4];
794 uint32_t log_num_srq :5;
795 uint32_t srqc_baseaddr_l :27;
796 uint32_t srqc_baseaddr_h;
798 uint32_t log_num_cq :5;
799 uint32_t cqc_baseaddr_l :27;
800 uint32_t cqc_baseaddr_h;
802 uint32_t rsrv2[2];
806 uint32_t rsrv3[2];
810 uint32_t rsrv4[2];
812 uint32_t log_num_eq :5;
813 uint32_t eqc_baseaddr_l :27;
814 uint32_t eqc_baseaddr_h;
816 uint32_t rsv5[2];
818 uint32_t log_num_rdmardc :3;
819 uint32_t :2;
820 uint32_t rdmardc_baseaddr_l :27;
821 uint32_t rdmardc_baseaddr_h;
823 uint32_t rsrv6[2];
827 uint32_t rsrv0[4];
829 uint32_t qpc_baseaddr_h;
830 uint32_t qpc_baseaddr_l :27;
831 uint32_t log_num_qp :5;
833 uint32_t rsrv1[4];
835 uint32_t srqc_baseaddr_h;
836 uint32_t srqc_baseaddr_l :27;
837 uint32_t log_num_srq :5;
839 uint32_t cqc_baseaddr_h;
840 uint32_t cqc_baseaddr_l :27;
841 uint32_t log_num_cq :5;
843 uint32_t rsrv2[2];
847 uint32_t rsrv3[2];
851 uint32_t rsrv4[2];
853 uint32_t eqc_baseaddr_h;
854 uint32_t eqc_baseaddr_l :27;
855 uint32_t log_num_eq :5;
857 uint32_t rsv5[2];
859 uint32_t rdmardc_baseaddr_h;
860 uint32_t rdmardc_baseaddr_l :27;
861 uint32_t :2;
862 uint32_t log_num_rdmardc :3;
864 uint32_t rsrv6[2];
875 uint32_t rsrv0[2];
877 uint32_t log_mc_tbl_hash_sz :5;
878 uint32_t :27;
880 uint32_t log_mc_tbl_ent :5;
881 uint32_t :27;
883 uint32_t :32;
885 uint32_t log_mc_tbl_sz :5;
886 uint32_t :19;
887 uint32_t mc_hash_fn :3;
888 uint32_t :5;
894 uint32_t rsrv0[2];
896 uint32_t :27;
897 uint32_t log_mc_tbl_ent :5;
899 uint32_t :27;
900 uint32_t log_mc_tbl_hash_sz :5;
902 uint32_t :5;
903 uint32_t mc_hash_fn :3;
904 uint32_t :19;
905 uint32_t log_mc_tbl_sz :5;
907 uint32_t :32;
917 uint32_t :32;
919 uint32_t log_dmpt_sz :6;
920 uint32_t :2;
921 uint32_t pgfault_rnr_to :5;
922 uint32_t :19;
932 uint32_t :19;
933 uint32_t pgfault_rnr_to :5;
934 uint32_t :2;
935 uint32_t log_dmpt_sz :6;
937 uint32_t :32;
948 uint32_t rsvd0[2];
950 uint32_t :32;
952 uint32_t uar_pg_sz :8;
953 uint32_t log_max_uars :4;
954 uint32_t :20;
956 uint32_t resvd1[4];
960 uint32_t rsvd0[2];
962 uint32_t :20;
963 uint32_t log_max_uars :4;
964 uint32_t uar_pg_sz :8;
966 uint32_t :32;
968 uint32_t resvd1[4];
984 uint32_t :32;
986 uint32_t ccq_base :24;
987 uint32_t log2ccqs :5;
988 uint32_t :2;
989 uint32_t ccq_en :1;
991 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */
995 uint32_t ccq_en :1;
996 uint32_t :2;
997 uint32_t log2ccqs :5;
998 uint32_t ccq_base :24;
1000 uint32_t :32;
1002 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */
1009 uint32_t :32;
1011 uint32_t :24;
1012 uint32_t version :8;
1014 uint32_t :13;
1015 uint32_t log2_cacheline :3;
1016 uint32_t hca_core_clock :16; /* QUERY_HCA only */
1018 uint32_t :32;
1020 uint32_t udav_port_chk :1;
1021 uint32_t big_endian :1;
1022 uint32_t qos :1;
1023 uint32_t chsum_en :1;
1024 uint32_t :12;
1025 uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */
1026 uint32_t cqmp :2; /* cq moderation policy */
1028 uint32_t router_qp :24;
1029 uint32_t :5;
1030 uint32_t ipr2 :1;
1031 uint32_t ipr1 :1;
1032 uint32_t router_en :1;
1034 uint32_t rsrv1[2];
1038 uint32_t rsrv2[8];
1042 uint32_t rsrv3[4];
1046 uint32_t rsrv4[4];
1050 uint32_t rsrv5[36];
1054 uint32_t rsrv6[24]; /* to 0x24C */
1056 uint32_t :32;
1058 uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */
1059 uint32_t :31;
1061 uint32_t rsrv7[42]; /* 0x254 - 0x2FC */
1065 uint32_t version :8;
1066 uint32_t :24;
1068 uint32_t :32;
1070 uint32_t :32;
1072 uint32_t hca_core_clock :16; /* QUERY_HCA only */
1073 uint32_t log2_cacheline :3;
1074 uint32_t :13;
1076 uint32_t router_en :1;
1077 uint32_t ipr1 :1;
1078 uint32_t ipr2 :1;
1079 uint32_t :5;
1080 uint32_t router_qp :24;
1082 uint32_t cqmp :2; /* cq moderation policy */
1083 uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */
1084 uint32_t :12;
1085 uint32_t chsum_en :1;
1086 uint32_t qos :1;
1087 uint32_t big_endian :1;
1088 uint32_t udav_port_chk :1;
1090 uint32_t rsrv1[2];
1094 uint32_t rsrv2[8];
1098 uint32_t rsrv3[4];
1102 uint32_t rsrv4[4];
1106 uint32_t rsrv5[36];
1110 uint32_t rsrv6[24]; /* to 0x24C */
1112 uint32_t :31;
1113 uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */
1115 uint32_t :32;
1117 uint32_t rsrv7[42]; /* 0x254 - 0x2FC */
1164 uint32_t log_max_pkey :4; /* pkey table size */
1165 uint32_t log_max_gid :4; /* max gids / port */
1166 uint32_t ib_port_wid :8;
1171 uint32_t eth_link_spd :4;
1172 uint32_t :4;
1176 uint32_t ib_link_spd :8;
1179 uint32_t eth_mtu :16; /* in bytes */
1183 uint32_t ib_mtu :4;
1184 uint32_t :4;
1191 uint32_t ib_link :1;
1192 uint32_t eth_link :1;
1193 uint32_t :1;
1194 uint32_t vpi :1;
1195 uint32_t :3;
1196 uint32_t link_up :1;
1199 uint32_t :32; /* 0x0C */
1202 uint32_t max_vl :4; /* 0x08 */
1203 uint32_t :4;
1204 uint32_t log_max_mac :4;
1205 uint32_t log_max_vlan :4;
1206 uint32_t :16;
1208 uint32_t mac_lo;
1210 uint32_t mac_hi :16;
1211 uint32_t :16;
1213 uint32_t rsvd1[2];
1219 uint32_t link_up :1;
1220 uint32_t :3;
1221 uint32_t vpi :1;
1222 uint32_t :1;
1228 uint32_t eth_link :1;
1229 uint32_t ib_link :1;
1230 uint32_t :4;
1234 uint32_t ib_mtu :4;
1235 uint32_t eth_mtu :16; /* in bytes */
1241 uint32_t ib_link_spd :8;
1242 uint32_t :4;
1247 uint32_t eth_link_spd :4;
1248 uint32_t ib_port_wid :8;
1249 uint32_t log_max_gid :4; /* max gids / port */
1250 uint32_t log_max_pkey :4; /* pkey table size */
1252 uint32_t :16; /* 0x08 */
1253 uint32_t log_max_vlan :4;
1254 uint32_t log_max_mac :4;
1255 uint32_t :4;
1257 uint32_t max_vl :4;
1259 uint32_t :32; /* 0x0C */
1261 uint32_t :16;
1262 uint32_t mac_hi :16;
1264 uint32_t mac_lo;
1266 uint32_t rsvd1[2];
1283 uint32_t cap_mask;
1285 uint32_t rqk :1; /* reset qkey violation cntr */
1286 uint32_t rcm :1; /* reset capability mask */
1287 uint32_t :2;
1288 uint32_t vl_cap :4;
1289 uint32_t :4;
1290 uint32_t mtu_cap :4;
1291 uint32_t g0 :1; /* set port GUID0 */
1292 uint32_t ng :1; /* set node GUID (all ports) */
1293 uint32_t sig :1; /* set sys image */
1294 uint32_t mg :1; /* change GID table */
1295 uint32_t mp :1; /* change pkey table size */
1296 uint32_t mvc :1; /* change vl_cap */
1297 uint32_t mmc :1; /* change mtu_cap */
1298 uint32_t :9;
1306 uint32_t ingress_sniff_qpn :24;
1307 uint32_t ingress_sniff_mode :1;
1308 uint32_t :7;
1310 uint32_t egress_sniff_qpn :24;
1311 uint32_t egress_sniff_mode :1;
1312 uint32_t :7;
1314 uint32_t :32;
1316 uint32_t max_gid :16; /* valid if noted above */
1317 uint32_t max_pkey :16; /* valid if noted above */
1319 uint32_t rsrd0[500];
1323 uint32_t :9;
1324 uint32_t mmc :1; /* change mtu_cap */
1325 uint32_t mvc :1; /* change vl_cap */
1326 uint32_t mp :1; /* change pkey table size */
1327 uint32_t mg :1; /* change GID table size */
1328 uint32_t sig :1; /* set sys image GUID */
1329 uint32_t ng :1; /* set node GUID (all ports) */
1330 uint32_t g0 :1; /* set port GUID0 */
1331 uint32_t mtu_cap :4;
1332 uint32_t :4;
1333 uint32_t vl_cap :4;
1334 uint32_t :2;
1335 uint32_t rcm :1; /* reset capability mask */
1336 uint32_t rqk :1; /* reset qkey violation cntr */
1338 uint32_t cap_mask;
1346 uint32_t :7;
1347 uint32_t egress_sniff_mode :1;
1348 uint32_t egress_sniff_qpn :24;
1350 uint32_t :7;
1351 uint32_t ingress_sniff_mode :1;
1352 uint32_t ingress_sniff_qpn :24;
1355 uint32_t max_pkey :16; /* valid if noted above */
1356 uint32_t max_gid :16; /* valid if noted above */
1358 uint32_t :32;
1360 uint32_t rsrd0[500];
1385 uint32_t mtu :16;
1386 uint32_t :16;
1388 uint32_t v_mtu :1;
1389 uint32_t v_pprx :1;
1390 uint32_t v_pptx :1;
1391 uint32_t :29;
1393 uint32_t :16;
1394 uint32_t pfcrx :8;
1395 uint32_t :7;
1396 uint32_t pprx :1;
1398 uint32_t :16;
1399 uint32_t pfctx :8;
1400 uint32_t :7;
1401 uint32_t pptx :1;
1403 uint32_t rsvd0[4];
1408 uint32_t :29;
1409 uint32_t v_pptx :1;
1410 uint32_t v_pprx :1;
1411 uint32_t v_mtu :1;
1413 uint32_t :16;
1414 uint32_t mtu :16;
1416 uint32_t pptx :1;
1417 uint32_t :7;
1418 uint32_t pfctx :8;
1419 uint32_t :16;
1421 uint32_t pprx :1;
1422 uint32_t :7;
1423 uint32_t pfcrx :8;
1424 uint32_t :16;
1426 uint32_t rsvd0[4];
1435 uint32_t n_p :2;
1436 uint32_t :6;
1437 uint32_t n_v :3;
1438 uint32_t :5;
1439 uint32_t n_m :4;
1440 uint32_t :12;
1442 uint32_t base_qpn :24;
1443 uint32_t :8;
1445 uint32_t vlan_miss_idx :7;
1446 uint32_t :8;
1447 uint32_t intra_vlan_miss :1;
1448 uint32_t no_vlan_idx :7;
1449 uint32_t :8;
1450 uint32_t intra_no_vlan :1;
1452 uint32_t mac_miss_idx :8;
1453 uint32_t :24;
1455 uint32_t promisc_qpn :24;
1456 uint32_t :7;
1457 uint32_t en_uc_promisc :1;
1459 uint32_t no_vlan_prio :3;
1460 uint32_t :29;
1462 uint32_t :32;
1464 uint32_t def_mcast_qpn :24;
1465 uint32_t :5;
1466 uint32_t mc_by_vlan :1;
1467 uint32_t mc_promisc_mode :2;
1469 uint32_t rsvd0[4];
1474 uint32_t :8;
1475 uint32_t base_qpn :24;
1477 uint32_t :12;
1478 uint32_t n_m :4;
1479 uint32_t :5;
1480 uint32_t n_v :3;
1481 uint32_t :6;
1482 uint32_t n_p :2;
1484 uint32_t :24;
1485 uint32_t mac_miss_idx :8;
1487 uint32_t intra_no_vlan :1;
1488 uint32_t :8;
1489 uint32_t no_vlan_idx :7;
1490 uint32_t intra_vlan_miss :1;
1491 uint32_t :8;
1492 uint32_t vlan_miss_idx :7;
1494 uint32_t :29;
1495 uint32_t no_vlan_prio :3;
1497 uint32_t en_uc_promisc :1;
1498 uint32_t :7;
1499 uint32_t promisc_qpn :24;
1501 uint32_t mc_promisc_mode :2;
1502 uint32_t mc_by_vlan :1;
1503 uint32_t :5;
1504 uint32_t def_mcast_qpn :24;
1506 uint32_t :32;
1508 uint32_t rsvd0[4];
1515 uint32_t mac_lo :32;
1517 uint32_t mac_hi :16;
1518 uint32_t :7;
1519 uint32_t mac_valid :1;
1523 uint32_t mac_valid :1;
1524 uint32_t :7;
1525 uint32_t mac_hi :16;
1527 uint32_t mac_lo :32;
1550 uint32_t vlan_id :12;
1551 uint32_t :18;
1552 uint32_t intra :1;
1553 uint32_t valid :1;
1557 uint32_t valid :1;
1558 uint32_t intra :1;
1559 uint32_t :18;
1560 uint32_t vlan_id :12;
1566 uint32_t rsvd[2];
1571 uint32_t rsvd[2];
1580 uint32_t :32;
1582 uint32_t prio0 :3;
1583 uint32_t :1;
1584 uint32_t prio1 :3;
1585 uint32_t :1;
1586 uint32_t prio2 :3;
1587 uint32_t :1;
1588 uint32_t prio3 :3;
1589 uint32_t :1;
1590 uint32_t prio4 :3;
1591 uint32_t :1;
1592 uint32_t prio5 :3;
1593 uint32_t :1;
1594 uint32_t prio6 :3;
1595 uint32_t :1;
1596 uint32_t prio7 :3;
1597 uint32_t :1;
1599 uint32_t rsvd[2];
1603 uint32_t :1;
1604 uint32_t prio7 :3;
1605 uint32_t :1;
1606 uint32_t prio6 :3;
1607 uint32_t :1;
1608 uint32_t prio5 :3;
1609 uint32_t :1;
1610 uint32_t prio4 :3;
1611 uint32_t :1;
1612 uint32_t prio3 :3;
1613 uint32_t :1;
1614 uint32_t prio2 :3;
1615 uint32_t :1;
1616 uint32_t prio1 :3;
1617 uint32_t :1;
1618 uint32_t prio0 :3;
1620 uint32_t :32;
1622 uint32_t rsvd[2];
1636 uint32_t :32;
1638 uint32_t int_vect :16;
1639 uint32_t min_delay :16;
1643 uint32_t min_delay :16;
1644 uint32_t int_vect :16;
1646 uint32_t :32;
1684 uint32_t :7;
1685 uint32_t bnd_qp :1;
1686 uint32_t qpn :24; /* dw 1, byte 4-7 */
1688 uint32_t :8;
1689 uint32_t reg_win :1;
1690 uint32_t phys_addr :1;
1691 uint32_t lr :1;
1692 uint32_t lw :1;
1693 uint32_t rr :1;
1694 uint32_t rw :1;
1695 uint32_t atomic :1;
1696 uint32_t en_bind :1;
1697 uint32_t atc_req :1;
1698 uint32_t atc_xlat :1;
1699 uint32_t :1;
1700 uint32_t no_snoop :1;
1701 uint32_t :8;
1702 uint32_t status :4; /* dw 0, byte 0-3 */
1704 uint32_t pd :24;
1705 uint32_t ren_inval :1;
1706 uint32_t en_inval :1;
1707 uint32_t net_cache :1;
1708 uint32_t fast_reg_en :1;
1709 uint32_t rem_acc_en :1;
1710 uint32_t w_dif :1;
1711 uint32_t m_dif :1;
1712 uint32_t :1; /* dw 2, byte 0xc-f */
1714 uint32_t mem_key;
1720 uint32_t win_cnt :24;
1721 uint32_t :8; /* dw 9, byte 0x24-27 */
1723 uint32_t lkey; /* dw 8, byte 0x20-23 */
1725 uint32_t mtt_addr_h :8;
1726 uint32_t :24; /* dw 11, byte 0x2c-2f */
1728 uint32_t mtt_rep :4;
1729 uint32_t :17;
1730 uint32_t blk_mode :1;
1731 uint32_t len_b64 :1; /* bit 64 of length */
1732 uint32_t fbo_en :1;
1733 uint32_t :8; /* dw 10, byte 0x28-2b */
1735 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1737 uint32_t :3;
1738 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */
1740 uint32_t mtt_fbo :21;
1741 uint32_t :11; /* dw 15, byte 0x3c-3f */
1743 uint32_t entity_sz :21;
1744 uint32_t :11; /* dw 14, byte 0x38-3b */
1746 uint32_t dif_m_atag :16;
1747 uint32_t :16; /* dw 17, 0x44-47 */
1749 uint32_t dif_a_msk :16;
1750 uint32_t dif_v_msk :2;
1751 uint32_t dif_rep :2;
1752 uint32_t :4;
1753 uint32_t dif_err :3;
1754 uint32_t :5; /* dw 16, 0x40-43 */
1756 uint32_t dif_w_atag :16;
1757 uint32_t :16; /* dw 19, 0x4c-4f */
1759 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */
1761 uint32_t :32;
1763 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */
1765 uint32_t rsvd[10];
1771 uint32_t status :4;
1772 uint32_t :8;
1773 uint32_t no_snoop :1;
1774 uint32_t :1;
1775 uint32_t atc_xlat :1;
1776 uint32_t atc_req :1;
1777 uint32_t en_bind :1;
1778 uint32_t atomic :1;
1779 uint32_t rw :1;
1780 uint32_t rr :1;
1781 uint32_t lw :1;
1782 uint32_t lr :1;
1783 uint32_t phys_addr :1;
1784 uint32_t reg_win :1;
1785 uint32_t :8; /* dw 0, byte 0x0-3 */
1787 uint32_t qpn :24;
1788 uint32_t bnd_qp :1;
1789 uint32_t :7; /* dw 1, byte 0x4-7 */
1791 uint32_t mem_key; /* dw 2, byte 0x8-b */
1793 uint32_t :1;
1794 uint32_t m_dif :1;
1795 uint32_t w_dif :1;
1796 uint32_t rem_acc_en :1;
1797 uint32_t fast_reg_en :1;
1798 uint32_t net_cache :1;
1799 uint32_t en_inval :1;
1800 uint32_t ren_inval :1;
1801 uint32_t pd :24; /* dw 3, byte 0xc-f */
1807 uint32_t lkey; /* dw 8, bytd 0x20-23 */
1809 uint32_t :8;
1810 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */
1812 uint32_t :8;
1813 uint32_t fbo_en :1;
1814 uint32_t len_b64 :1; /* bit 64 of length */
1815 uint32_t blk_mode :1;
1816 uint32_t :17;
1817 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */
1819 uint32_t :24;
1820 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */
1822 uint32_t mtt_addr_l :29;
1823 uint32_t :3; /* dw 12, byte 0x30-33 */
1825 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1827 uint32_t :11;
1828 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */
1830 uint32_t :11;
1831 uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */
1833 uint32_t :5;
1834 uint32_t dif_err :3;
1835 uint32_t :4;
1836 uint32_t dif_rep :2;
1837 uint32_t dif_v_msk :2;
1838 uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */
1840 uint32_t :16;
1841 uint32_t dif_m_atag :16; /* dw 17, 0x44-47 */
1843 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */
1845 uint32_t :16;
1846 uint32_t dif_w_atag :16; /* dw 19, 0x4c-4f */
1848 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */
1850 uint32_t :32;
1852 uint32_t rsvd[10];
1869 uint32_t :7;
1870 uint32_t bnd_qp :1;
1871 uint32_t qpn :24; /* dw 1, byte 4-7 */
1873 uint32_t :8;
1874 uint32_t reg_win :1;
1875 uint32_t phys_addr :1;
1876 uint32_t lr :1;
1877 uint32_t lw :1;
1878 uint32_t rr :1;
1879 uint32_t rw :1;
1880 uint32_t atomic :1;
1881 uint32_t en_bind :1;
1882 uint32_t atc_req :1;
1883 uint32_t atc_xlat :1;
1884 uint32_t :1;
1885 uint32_t no_snoop :1;
1886 uint32_t :8;
1887 uint32_t status :4; /* dw 0, byte 0-3 */
1889 uint32_t pd :24;
1890 uint32_t ren_inval :1;
1891 uint32_t en_inval :1;
1892 uint32_t net_cache :1;
1893 uint32_t fast_reg_en :1;
1894 uint32_t rem_acc_en :1;
1895 uint32_t w_dif :1;
1896 uint32_t m_dif :1;
1897 uint32_t :1; /* dw 2, byte 0xc-f */
1899 uint32_t mem_key;
1904 uint32_t win_cnt :24;
1905 uint32_t :8; /* dw 9, byte 0x24-27 */
1907 uint32_t lkey; /* dw 8, byte 0x20-23 */
1909 uint32_t mtt_addr_h :8;
1910 uint32_t :24; /* dw 11, byte 0x2c-2f */
1912 uint32_t mtt_rep :4;
1913 uint32_t :17;
1914 uint32_t blk_mode :1;
1915 uint32_t len_b64 :1; /* bit 64 of length */
1916 uint32_t fbo_en :1;
1917 uint32_t :8; /* dw 10, byte 0x28-2b */
1919 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1921 uint32_t :3;
1922 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */
1924 uint32_t mtt_fbo :21;
1925 uint32_t :11; /* dw 15, byte 0x3c-3f */
1927 uint32_t entity_sz :21;
1928 uint32_t :11; /* dw 14, byte 0x38-3b */
1935 uint32_t status :4;
1936 uint32_t :8;
1937 uint32_t no_snoop :1;
1938 uint32_t :1;
1939 uint32_t atc_xlat :1;
1940 uint32_t atc_req :1;
1941 uint32_t en_bind :1;
1942 uint32_t atomic :1;
1943 uint32_t rw :1;
1944 uint32_t rr :1;
1945 uint32_t lw :1;
1946 uint32_t lr :1;
1947 uint32_t phys_addr :1;
1948 uint32_t reg_win :1;
1949 uint32_t :8; /* dw 0, byte 0x0-3 */
1951 uint32_t qpn :24;
1952 uint32_t bnd_qp :1;
1953 uint32_t :7; /* dw 1, byte 0x4-7 */
1955 uint32_t mem_key; /* dw 2, byte 0x8-b */
1957 uint32_t :1;
1958 uint32_t m_dif :1;
1959 uint32_t w_dif :1;
1960 uint32_t rem_acc_en :1;
1961 uint32_t fast_reg_en :1;
1962 uint32_t net_cache :1;
1963 uint32_t en_inval :1;
1964 uint32_t ren_inval :1;
1965 uint32_t pd :24; /* dw 3, byte 0xc-f */
1971 uint32_t lkey; /* dw 8, bytd 0x20-23 */
1973 uint32_t :8;
1974 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */
1976 uint32_t :8;
1977 uint32_t fbo_en :1;
1978 uint32_t len_b64 :1; /* bit 64 of length */
1979 uint32_t blk_mode :1;
1980 uint32_t :17;
1981 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */
1983 uint32_t :24;
1984 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */
1986 uint32_t mtt_addr_l :29;
1987 uint32_t :3; /* dw 12, byte 0x30-33 */
1989 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1991 uint32_t :11;
1992 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */
1994 uint32_t :11; /* dw 15, byte 0x3c-3f */
1995 uint32_t mtt_fbo :21;
2028 uint32_t present :1;
2029 uint32_t :2;
2030 uint32_t ptag_l :29;
2032 uint32_t ptag_h;
2036 uint32_t ptag_h;
2038 uint32_t ptag_l :29;
2039 uint32_t :2;
2040 uint32_t present :1;
2083 uint32_t :32;
2085 uint32_t :8;
2086 uint32_t state :4;
2087 uint32_t :5;
2088 uint32_t overrun_ignore :1;
2089 uint32_t ev_coalesc :1;
2090 uint32_t :9;
2091 uint32_t status :4;
2093 uint32_t :24;
2094 uint32_t log_eq_sz :5;
2095 uint32_t :3;
2097 uint32_t :5;
2098 uint32_t pg_offs :7;
2099 uint32_t :20;
2101 uint32_t intr :10;
2102 uint32_t :22;
2104 uint32_t eq_max_cnt :16;
2105 uint32_t eq_period :16;
2107 uint32_t :3;
2108 uint32_t mtt_base_addrl :29;
2110 uint32_t mtt_base_addrh :8;
2111 uint32_t :16;
2112 uint32_t log2_pgsz :6; /* in 4K pages */
2113 uint32_t :2;
2115 uint32_t rsrv0[2];
2117 uint32_t prod_indx :24;
2118 uint32_t :8;
2120 uint32_t cons_indx :24;
2121 uint32_t :8;
2127 uint32_t status :4;
2128 uint32_t :9;
2129 uint32_t ev_coalesc :1;
2130 uint32_t overrun_ignore :1;
2131 uint32_t :5;
2132 uint32_t state :4;
2133 uint32_t :8;
2135 uint32_t :32;
2137 uint32_t :20;
2138 uint32_t pg_offs :7;
2139 uint32_t :5;
2141 uint32_t :3;
2142 uint32_t log_eq_sz :5;
2143 uint32_t :24;
2145 uint32_t eq_period :16;
2146 uint32_t eq_max_cnt :16;
2148 uint32_t :22;
2149 uint32_t intr :10;
2151 uint32_t :2;
2152 uint32_t log2_pgsz :6; /* in 4K pages */
2153 uint32_t :16;
2154 uint32_t mtt_base_addrh :8;
2156 uint32_t mtt_base_addrl :29;
2157 uint32_t :3;
2159 uint32_t rsrv0[2];
2161 uint32_t :8;
2162 uint32_t cons_indx :24;
2164 uint32_t :8;
2165 uint32_t prod_indx :24;
2212 uint32_t :8;
2213 uint32_t cqn :24;
2214 uint32_t rsrv0[5];
2220 uint32_t :8;
2221 uint32_t qpn :24;
2223 uint32_t rsrv0[5];
2228 uint32_t :8;
2229 uint32_t cqn :24;
2231 uint32_t :32;
2233 uint32_t :24;
2234 uint32_t syndrome :8;
2236 uint32_t rsrv0[3];
2243 uint32_t rsrv0[2];
2245 uint32_t :2;
2246 uint32_t port :2;
2247 uint32_t :28;
2249 uint32_t rsrv1[3];
2256 uint32_t rsrv0[3];
2258 uint32_t gpio_ev0;
2260 uint32_t gpio_ev1;
2262 uint32_t :32;
2267 uint32_t :16;
2268 uint32_t token :16;
2270 uint32_t :32;
2272 uint32_t :24;
2273 uint32_t status :8;
2275 uint32_t out_param0;
2277 uint32_t out_param1;
2279 uint32_t :32;
2284 uint32_t rsrv0[2];
2286 uint32_t :24;
2287 uint32_t error_type :8;
2289 uint32_t data;
2291 uint32_t rsrv1[2];
2301 uint32_t :14;
2302 uint32_t port :2;
2303 uint32_t fexch :16; /* fexch number */
2305 uint32_t :32;
2307 uint32_t :24;
2308 uint32_t fcsyndrome :8;
2310 uint32_t rsvd[3];
2317 uint32_t rsrv0[2];
2318 uint32_t :24;
2319 uint32_t fault_type :4;
2320 uint32_t wqv :1;
2321 uint32_t wqe_data :1;
2322 uint32_t rem_loc :1;
2323 uint32_t snd_rcv :1;
2324 uint32_t vaddr_h;
2325 uint32_t vaddr_l;
2326 uint32_t mem_key;
2342 uint32_t :8;
2343 uint32_t event_type :8;
2344 uint32_t :8;
2345 uint32_t event_subtype :8;
2357 uint32_t :24;
2358 uint32_t owner :1;
2359 uint32_t :7;
2389 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_CQNUM_MASK) >> \
2392 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_QPNUM_MASK) >> \
2402 htonl(((uint32_t *)(eqe))[4])
2404 htonl(((uint32_t *)(eqe))[5])
2408 htonl(((uint32_t *)(eqe))[4])
2456 uint32_t :32;
2458 uint32_t :8;
2459 uint32_t state :4;
2460 uint32_t :5;
2461 uint32_t overrun_ignore :1;
2462 uint32_t cqe_coalesc :1;
2463 uint32_t :9;
2464 uint32_t status :4;
2466 uint32_t usr_page :24;
2467 uint32_t log_cq_sz :5;
2468 uint32_t :3;
2470 uint32_t :5;
2471 uint32_t pg_offs :7;
2472 uint32_t :20;
2474 uint32_t c_eqn :9;
2475 uint32_t :23;
2477 uint32_t cq_max_cnt :16;
2478 uint32_t cq_period :16;
2480 uint32_t :3;
2481 uint32_t mtt_base_addl :29;
2483 uint32_t mtt_base_addh :8;
2484 uint32_t :16;
2485 uint32_t log2_pgsz :6;
2486 uint32_t :2;
2488 uint32_t solicit_prod_indx :24;
2489 uint32_t :8;
2491 uint32_t last_notified_indx :24;
2492 uint32_t :8;
2494 uint32_t prod_cntr :24; /* producer counter */
2495 uint32_t :8;
2497 uint32_t cons_cntr :24; /* consumer counter */
2498 uint32_t :8;
2500 uint32_t rsrv0[2];
2502 uint32_t :3;
2503 uint32_t dbr_addrl :29;
2505 uint32_t dbr_addrh;
2511 uint32_t status :4;
2512 uint32_t :9;
2513 uint32_t cqe_coalesc :1;
2514 uint32_t overrun_ignore :1;
2515 uint32_t :5;
2516 uint32_t state :4;
2517 uint32_t :8;
2519 uint32_t :32;
2521 uint32_t :20;
2522 uint32_t pg_offs :7;
2523 uint32_t :5;
2525 uint32_t :3;
2526 uint32_t log_cq_sz :5;
2527 uint32_t usr_page :24;
2529 uint32_t cq_period :16;
2530 uint32_t cq_max_cnt :16;
2532 uint32_t :23;
2533 uint32_t c_eqn :9;
2535 uint32_t :2;
2536 uint32_t log2_pgsz :6;
2537 uint32_t :16;
2538 uint32_t mtt_base_addh :8;
2540 uint32_t mtt_base_addl :29;
2541 uint32_t :3;
2543 uint32_t :8;
2544 uint32_t last_notified_indx :24;
2546 uint32_t :8;
2547 uint32_t solicit_prod_indx :24;
2549 uint32_t :8;
2550 uint32_t cons_cntr :24; /* consumer counter */
2552 uint32_t :8;
2553 uint32_t prod_cntr :24; /* priducer counter */
2555 uint32_t rsrv0[2];
2557 uint32_t dbr_addrh;
2559 uint32_t dbr_addrl :29;
2560 uint32_t :3;
2586 uint32_t dife :1;
2587 uint32_t vlan :2;
2588 uint32_t fl :1;
2589 uint32_t fcrc_sd :1;
2590 uint32_t d2s :1;
2591 uint32_t :2;
2592 uint32_t my_qpn :24;
2594 uint32_t immed_rss_val_key;
2596 uint32_t grh :1;
2597 uint32_t ml_path :7;
2598 uint32_t srq_rqpn :24;
2600 uint32_t sl :4;
2601 uint32_t vid :12;
2602 uint32_t slid :16; /* SMAC 47:32 or SLID */
2604 uint32_t ipoib_status; /* SMAC 31:0 or enet/ipoib/EoIB status */
2606 uint32_t byte_cnt;
2608 uint32_t wqe_cntr :16;
2609 uint32_t checksum :16;
2611 uint32_t :8;
2612 uint32_t :16;
2613 uint32_t owner :1;
2614 uint32_t send_or_recv :1;
2615 uint32_t inline_scatter :1;
2616 uint32_t opcode :5;
2661 htonl((((uint32_t *)(cqe)))[4])
2664 ((htonl((((uint32_t *)(cqe)))[0]) & HERMON_CQE_QPNUM_MASK) >> \
2668 htonl(((uint32_t *)(cqe))[1])
2671 ((htonl(((uint32_t *)(cqe))[2]) & HERMON_CQE_DQPN_MASK) >> \
2688 htonl(((uint32_t *)(cqe))[5])
2711 htonl(((uint32_t *)(cqe))[3])
2714 htonl(((uint32_t *)(cqe))[4])
2720 htonl(((uint32_t *)(cqe))[0])
2738 uint32_t xrc_domain :16;
2739 uint32_t :8;
2740 uint32_t log_rq_stride :3;
2741 uint32_t :5;
2743 uint32_t srqn :24;
2744 uint32_t log_srq_size :4;
2745 uint32_t state :4;
2747 uint32_t :32;
2749 uint32_t cqn_xrc :24;
2750 uint32_t :2;
2751 uint32_t page_offs :6;
2753 uint32_t :3;
2754 uint32_t mtt_base_addrl :29;
2756 uint32_t mtt_base_addrh :8;
2757 uint32_t :16;
2758 uint32_t log2_pgsz :6;
2759 uint32_t :2;
2761 uint32_t wqe_cnt :16;
2762 uint32_t lwm :16;
2764 uint32_t pd :24;
2765 uint32_t :8;
2767 uint32_t :32;
2769 uint32_t srq_wqe_cntr :16;
2770 uint32_t :16;
2772 uint32_t :2;
2773 uint32_t dbr_addrl :30;
2775 uint32_t dbr_addrh;
2777 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */
2782 uint32_t state :4;
2783 uint32_t log_srq_size :4;
2784 uint32_t srqn :24;
2786 uint32_t :5;
2787 uint32_t log_rq_stride :3;
2788 uint32_t :8;
2789 uint32_t xrc_domain :16;
2791 uint32_t page_offs :6;
2792 uint32_t :2;
2793 uint32_t cqn_xrc :24;
2795 uint32_t :32;
2797 uint32_t :2;
2798 uint32_t log2_pgsz :6;
2799 uint32_t :16;
2800 uint32_t mtt_base_addrh :8;
2802 uint32_t mtt_base_addrl :29;
2803 uint32_t :3;
2805 uint32_t :8;
2806 uint32_t pd :24;
2808 uint32_t lwm :16;
2809 uint32_t wqe_cnt :16;
2811 uint32_t :16;
2812 uint32_t srq_wqe_cntr :16;
2814 uint32_t :32;
2816 uint32_t dbr_addrh;
2818 uint32_t dbr_addrl :30;
2819 uint32_t :2;
2821 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */
2832 uint32_t :16;
2833 uint32_t qdr_rx_op :4;
2834 uint32_t :3;
2835 uint32_t qdr_rx_opt_m :1;
2836 uint32_t qdr_tx_op :4;
2837 uint32_t :3;
2838 uint32_t qdr_tx_opt_m :1;
2840 uint32_t log_pg_sz :8;
2841 uint32_t log_pg_sz_m :1;
2842 uint32_t :5;
2843 uint32_t dife :1;
2844 uint32_t dife_m :1;
2845 uint32_t rx_options :4;
2846 uint32_t :3;
2847 uint32_t rx_options_m :1;
2848 uint32_t tx_options :4;
2849 uint32_t :3;
2850 uint32_t tx_options_m :1;
2852 uint32_t lid :16;
2853 uint32_t lid_m :1;
2854 uint32_t :3;
2855 uint32_t port_en :1;
2856 uint32_t port_en_m :1;
2857 uint32_t :10;
2859 uint32_t :32;
2861 uint32_t guid_hi;
2863 uint32_t :31;
2864 uint32_t guid_hi_m :1;
2866 uint32_t guid_lo;
2868 uint32_t :31;
2869 uint32_t guid_lo_m :1;
2871 uint32_t rsvd[4];
2873 uint32_t inbuf_ind_en :3;
2874 uint32_t :1;
2875 uint32_t sd_main :4;
2876 uint32_t :4;
2877 uint32_t sd_equal :4;
2878 uint32_t :4;
2879 uint32_t sd_mux_main :2;
2880 uint32_t :2;
2881 uint32_t mux_eq :2;
2882 uint32_t :2;
2883 uint32_t sigdet_th :3;
2884 uint32_t :1;
2886 uint32_t ob_preemp_pre :5;
2887 uint32_t :3;
2888 uint32_t op_preemp_post :5;
2889 uint32_t :3;
2890 uint32_t ob_preemp_main :5;
2891 uint32_t :3;
2892 uint32_t ob_preemp :5;
2893 uint32_t :2;
2894 uint32_t serdes_m :1;
2896 uint32_t reserved[22];
2898 uint32_t mac_lo :32;
2900 uint32_t mac_hi :16;
2901 uint32_t :15;
2902 uint32_t mac_m :1;
2906 uint32_t tx_options_m :1;
2907 uint32_t :3;
2908 uint32_t tx_options :4;
2909 uint32_t rx_options_m :1;
2910 uint32_t :3;
2911 uint32_t rx_options :4;
2912 uint32_t dife_m :1;
2913 uint32_t dife :1;
2914 uint32_t :5;
2915 uint32_t log_pg_sz_m :1;
2916 uint32_t log_pg_sz :8;
2918 uint32_t qdr_tx_opt_m :1;
2919 uint32_t :3;
2920 uint32_t qdr_tx_op :4;
2921 uint32_t qdr_rx_opt_m :1;
2922 uint32_t :3;
2923 uint32_t qdr_rx_op :4;
2924 uint32_t :16;
2926 uint32_t :32;
2928 uint32_t :10;
2929 uint32_t port_en_m :1;
2930 uint32_t port_en :1;
2931 uint32_t :3;
2932 uint32_t lid_m :1;
2933 uint32_t lid :16;
2935 uint32_t guid_hi_m :1;
2936 uint32_t :31;
2938 uint32_t guid_hi;
2940 uint32_t guid_lo_m :1;
2941 uint32_t :31;
2943 uint32_t guid_lo;
2945 uint32_t rsvd[4];
2947 uint32_t serdes_m :1;
2948 uint32_t :2;
2949 uint32_t ob_preemp :5;
2950 uint32_t :3;
2951 uint32_t ob_preemp_main :5;
2952 uint32_t :3;
2953 uint32_t op_preemp_post :5;
2954 uint32_t :3;
2955 uint32_t ob_preemp_pre :5;
2957 uint32_t :1;
2958 uint32_t sigdet_th :3;
2959 uint32_t :2;
2960 uint32_t mux_eq :2;
2961 uint32_t :2;
2962 uint32_t sd_mux_main :2;
2963 uint32_t :4;
2964 uint32_t sd_equal :4;
2965 uint32_t :4;
2966 uint32_t sd_main :4;
2967 uint32_t :1;
2968 uint32_t inbuf_ind_en :3;
2970 uint32_t reserved[22]; /* get to new enet stuff */
2972 uint32_t mac_m :1;
2973 uint32_t :15;
2974 uint32_t mac_hi :16;
2976 uint32_t mac_lo :32;
2987 uint32_t offset :8;
2988 uint32_t port_num :8;
2989 uint32_t lane_num :4;
2990 uint32_t link_speed :3;
2991 uint32_t auto_neg :1;
2992 uint32_t :8;
2994 uint32_t :8;
2995 uint32_t auto_neg :1;
2996 uint32_t link_speed :3;
2997 uint32_t lane_num :4;
2998 uint32_t port_num :8;
2999 uint32_t offset :8;
3017 uint32_t rlid :16;
3018 uint32_t ml_path :7; /* mlid or SMAC idx */
3019 uint32_t grh :1;
3020 uint32_t :8;
3022 uint32_t pd :24;
3023 uint32_t portnum :2;
3024 uint32_t :5;
3025 uint32_t force_lb :1;
3027 uint32_t flow_label :20;
3028 uint32_t tclass :8;
3029 uint32_t sl :4;
3031 uint32_t hop_limit :8;
3032 uint32_t max_stat_rate :4;
3033 uint32_t :4;
3034 uint32_t mgid_index :7;
3035 uint32_t :9;
3042 uint32_t force_lb :1;
3043 uint32_t :5;
3044 uint32_t portnum :2;
3045 uint32_t pd :24;
3047 uint32_t :8;
3048 uint32_t grh :1;
3049 uint32_t ml_path :7; /* mlid or SMAC idx */
3050 uint32_t rlid :16;
3052 uint32_t :9;
3053 uint32_t mgid_index :7;
3054 uint32_t :4;
3055 uint32_t max_stat_rate :4;
3056 uint32_t hop_limit :8;
3058 uint32_t sl :4;
3059 uint32_t tclass :8;
3060 uint32_t flow_label :20;
3073 uint32_t :16;
3074 uint32_t smac_idx :7;
3075 uint32_t :9;
3077 uint32_t pd :24;
3078 uint32_t portnum :2;
3079 uint32_t :3;
3080 uint32_t cv :1;
3081 uint32_t :1;
3082 uint32_t force_lb :1;
3084 uint32_t flow_label :20;
3085 uint32_t tclass :8;
3086 uint32_t sl :4;
3088 uint32_t hop_limit :8;
3089 uint32_t max_stat_rate :4;
3090 uint32_t :4;
3091 uint32_t mgid_index :7;
3092 uint32_t :9;
3097 uint32_t rsrv[2];
3099 uint32_t dmac_lo;
3101 uint32_t dmac_hi :16;
3102 uint32_t vlan :16;
3106 uint32_t force_lb :1;
3107 uint32_t :1;
3108 uint32_t cv :1;
3109 uint32_t :3;
3110 uint32_t portnum :2;
3111 uint32_t pd :24;
3113 uint32_t :9;
3114 uint32_t smac_idx :7;
3115 uint32_t :16;
3117 uint32_t :9;
3118 uint32_t mgid_index :7;
3119 uint32_t :4;
3120 uint32_t max_stat_rate :4;
3121 uint32_t hop_limit :8;
3123 uint32_t sl :4;
3124 uint32_t tclass :8;
3125 uint32_t flow_label :20;
3130 uint32_t rsrv[2];
3132 uint32_t vlan :16;
3133 uint32_t dmac_hi :16;
3135 uint32_t dmac_low;
3168 uint32_t rlid :16;
3169 uint32_t mlid :7; /* mlid or SMAC idx */
3170 uint32_t grh :1;
3171 uint32_t cntr_idx :8;
3173 uint32_t pkey_indx :7;
3174 uint32_t :22;
3175 uint32_t :1; /* but may be used for enet */
3176 uint32_t cv :1;
3177 uint32_t force_lb :1;
3179 uint32_t flow_label :20;
3180 uint32_t tclass :8;
3181 uint32_t sniff_s_in :1;
3182 uint32_t sniff_s_out :1;
3183 uint32_t sniff_r_in :1;
3184 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3186 uint32_t hop_limit :8;
3187 uint32_t max_stat_rate :4;
3188 uint32_t :4;
3189 uint32_t mgid_index :7;
3190 uint32_t :1;
3191 uint32_t link_type :3;
3192 uint32_t ack_timeout :5;
3197 uint32_t dmac_hi :16;
3198 uint32_t :16;
3200 uint32_t :8; /* but may be used for enet */
3201 uint32_t sp :1;
3202 uint32_t :2;
3203 uint32_t fvl :1;
3204 uint32_t fsip :1;
3205 uint32_t fsm :1;
3206 uint32_t :2;
3207 uint32_t vlan_idx :7;
3208 uint32_t :1;
3209 uint32_t sched_q :8;
3211 uint32_t dmac_lo :32;
3215 uint32_t force_lb :1;
3216 uint32_t cv :1;
3217 uint32_t :1; /* but may be used for enet */
3218 uint32_t :22;
3219 uint32_t pkey_indx :7;
3221 uint32_t cntr_idx :8;
3222 uint32_t grh :1;
3223 uint32_t mlid :7; /* mlid or SMAC idx */
3224 uint32_t rlid :16;
3226 uint32_t ack_timeout :5;
3227 uint32_t link_type :3;
3228 uint32_t :1;
3229 uint32_t mgid_index :7;
3230 uint32_t :4;
3231 uint32_t max_stat_rate :4;
3232 uint32_t hop_limit :8;
3234 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3235 uint32_t sniff_r_in :1;
3236 uint32_t sniff_s_out :1;
3237 uint32_t sniff_s_in :1;
3238 uint32_t tclass :8;
3239 uint32_t flow_label :20;
3244 uint32_t sched_q :8;
3245 uint32_t :1;
3246 uint32_t vlan_idx :7;
3247 uint32_t :2;
3248 uint32_t fsm :1;
3249 uint32_t fsip :1;
3250 uint32_t fvl :1;
3251 uint32_t :2;
3252 uint32_t sp :1;
3253 uint32_t :8; /* but may be used for enet */
3255 uint32_t :16;
3256 uint32_t dmac_hi :16;
3258 uint32_t dmac_lo :32;
3265 uint32_t rlid :16;
3266 uint32_t mlid :7;
3267 uint32_t grh :1;
3268 uint32_t cntr_idx :8;
3270 uint32_t pkey_indx :7;
3271 uint32_t :22;
3272 uint32_t :1; /* but may be used for enet */
3273 uint32_t cv :1;
3274 uint32_t force_lb :1;
3276 uint32_t flow_label :20;
3277 uint32_t tclass :8;
3278 uint32_t sniff_s_in :1;
3279 uint32_t sniff_s_out :1;
3280 uint32_t sniff_r_in :1;
3281 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3283 uint32_t hop_limit :8;
3284 uint32_t max_stat_rate :4;
3285 uint32_t :4;
3286 uint32_t mgid_index :7;
3287 uint32_t :1;
3288 uint32_t link_type :3;
3289 uint32_t ack_timeout :5;
3294 uint32_t base_qpn :24;
3295 uint32_t log2_tbl_sz :4;
3296 uint32_t :4;
3298 uint32_t :8; /* but may be used for enet */
3299 uint32_t sp :1;
3300 uint32_t :2;
3301 uint32_t fvl :1;
3302 uint32_t fsip :1;
3303 uint32_t fsm :1;
3304 uint32_t :2;
3305 uint32_t vlan_idx :7;
3306 uint32_t :1;
3307 uint32_t sched_q :8;
3309 uint32_t :2;
3310 uint32_t tcp_ipv6 :1;
3311 uint32_t ipv6 :1;
3312 uint32_t tcp_ipv4 :1;
3313 uint32_t ipv4 :1;
3314 uint32_t :2;
3315 uint32_t hash_fn :2;
3316 uint32_t :22;
3318 uint32_t default_qpn :24;
3319 uint32_t :8;
3325 uint32_t force_lb :1;
3326 uint32_t cv :1;
3327 uint32_t :1; /* but may be used for enet */
3328 uint32_t :22;
3329 uint32_t pkey_indx :7;
3331 uint32_t cntr_idx :8;
3332 uint32_t grh :1;
3333 uint32_t mlid :7;
3334 uint32_t rlid :16;
3336 uint32_t ack_timeout :5;
3337 uint32_t link_type :3;
3338 uint32_t :1;
3339 uint32_t mgid_index :7;
3340 uint32_t :4;
3341 uint32_t max_stat_rate :4;
3342 uint32_t hop_limit :8;
3344 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3345 uint32_t sniff_r_in :1;
3346 uint32_t sniff_s_out :1;
3347 uint32_t sniff_s_in :1;
3348 uint32_t tclass :8;
3349 uint32_t flow_label :20;
3354 uint32_t sched_q :8;
3355 uint32_t :1;
3356 uint32_t vlan_idx :7;
3357 uint32_t :2;
3358 uint32_t fsm :1;
3359 uint32_t fsip :1;
3360 uint32_t fvl :1;
3361 uint32_t :2;
3362 uint32_t sp :1;
3363 uint32_t :8; /* but may be used for enet */
3365 uint32_t :4;
3366 uint32_t log2_tbl_sz :4;
3367 uint32_t base_qpn :24;
3369 uint32_t :8;
3370 uint32_t default_qpn :24;
3372 uint32_t :22;
3373 uint32_t hash_fn :2;
3374 uint32_t :2;
3375 uint32_t ipv4 :1;
3376 uint32_t tcp_ipv4 :1;
3377 uint32_t ipv6 :1;
3378 uint32_t tcp_ipv6 :1;
3379 uint32_t :2;
3394 uint32_t pd :24;
3395 uint32_t :8;
3397 uint32_t :11;
3398 uint32_t pm_state :2;
3399 uint32_t rss :1;
3400 uint32_t :2;
3401 uint32_t serv_type :8;
3402 uint32_t :4;
3403 uint32_t state :4;
3405 uint32_t usr_page :24;
3406 uint32_t :8;
3408 uint32_t :4;
3409 uint32_t rlky :1;
3410 uint32_t :3;
3411 uint32_t log_sq_stride :3;
3412 uint32_t log_sq_size :4;
3413 uint32_t sq_no_prefetch :1;
3414 uint32_t log_rq_stride :3;
3415 uint32_t log_rq_size :4;
3416 uint32_t :1;
3417 uint32_t msg_max :5;
3418 uint32_t mtu :3;
3420 uint32_t rem_qpn :24;
3421 uint32_t :8;
3423 uint32_t loc_qpn :24;
3424 uint32_t :8;
3430 uint32_t :32;
3432 uint32_t :5;
3433 uint32_t cur_retry_cnt :3;
3434 uint32_t cur_rnr_retry :3;
3435 uint32_t fre :1;
3436 uint32_t :1;
3437 uint32_t rnr_retry :3;
3438 uint32_t retry_cnt :3;
3439 uint32_t :2;
3440 uint32_t sra_max :3;
3441 uint32_t :4;
3442 uint32_t ack_req_freq :4;
3444 uint32_t cqn_snd :24;
3445 uint32_t :8;
3447 uint32_t next_snd_psn :24;
3448 uint32_t :8;
3450 uint32_t :32;
3452 uint32_t :32;
3454 uint32_t ssn :24;
3455 uint32_t :8;
3457 uint32_t last_acked_psn :24;
3458 uint32_t :8;
3460 uint32_t next_rcv_psn :24;
3461 uint32_t min_rnr_nak :5;
3462 uint32_t :3;
3464 uint32_t :4;
3465 uint32_t ric :1;
3466 uint32_t :1;
3467 uint32_t page_offs :6;
3468 uint32_t :1;
3469 uint32_t rae :1;
3470 uint32_t rwe :1;
3471 uint32_t rre :1;
3472 uint32_t :5;
3473 uint32_t rra_max :3;
3474 uint32_t :8;
3476 uint32_t cqn_rcv :24;
3477 uint32_t :8;
3479 uint32_t xrcd :16;
3480 uint32_t :16;
3482 uint32_t :2;
3483 uint32_t dbr_addrl :30;
3485 uint32_t dbr_addrh :32;
3487 uint32_t srq_number :24;
3488 uint32_t srq_en :1;
3489 uint32_t :7;
3491 uint32_t qkey;
3493 uint32_t sq_wqe_counter :16;
3494 uint32_t rq_wqe_counter :16;
3496 uint32_t rmsn :24;
3497 uint32_t :8;
3499 uint32_t rsrv0[2];
3503 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */
3504 uint32_t num_rmc_peers :8;
3506 uint32_t rmc_parent_qpn :24;
3507 uint32_t header_sep :1;
3508 uint32_t inline_scatter :1; /* m/b 0 for srq */
3509 uint32_t :1;
3510 uint32_t rmc_enable :2;
3511 uint32_t :2; /* may use one bit for enet */
3512 uint32_t mkey_remap :1;
3514 uint32_t :3;
3515 uint32_t mtt_base_addrl :29;
3517 uint32_t mtt_base_addrh :8;
3518 uint32_t :16;
3519 uint32_t log2_pgsz :6;
3520 uint32_t :2;
3522 uint32_t exch_base :16;
3523 uint32_t exch_size :4;
3524 uint32_t :12;
3526 uint32_t vft_vf_id :12;
3527 uint32_t vft_prior :3;
3528 uint32_t :16;
3529 uint32_t ve :1;
3531 uint32_t :32;
3533 uint32_t :16;
3534 uint32_t my_fc_id_idx :8;
3535 uint32_t vft_hop_cnt :8;
3537 uint32_t rsvd[8];
3541 uint32_t state :4;
3542 uint32_t :4;
3543 uint32_t serv_type :8;
3544 uint32_t :2;
3545 uint32_t rss :1;
3546 uint32_t pm_state :2;
3547 uint32_t :11;
3549 uint32_t :8;
3550 uint32_t pd :24;
3552 uint32_t mtu :3;
3553 uint32_t msg_max :5;
3554 uint32_t :1;
3555 uint32_t log_rq_size :4;
3556 uint32_t log_rq_stride :3;
3557 uint32_t sq_no_prefetch :1;
3558 uint32_t log_sq_size :4;
3559 uint32_t log_sq_stride :3;
3560 uint32_t :3;
3561 uint32_t rlky :1;
3562 uint32_t :4;
3564 uint32_t :8;
3565 uint32_t usr_page :24;
3567 uint32_t :8;
3568 uint32_t loc_qpn :24;
3570 uint32_t :8;
3571 uint32_t rem_qpn :24;
3577 uint32_t ack_req_freq :4;
3578 uint32_t :4;
3579 uint32_t sra_max :3;
3580 uint32_t :2;
3581 uint32_t retry_cnt :3;
3582 uint32_t rnr_retry :3;
3583 uint32_t :1;
3584 uint32_t fre :1;
3585 uint32_t cur_rnr_retry :3;
3586 uint32_t cur_retry_cnt :3;
3587 uint32_t :5;
3589 uint32_t :32;
3591 uint32_t :8;
3592 uint32_t next_snd_psn :24;
3594 uint32_t :8;
3595 uint32_t cqn_snd :24;
3597 uint32_t :32;
3599 uint32_t :32;
3601 uint32_t :8;
3602 uint32_t last_acked_psn :24;
3604 uint32_t :8;
3605 uint32_t ssn :24;
3607 uint32_t :8;
3608 uint32_t rra_max :3;
3609 uint32_t :5;
3610 uint32_t rre :1;
3611 uint32_t rwe :1;
3612 uint32_t rae :1;
3613 uint32_t :1;
3614 uint32_t page_offs :6;
3615 uint32_t :1;
3616 uint32_t ric :1;
3617 uint32_t :4;
3619 uint32_t :3;
3620 uint32_t min_rnr_nak :5;
3621 uint32_t next_rcv_psn :24;
3623 uint32_t :16;
3624 uint32_t xrcd :16;
3626 uint32_t :8;
3627 uint32_t cqn_rcv :24;
3629 uint32_t dbr_addrh :32;
3631 uint32_t dbr_addrl :30;
3632 uint32_t :2;
3634 uint32_t qkey;
3636 uint32_t :7;
3637 uint32_t srq_en :1;
3638 uint32_t srq_number :24;
3640 uint32_t :8;
3641 uint32_t rmsn :24;
3643 uint32_t rq_wqe_counter :16;
3644 uint32_t sq_wqe_counter :16;
3646 uint32_t rsrv0[2];
3650 uint32_t mkey_remap :1;
3651 uint32_t :2; /* may use one bit for enet */
3652 uint32_t rmc_enable :2;
3653 uint32_t :1;
3654 uint32_t inline_scatter :1; /* m/b 0 for srq */
3655 uint32_t header_sep :1;
3656 uint32_t rmc_parent_qpn :24;
3658 uint32_t num_rmc_peers :8;
3659 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */
3661 uint32_t :2;
3662 uint32_t log2_pgsz :6;
3663 uint32_t :16;
3664 uint32_t mtt_base_addrh :8;
3666 uint32_t mtt_base_addrl :29;
3667 uint32_t :3;
3669 uint32_t ve :1;
3670 uint32_t :16;
3671 uint32_t vft_prior :3;
3672 uint32_t vft_vf_id :12;
3674 uint32_t :12;
3675 uint32_t exch_size :4;
3676 uint32_t exch_base :16;
3678 uint32_t vft_hop_cnt :8;
3679 uint32_t my_fc_id_idx :8;
3680 uint32_t :16;
3682 uint32_t :32;
3684 uint32_t rsvd[8];
3755 uint32_t member_cnt :24;
3756 uint32_t :6;
3757 uint32_t protocol :2;
3759 uint32_t :6;
3760 uint32_t next_gid_indx :26;
3762 uint32_t :32;
3763 uint32_t :32;
3770 uint32_t next_gid_indx :26;
3771 uint32_t :6;
3773 uint32_t protocol :2;
3774 uint32_t :6;
3775 uint32_t member_cnt :24;
3777 uint32_t :32;
3778 uint32_t :32;
3787 uint32_t member_cnt :24;
3788 uint32_t :6;
3789 uint32_t protocol :2;
3791 uint32_t :6;
3792 uint32_t next_gid_indx :26;
3794 uint32_t :32;
3795 uint32_t :32;
3797 uint32_t vlan_present :1;
3798 uint32_t :31;
3800 uint32_t :32;
3802 uint32_t mac_lo :32;
3804 uint32_t mac_hi :16;
3805 uint32_t vlan_id :12;
3806 uint32_t vlan_cfi :1;
3807 uint32_t vlan_prior :3;
3812 uint32_t next_gid_indx :26;
3813 uint32_t :6;
3815 uint32_t protocol :2;
3816 uint32_t :6;
3817 uint32_t member_cnt :24;
3819 uint32_t :32;
3820 uint32_t :32;
3822 uint32_t :32;
3824 uint32_t :31;
3825 uint32_t vlan_present :1;
3827 uint32_t vlan_prior :3;
3828 uint32_t vlan_cfi :1;
3829 uint32_t vlan_id :12;
3830 uint32_t mac_hi :16;
3832 uint32_t mac_lo :32;
3841 uint32_t qpn :24;
3842 uint32_t :6;
3843 uint32_t blk_lb :1;
3844 uint32_t :1;
3848 uint32_t :1;
3849 uint32_t blk_lb :1;
3850 uint32_t :6;
3851 uint32_t qpn :24;
3864 uint32_t mac_lo;
3866 uint32_t mac_hi :16;
3867 uint32_t :15;
3868 uint32_t sfs :1;
3872 uint32_t sfs :1;
3873 uint32_t :15;
3874 uint32_t mac_hi :16;
3876 uint32_t mac_lo;
3894 uint32_t n_p :2;
3895 uint32_t :6;
3896 uint32_t n_v :3;
3897 uint32_t :5;
3898 uint32_t n_m :4;
3899 uint32_t :12;
3901 uint32_t :16;
3902 uint32_t fexch_base_hi :8;
3903 uint32_t :8;
3905 uint32_t rfci_base :24;
3906 uint32_t log2_num_rfci :3;
3907 uint32_t :5;
3909 uint32_t fx_base_mpt_lo :8;
3910 uint32_t :17;
3911 uint32_t fx_base_mpt_hi :7;
3913 uint32_t fcoe_prom_qpn :24;
3914 uint32_t uint32_t :8; member
3916 uint32_t :32;
3918 uint32_t rsrv[58];
3922 uint32_t :8;
3923 uint32_t fexch_base_hi :8;
3924 uint32_t :16;
3926 uint32_t :12;
3927 uint32_t n_m :4;
3928 uint32_t :5;
3929 uint32_t n_v :3;
3930 uint32_t :6;
3931 uint32_t n_p :2;
3933 uint32_t fx_base_mpt_hi :7;
3934 uint32_t :17;
3935 uint32_t fx_base_mpt_lo :8;
3937 uint32_t :5;
3938 uint32_t log2_num_rfci :3;
3939 uint32_t rfci_base :24;
3941 uint32_t :32;
3943 uint32_t uint32_t :8; member
3944 uint32_t fcoe_prom_qpn :24;
3946 uint32_t rsrv[58];
3957 uint32_t :32;
3959 uint32_t log2_max_rfci :3;
3960 uint32_t :5;
3961 uint32_t log2_max_fexch :5;
3962 uint32_t :3;
3963 uint32_t log2_max_nports :3;
3964 uint32_t :13;
3966 uint32_t rsrv[62];
3970 uint32_t :13;
3971 uint32_t log2_max_nports :3;
3972 uint32_t :3;
3973 uint32_t log2_max_fexch :5;
3974 uint32_t :5;
3975 uint32_t log2_max_rfci :3;
3977 uint32_t :32;
3979 uint32_t rsrv[62];
3989 uint32_t lwm :16;
3990 uint32_t :16;
3992 uint32_t :32;
3996 uint32_t :32;
3998 uint32_t :16;
3999 uint32_t lwm :16;
4009 uint32_t linkdown :8;
4010 uint32_t linkerrrec :8;
4011 uint32_t symerr :16;
4013 uint32_t cntrsel :16;
4014 uint32_t portsel :8;
4015 uint32_t :8;
4017 uint32_t portxmdiscard :16;
4018 uint32_t portrcvswrelay :16;
4020 uint32_t portrcvrem :16;
4021 uint32_t portrcv :16;
4023 uint32_t vl15drop :16;
4024 uint32_t :16;
4026 uint32_t xsbuffovrun :4;
4027 uint32_t locallinkint :4;
4028 uint32_t :8;
4029 uint32_t portrcconstr :8;
4030 uint32_t portxmconstr :8;
4032 uint32_t portrcdata;
4034 uint32_t portxmdata;
4036 uint32_t portrcpkts;
4038 uint32_t portxmpkts;
4040 uint32_t reserved;
4042 uint32_t portxmwait;
4046 uint32_t :8;
4047 uint32_t portsel :8;
4048 uint32_t cntrsel :16;
4050 uint32_t symerr :16;
4051 uint32_t linkerrrec :8;
4052 uint32_t linkdown :8;
4054 uint32_t portrcv :16;
4055 uint32_t portrcvrem :16;
4057 uint32_t portrcvswrelay :16;
4058 uint32_t portxmdiscard :16;
4060 uint32_t portxmconstr :8;
4061 uint32_t portrcconstr :8;
4062 uint32_t :8;
4063 uint32_t locallinkint :4;
4064 uint32_t xsbuffovrun :4;
4066 uint32_t :16;
4067 uint32_t vl15drop :16;
4069 uint32_t portxmdata;
4071 uint32_t portrcdata;
4073 uint32_t portxmpkts;
4075 uint32_t portrcpkts;
4077 uint32_t portxmwait;
4079 uint32_t reserved;
4089 uint32_t rsvd;
4090 uint32_t cntrsel :16;
4091 uint32_t portsel :8;
4092 uint32_t :8;
4112 uint32_t :8;
4113 uint32_t portsel :8;
4114 uint32_t cntrsel :16;
4115 uint32_t rsvd;
4189 uint32_t :32;
4191 uint32_t snd_q_num :24;
4192 uint32_t :8;
4204 uint32_t :2;
4205 uint32_t cmd_sn :2;
4206 uint32_t :2;
4207 uint32_t cmd :2;
4208 uint32_t cqn :24;
4210 uint32_t :8;
4212 uint32_t cq_ci :24;
4226 uint32_t armed :1;
4227 uint32_t :7;
4228 uint32_t guestos_ci :24;
4230 uint32_t :32;
4239 uint32_t rsrv0[4];
4243 uint32_t rsrv1[2];
4247 uint32_t rsrv2[502]; /* next is at offset 0x800 */
4254 uint32_t rsrv3[504]; /* end of page */
4265 uint32_t :16;
4266 uint32_t rcv_wqe_cntr :16; /* wqe_counter */
4268 uint32_t :32;
4277 uint32_t :8;
4278 uint32_t update_ci :24;
4280 uint32_t :2;
4282 uint32_t cmd_sn :2;
4283 uint32_t :1;
4284 uint32_t cmd :3; /* command */
4285 uint32_t cq_ci :24;
4336 uint32_t owner :1;
4337 uint32_t :1;
4338 uint32_t nec :1;
4339 uint32_t :5;
4340 uint32_t fceof :8;
4341 uint32_t :9;
4342 uint32_t rr :1;
4343 uint32_t :1;
4344 uint32_t opcode :5;
4346 uint32_t vlan :16;
4347 uint32_t :1;
4348 uint32_t cv :1;
4349 uint32_t :7;
4350 uint32_t fence :1;
4351 uint32_t ds :6; /* WQE size in octowords */
4357 uint32_t xrc_rem_buf :24;
4358 uint32_t so :1;
4359 uint32_t fcrc :1; /* fc crc calc */
4360 uint32_t tcp_udp :1; /* Checksumming */
4361 uint32_t ip :1; /* Checksumming */
4362 uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */
4364 uint32_t s :1;
4365 uint32_t force_lb :1;
4370 uint32_t immediate :32;
4374 uint32_t :16;
4375 uint32_t next_wqe_idx :16;
4377 uint32_t rsvd[3];
4382 uint32_t owner :1;
4383 uint32_t :1;
4384 uint32_t nec :1;
4385 uint32_t :24;
4386 uint32_t opcode :5;
4388 uint32_t :24;
4389 uint32_t sit :1;
4390 uint32_t :1;
4391 uint32_t ds :6;
4393 uint32_t seq_id :8;
4394 uint32_t info :4;
4395 uint32_t :3;
4396 uint32_t ls :1;
4397 uint32_t :8;
4398 uint32_t so :1;
4399 uint32_t :3;
4400 uint32_t cq_gen :2;
4401 uint32_t :2;
4403 uint32_t param :32;
4407 uint32_t :8;
4408 uint32_t pe :1;
4409 uint32_t :23;
4411 uint32_t csctl_prior :8;
4412 uint32_t seqid_tx :8;
4413 uint32_t :6;
4414 uint32_t mtu :10;
4416 uint32_t rem_id :24;
4417 uint32_t abort :2;
4418 uint32_t :1;
4419 uint32_t op :2;
4420 uint32_t :1;
4421 uint32_t org :1;
4422 uint32_t :1;
4424 uint32_t rem_exch :16;
4425 uint32_t loc_exch_idx :16;
4429 uint32_t :4;
4430 uint32_t stat_rate :4;
4431 uint32_t :24;
4433 uint32_t :32;
4435 uint32_t :16;
4436 uint32_t dmac_hi :16;
4438 uint32_t dmac_lo :32;
4442 uint32_t :32;
4444 uint32_t :8;
4445 uint32_t grh :1;
4446 uint32_t :7;
4447 uint32_t rlid :16;
4449 uint32_t :20;
4450 uint32_t stat_rate :4;
4451 uint32_t hop_limit :8;
4453 uint32_t sl :4;
4454 uint32_t tclass :8;
4455 uint32_t flow_label :20;
4461 uint32_t :8;
4462 uint32_t rqp :24;
4464 uint32_t rsrv[3];
4501 uint32_t :8;
4502 uint32_t dest_qp :24;
4504 uint32_t qkey :32;
4506 uint32_t vlan :16;
4507 uint32_t dmac_hi :16;
4509 uint32_t dmac_lo :32;
4515 uint32_t ae :1;
4516 uint32_t rw :1;
4517 uint32_t rr :1;
4518 uint32_t :3;
4519 uint32_t l_64 :1;
4520 uint32_t :25;
4522 uint32_t win_t :1;
4523 uint32_t z_base :1;
4524 uint32_t :30;
4526 uint32_t new_rkey;
4527 uint32_t reg_lkey;
4536 uint32_t mss :16;
4537 uint32_t :6;
4538 uint32_t hdr_size :10;
4543 uint32_t rkey;
4544 uint32_t :32;
4560 uint32_t :6;
4561 uint32_t atc_shoot :1;
4562 uint32_t :25;
4564 uint32_t :32;
4566 uint32_t mkey;
4568 uint32_t rsrv0;
4570 uint32_t rsrv1;
4571 uint32_t :25;
4572 uint32_t guest_id :7; /* for atc shootdown */
4574 uint32_t p_addrh;
4575 uint32_t p_addrl :23;
4576 uint32_t :9;
4582 uint32_t rkey;
4583 uint32_t rsrv;
4588 uint32_t rem_atomic :1;
4589 uint32_t rem_write :1;
4590 uint32_t rem_read :1;
4591 uint32_t loc_write :1;
4592 uint32_t loc_read :1;
4593 uint32_t fbo_en :1;
4594 uint32_t len_64 :1;
4595 uint32_t :2;
4596 uint32_t dif :1; /* FCoIB */
4597 uint32_t bind_en :1;
4598 uint32_t blk_pg_mode :1;
4599 uint32_t mtt_rep :4;
4600 uint32_t :16;
4602 uint32_t mkey; /* swapped w/ addrh relative to arbel */
4610 uint32_t :11;
4611 uint32_t fbo :21;
4613 uint32_t :11;
4614 uint32_t pge_blk_sz :21;
4616 uint32_t rsrv0[2];
4620 uint32_t dif_in_mem :1;
4621 uint32_t dif_on_wire :1;
4622 uint32_t valid_ref :1;
4623 uint32_t valid_crc :1;
4624 uint32_t repl_ref_tag :1;
4625 uint32_t repl_app_tag :1;
4626 uint32_t :10;
4627 uint32_t app_mask :16;
4629 uint32_t wire_app_tag :16;
4630 uint32_t mem_app_tag :16;
4632 uint32_t wire_ref_tag_base;
4634 uint32_t mem_ref_tag_base;
4653 uint32_t owner :1;
4654 uint32_t :23;
4655 uint32_t :3;
4656 uint32_t opcode :5; /* is 0x0A (send) for MLX */
4658 uint32_t :26;
4659 uint32_t ds :6; /* WQE size in octowords */
4661 uint32_t :14;
4662 uint32_t vl15 :1;
4663 uint32_t slr :1;
4664 uint32_t max_srate :4;
4665 uint32_t sl :4;
4666 uint32_t :3; /* FCoIB usage */
4667 uint32_t icrc :1; /* 1==don't replace icrc fld */
4668 uint32_t cq_gen :2; /* 00= no cqe, 11==cqe */
4669 uint32_t :1;
4670 uint32_t force_lb :1;
4672 uint32_t rlid :16;
4673 uint32_t :16;
4699 uint32_t inline_data :1;
4700 uint32_t byte_cnt :31;
4702 uint32_t lkey;
4783 *(uint32_t *)(ds) = htonl(((mss) << 16) | hdr_sz);
4841 ((uint32_t *)frwr64)[0] = htonl(0x08000000 | \
4849 ((uint32_t *)frwr64)[1] = htonl(lkey); \
4853 ((uint32_t *)frwr64)[8] = htonl(pmr->pmr_offset); \
4854 ((uint32_t *)frwr64)[9] = htonl(pmr->pmr_buf_sz); \
4863 ((uint32_t *)li64)[2] = htonl((wr_li)->li_rkey); \
4864 ((uint32_t *)li64)[3] = 0; \
4872 uint32_t *fc_init; \
4874 fc_init = (uint32_t *)ds; \
4896 ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \
4898 ((uint32_t *)(ds))[0] = \
4903 *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz))
4907 uint32_t *tmp; \
4909 tmp = (uint32_t *)(ds); \
4918 uint32_t *tmp; \
4919 uint32_t cntr_tmp; \
4922 tmp = (uint32_t *)desc; \
4933 uint32_t *tmp; \
4934 uint32_t cntr_tmp; \
4936 tmp = (uint32_t *)desc; \
4953 uint32_t *tmp; \
4954 uint32_t lrh_tmp; \
4956 tmp = (uint32_t *)(void *)(lrh); \
4989 uint32_t *tmp; \
4990 uint32_t grh_tmp; \
4993 tmp = (uint32_t *)(grh); \
5015 uint32_t *tmp; \
5016 uint32_t bth_tmp; \
5018 tmp = (uint32_t *)(bth); \
5038 uint32_t *tmp; \
5040 tmp = (uint32_t *)(deth); \