Lines Matching refs:ring
607 tx_ring_t *ring; in nxge_tdc_lp_conf() local
614 ring = nxge->tx_rings->rings[channel]; in nxge_tdc_lp_conf()
616 if (ring->hv_set) { in nxge_tdc_lp_conf()
631 ring->hv_tx_buf_base_ioaddr_pp = (uint64_t)data->orig_ioaddr_pp; in nxge_tdc_lp_conf()
632 ring->hv_tx_buf_ioaddr_size = (uint64_t)data->orig_alength; in nxge_tdc_lp_conf()
636 ring->hv_tx_buf_base_ioaddr_pp, in nxge_tdc_lp_conf()
637 ring->hv_tx_buf_ioaddr_size); in nxge_tdc_lp_conf()
645 ring->hv_tx_buf_base_ioaddr_pp, in nxge_tdc_lp_conf()
646 ring->hv_tx_buf_ioaddr_size)); in nxge_tdc_lp_conf()
659 channel, hv_rv, ring->hv_tx_buf_base_ioaddr_pp, in nxge_tdc_lp_conf()
660 ring->hv_tx_buf_ioaddr_size, ra, size)); in nxge_tdc_lp_conf()
666 ring->hv_tx_cntl_base_ioaddr_pp = (uint64_t)control->orig_ioaddr_pp; in nxge_tdc_lp_conf()
667 ring->hv_tx_cntl_ioaddr_size = (uint64_t)control->orig_alength; in nxge_tdc_lp_conf()
671 ring->hv_tx_cntl_base_ioaddr_pp, in nxge_tdc_lp_conf()
672 ring->hv_tx_cntl_ioaddr_size); in nxge_tdc_lp_conf()
680 ring->hv_tx_cntl_base_ioaddr_pp, in nxge_tdc_lp_conf()
681 ring->hv_tx_cntl_ioaddr_size)); in nxge_tdc_lp_conf()
694 channel, hv_rv, ring->hv_tx_cntl_base_ioaddr_pp, in nxge_tdc_lp_conf()
695 ring->hv_tx_cntl_ioaddr_size, ra, size)); in nxge_tdc_lp_conf()
697 ring->hv_set = B_TRUE; in nxge_tdc_lp_conf()
726 rx_rbr_ring_t *ring; in nxge_rdc_lp_conf() local
733 ring = nxge->rx_rbr_rings->rbr_rings[channel]; in nxge_rdc_lp_conf()
735 if (ring->hv_set) { in nxge_rdc_lp_conf()
749 ring->hv_rx_buf_base_ioaddr_pp = (uint64_t)data->orig_ioaddr_pp; in nxge_rdc_lp_conf()
750 ring->hv_rx_buf_ioaddr_size = (uint64_t)data->orig_alength; in nxge_rdc_lp_conf()
754 ring->hv_rx_buf_base_ioaddr_pp, in nxge_rdc_lp_conf()
755 ring->hv_rx_buf_ioaddr_size); in nxge_rdc_lp_conf()
763 ring->hv_rx_buf_base_ioaddr_pp, in nxge_rdc_lp_conf()
764 ring->hv_rx_buf_ioaddr_size)); in nxge_rdc_lp_conf()
777 channel, hv_rv, ring->hv_rx_buf_base_ioaddr_pp, in nxge_rdc_lp_conf()
778 ring->hv_rx_buf_ioaddr_size, ra, size)); in nxge_rdc_lp_conf()
784 ring->hv_rx_cntl_base_ioaddr_pp = (uint64_t)control->orig_ioaddr_pp; in nxge_rdc_lp_conf()
785 ring->hv_rx_cntl_ioaddr_size = (uint64_t)control->orig_alength; in nxge_rdc_lp_conf()
789 ring->hv_rx_cntl_base_ioaddr_pp, in nxge_rdc_lp_conf()
790 ring->hv_rx_cntl_ioaddr_size); in nxge_rdc_lp_conf()
798 ring->hv_rx_cntl_base_ioaddr_pp, in nxge_rdc_lp_conf()
799 ring->hv_rx_cntl_ioaddr_size)); in nxge_rdc_lp_conf()
812 channel, hv_rv, ring->hv_rx_cntl_base_ioaddr_pp, in nxge_rdc_lp_conf()
813 ring->hv_rx_cntl_ioaddr_size, ra, size)); in nxge_rdc_lp_conf()
815 ring->hv_set = B_TRUE; in nxge_rdc_lp_conf()