Lines Matching refs:handle
141 npi_txc_dump_tdc_fzc_regs(npi_handle_t handle, uint8_t tdc) in npi_txc_dump_tdc_fzc_regs() argument
148 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_dump_tdc_fzc_regs()
155 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_tdc_fzc_regs()
162 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_tdc_fzc_regs()
163 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " in npi_txc_dump_tdc_fzc_regs()
168 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_tdc_fzc_regs()
185 npi_txc_dump_fzc_regs(npi_handle_t handle) in npi_txc_dump_fzc_regs() argument
191 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_fzc_regs()
196 NXGE_REG_RD64(handle, txc_fzc_offset[i], &value); in npi_txc_dump_fzc_regs()
197 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " in npi_txc_dump_fzc_regs()
201 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_fzc_regs()
221 npi_txc_dump_port_fzc_regs(npi_handle_t handle, uint8_t port) in npi_txc_dump_port_fzc_regs() argument
228 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_port_fzc_regs()
234 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_port_fzc_regs()
235 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, "0x%08llx " in npi_txc_dump_port_fzc_regs()
240 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, in npi_txc_dump_port_fzc_regs()
265 npi_txc_dma_max_burst(npi_handle_t handle, io_op_t op_mode, uint8_t channel, in npi_txc_dma_max_burst() argument
272 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_dma_max_burst()
281 TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_BURST_REG, channel, in npi_txc_dma_max_burst()
287 TXC_FZC_REG_WRITE64(handle, in npi_txc_dma_max_burst()
292 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_dma_max_burst()
317 npi_txc_dma_max_burst_set(npi_handle_t handle, uint8_t channel, in npi_txc_dma_max_burst_set() argument
322 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_dma_max_burst_set()
329 TXC_FZC_REG_WRITE64(handle, TXC_DMA_MAX_BURST_REG, in npi_txc_dma_max_burst_set()
352 npi_txc_dma_bytes_transmitted(npi_handle_t handle, uint8_t channel, in npi_txc_dma_bytes_transmitted() argument
359 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_dma_bytes_transmitted()
366 TXC_FZC_REG_READ64(handle, TXC_DMA_MAX_LENGTH_REG, channel, &val); in npi_txc_dma_bytes_transmitted()
390 npi_txc_control(npi_handle_t handle, io_op_t op_mode, in npi_txc_control() argument
395 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value); in npi_txc_control()
399 NXGE_REG_WR64(handle, TXC_CONTROL_REG, in npi_txc_control()
404 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_control()
426 npi_txc_global_enable(npi_handle_t handle) in npi_txc_global_enable() argument
434 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_enable()
435 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_enable()
452 npi_txc_global_disable(npi_handle_t handle) in npi_txc_global_disable() argument
461 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_disable()
462 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_disable()
479 npi_txc_control_clear(npi_handle_t handle, uint8_t port) in npi_txc_control_clear() argument
483 NXGE_REG_WR64(handle, TXC_PORT_CTL_REG, TXC_PORT_CNTL_CLEAR); in npi_txc_control_clear()
502 npi_txc_training_set(npi_handle_t handle, uint32_t vector) in npi_txc_training_set() argument
504 NXGE_REG_WR64(handle, TXC_TRAINING_REG, (uint64_t)vector); in npi_txc_training_set()
523 npi_txc_training_get(npi_handle_t handle, uint32_t *vector_p) in npi_txc_training_get() argument
527 NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK), in npi_txc_training_get()
549 npi_txc_port_enable(npi_handle_t handle, uint8_t port) in npi_txc_port_enable() argument
555 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_enable()
556 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | (1 << port)); in npi_txc_port_enable()
576 npi_txc_port_disable(npi_handle_t handle, uint8_t port) in npi_txc_port_disable() argument
582 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_disable()
583 NXGE_REG_WR64(handle, TXC_CONTROL_REG, (val & ~(1 << port))); in npi_txc_port_disable()
605 npi_txc_port_dma_enable(npi_handle_t handle, uint8_t port, in npi_txc_port_dma_enable() argument
611 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_enable()
617 npi_txc_port_dma_list_get(npi_handle_t handle, uint8_t port, in npi_txc_port_dma_list_get() argument
624 TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val); in npi_txc_port_dma_list_get()
646 npi_txc_port_dma_channel_enable(npi_handle_t handle, uint8_t port, in npi_txc_port_dma_channel_enable() argument
655 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_port_dma_channel_enable()
661 TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val); in npi_txc_port_dma_channel_enable()
662 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_channel_enable()
684 npi_txc_port_dma_channel_disable(npi_handle_t handle, uint8_t port, in npi_txc_port_dma_channel_disable() argument
693 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, in npi_txc_port_dma_channel_disable()
699 TXC_FZC_CNTL_REG_READ64(handle, TXC_PORT_DMA_ENABLE_REG, port, &val) in npi_txc_port_dma_channel_disable()
700 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_PORT_DMA_ENABLE_REG, port, in npi_txc_port_dma_channel_disable()
721 npi_txc_reorder_set(npi_handle_t handle, uint8_t port, uint8_t *reorder) in npi_txc_reorder_set() argument
727 NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val); in npi_txc_reorder_set()
731 NXGE_REG_WR64(handle, TXC_MAX_REORDER_REG, val); in npi_txc_reorder_set()
751 npi_txc_reorder_get(npi_handle_t handle, uint8_t port, uint32_t *reorder) in npi_txc_reorder_get() argument
757 NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val); in npi_txc_reorder_get()
783 npi_txc_pkt_stuffed_get(npi_handle_t handle, uint8_t port, in npi_txc_pkt_stuffed_get() argument
790 TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_STUFFED_REG, port, &value); in npi_txc_pkt_stuffed_get()
818 npi_txc_pkt_xmt_to_mac_get(npi_handle_t handle, uint8_t port, in npi_txc_pkt_xmt_to_mac_get() argument
825 TXC_FZC_CNTL_REG_READ64(handle, TXC_PKT_XMIT_REG, port, &value); in npi_txc_pkt_xmt_to_mac_get()
851 npi_txc_ro_states_get(npi_handle_t handle, uint8_t port, in npi_txc_ro_states_get() argument
869 TXC_FZC_CNTL_REG_READ64(handle, TXC_ROECC_ST_REG, port, &ecc.value); in npi_txc_ro_states_get()
871 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA0_REG, port, in npi_txc_ro_states_get()
873 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA1_REG, port, in npi_txc_ro_states_get()
875 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA2_REG, port, in npi_txc_ro_states_get()
877 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA3_REG, port, in npi_txc_ro_states_get()
879 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_DATA4_REG, port, in npi_txc_ro_states_get()
891 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, in npi_txc_ro_states_get()
895 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_CTL_REG, port, &ctl.value); in npi_txc_ro_states_get()
896 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE0_REG, port, &s0.value); in npi_txc_ro_states_get()
897 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE1_REG, port, &s1.value); in npi_txc_ro_states_get()
898 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE2_REG, port, &s2.value); in npi_txc_ro_states_get()
899 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_STATE3_REG, port, &s3.value); in npi_txc_ro_states_get()
900 TXC_FZC_CNTL_REG_READ64(handle, TXC_RO_TIDS_REG, port, &tids.value); in npi_txc_ro_states_get()
911 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_RO_CTL_REG, port, ctl.value); in npi_txc_ro_states_get()
917 npi_txc_ro_ecc_state_clr(npi_handle_t handle, uint8_t port) in npi_txc_ro_ecc_state_clr() argument
921 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_ROECC_ST_REG, port, 0); in npi_txc_ro_ecc_state_clr()
943 npi_txc_sf_states_get(npi_handle_t handle, uint8_t port, in npi_txc_sf_states_get() argument
961 TXC_FZC_CNTL_REG_READ64(handle, TXC_SFECC_ST_REG, port, &ecc.value); in npi_txc_sf_states_get()
963 TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA0_REG, port, in npi_txc_sf_states_get()
965 TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA1_REG, port, in npi_txc_sf_states_get()
967 TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA2_REG, port, in npi_txc_sf_states_get()
969 TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA3_REG, port, in npi_txc_sf_states_get()
971 TXC_FZC_CNTL_REG_READ64(handle, TXC_SF_DATA4_REG, port, in npi_txc_sf_states_get()
977 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, in npi_txc_sf_states_get()
992 npi_txc_sf_ecc_state_clr(npi_handle_t handle, uint8_t port) in npi_txc_sf_ecc_state_clr() argument
996 TXC_FZC_CNTL_REG_WRITE64(handle, TXC_SFECC_ST_REG, port, 0); in npi_txc_sf_ecc_state_clr()
1012 npi_txc_global_istatus_get(npi_handle_t handle, txc_int_stat_t *istatus) in npi_txc_global_istatus_get() argument
1016 NXGE_REG_RD64(handle, TXC_INT_STAT_REG, &status.value); in npi_txc_global_istatus_get()
1032 npi_txc_global_istatus_clear(npi_handle_t handle, uint64_t istatus) in npi_txc_global_istatus_clear() argument
1034 NXGE_REG_WR64(handle, TXC_INT_STAT_REG, istatus); in npi_txc_global_istatus_clear()
1038 npi_txc_global_imask_set(npi_handle_t handle, uint8_t portn, uint8_t istatus) in npi_txc_global_imask_set() argument
1042 NXGE_REG_RD64(handle, TXC_INT_MASK_REG, &val); in npi_txc_global_imask_set()
1063 NXGE_REG_WR64(handle, TXC_INT_MASK_REG, val); in npi_txc_global_imask_set()