Lines Matching refs:frame
3093 mif_frame_t frame; in npi_mac_mif_mdio_read() local
3096 frame.value = 0; in npi_mac_mif_mdio_read()
3097 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_read()
3098 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ in npi_mac_mif_mdio_read()
3099 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_read()
3100 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_read()
3101 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_read()
3102 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_read()
3103 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_read()
3106 "mdio read port %d addr val=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_read()
3108 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mdio_read()
3111 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); in npi_mac_mif_mdio_read()
3114 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_read()
3121 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_read()
3122 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ in npi_mac_mif_mdio_read()
3123 frame.bits.w0.phyad = portn; /* Port Number */ in npi_mac_mif_mdio_read()
3124 frame.bits.w0.regad = device; /* Device Number */ in npi_mac_mif_mdio_read()
3125 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_read()
3126 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_read()
3129 "mdio read port %d data frame=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_read()
3131 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mdio_read()
3134 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); in npi_mac_mif_mdio_read()
3137 "mdio read port %d data poll=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_read()
3139 *value = frame.bits.w0.data; in npi_mac_mif_mdio_read()
3155 mif_frame_t frame; in npi_mac_mif_mii_read() local
3158 frame.bits.w0.st = 0x1; /* Clause 22 */ in npi_mac_mif_mii_read()
3159 frame.bits.w0.op = 0x2; in npi_mac_mif_mii_read()
3160 frame.bits.w0.phyad = portn; in npi_mac_mif_mii_read()
3161 frame.bits.w0.regad = xcvr_reg; in npi_mac_mif_mii_read()
3162 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mii_read()
3163 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mii_read()
3164 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mii_read()
3167 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); in npi_mac_mif_mii_read()
3172 *value = frame.bits.w0.data; in npi_mac_mif_mii_read()
3175 xcvr_reg, frame.bits.w0.data)); in npi_mac_mif_mii_read()
3184 mif_frame_t frame; in npi_mac_mif_mdio_write() local
3187 frame.value = 0; in npi_mac_mif_mdio_write()
3188 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_write()
3189 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ in npi_mac_mif_mdio_write()
3190 frame.bits.w0.phyad = portn; /* Port Number */ in npi_mac_mif_mdio_write()
3191 frame.bits.w0.regad = device; /* Device Number */ in npi_mac_mif_mdio_write()
3192 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_write()
3193 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_write()
3194 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_write()
3196 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mdio_write()
3199 "mdio write port %d addr val=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_write()
3202 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); in npi_mac_mif_mdio_write()
3205 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_write()
3212 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_write()
3213 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ in npi_mac_mif_mdio_write()
3214 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_write()
3215 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_write()
3216 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_write()
3217 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_write()
3218 frame.bits.w0.data = value; in npi_mac_mif_mdio_write()
3219 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mdio_write()
3222 "mdio write port %d data val=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_write()
3225 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); in npi_mac_mif_mdio_write()
3228 "mdio write port %d data poll=0x%x\n", portn, frame.value)); in npi_mac_mif_mdio_write()
3242 mif_frame_t frame; in npi_mac_mif_mii_write() local
3245 frame.bits.w0.st = 0x1; /* Clause 22 */ in npi_mac_mif_mii_write()
3246 frame.bits.w0.op = 0x1; in npi_mac_mif_mii_write()
3247 frame.bits.w0.phyad = portn; in npi_mac_mif_mii_write()
3248 frame.bits.w0.regad = xcvr_reg; in npi_mac_mif_mii_write()
3249 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mii_write()
3250 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mii_write()
3251 frame.bits.w0.data = value; in npi_mac_mif_mii_write()
3252 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mii_write()
3255 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); in npi_mac_mif_mii_write()
3259 xcvr_reg, frame.value)); in npi_mac_mif_mii_write()
3434 mif_frame_t frame; in npi_mac_mif_mdio_link_intr_enable() local
3439 frame.bits.w0.st = 0; /* Clause 45 */ in npi_mac_mif_mdio_link_intr_enable()
3440 frame.bits.w0.op = 0; /* Select address */ in npi_mac_mif_mdio_link_intr_enable()
3441 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_link_intr_enable()
3442 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_link_intr_enable()
3443 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_link_intr_enable()
3444 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_link_intr_enable()
3445 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_link_intr_enable()
3447 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); in npi_mac_mif_mdio_link_intr_enable()
3450 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); in npi_mac_mif_mdio_link_intr_enable()