Lines Matching refs:sc
475 iwp_sc_t *sc; in iwp_attach() local
491 sc = ddi_get_soft_state(iwp_soft_state_p, in iwp_attach()
493 ASSERT(sc != NULL); in iwp_attach()
495 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_attach()
496 (void) iwp_init(sc); in iwp_attach()
499 atomic_and_32(&sc->sc_flags, ~IWP_F_SUSPEND); in iwp_attach()
516 sc = ddi_get_soft_state(iwp_soft_state_p, instance); in iwp_attach()
517 ASSERT(sc != NULL); in iwp_attach()
519 sc->sc_dip = dip; in iwp_attach()
524 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwp_attach()
525 &iwp_reg_accattr, &sc->sc_cfg_handle); in iwp_attach()
532 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle, in iwp_attach()
533 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwp_attach()
534 if ((sc->sc_dev_id != 0x422B) && in iwp_attach()
535 (sc->sc_dev_id != 0x422C) && in iwp_attach()
536 (sc->sc_dev_id != 0x4238) && in iwp_attach()
537 (sc->sc_dev_id != 0x4239) && in iwp_attach()
538 (sc->sc_dev_id != 0x008d) && in iwp_attach()
539 (sc->sc_dev_id != 0x008e)) { in iwp_attach()
545 iwp_set_chip_param(sc); in iwp_attach()
547 sc->sc_rev = ddi_get8(sc->sc_cfg_handle, in iwp_attach()
548 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID)); in iwp_attach()
553 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + in iwp_attach()
559 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle, in iwp_attach()
560 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ)); in iwp_attach()
561 if (!sc->sc_clsz) { in iwp_attach()
562 sc->sc_clsz = 16; in iwp_attach()
564 sc->sc_clsz = (sc->sc_clsz << 2); in iwp_attach()
566 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) + in iwp_attach()
569 IEEE80211_WEP_CRCLEN), sc->sc_clsz); in iwp_attach()
574 err = ddi_regs_map_setup(dip, 1, &sc->sc_base, in iwp_attach()
575 0, 0, &iwp_reg_accattr, &sc->sc_handle); in iwp_attach()
585 sc->sc_hw_rev = IWP_READ(sc, CSR_HW_REV); in iwp_attach()
601 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP); in iwp_attach()
603 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0, in iwp_attach()
611 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri); in iwp_attach()
618 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER, in iwp_attach()
619 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
620 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER, in iwp_attach()
621 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
622 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER, in iwp_attach()
623 DDI_INTR_PRI(sc->sc_intr_pri)); in iwp_attach()
625 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
626 cv_init(&sc->sc_put_seg_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
627 cv_init(&sc->sc_ucode_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
632 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL); in iwp_attach()
633 sc->sc_mf_thread = NULL; in iwp_attach()
634 sc->sc_mf_thread_switch = 0; in iwp_attach()
639 err = iwp_alloc_shared(sc); in iwp_attach()
646 (void) memset(sc->sc_shared, 0, sizeof (iwp_shared_t)); in iwp_attach()
651 err = iwp_alloc_kw(sc); in iwp_attach()
661 err = iwp_preinit(sc); in iwp_attach()
671 err = iwp_eep_load(sc); in iwp_attach()
681 sc->sc_eep_calib = (struct iwp_eep_calibration *) in iwp_attach()
682 iwp_eep_addr_trans(sc, EEP_CALIBRATION); in iwp_attach()
684 err = iwp_eep_ver_chk(sc); in iwp_attach()
692 iwp_get_mac_from_eep(sc); in iwp_attach()
698 err = iwp_ring_init(sc); in iwp_attach()
705 sc->sc_hdr = (iwp_firmware_hdr_t *)iwp_fw_bin; in iwp_attach()
710 err = iwp_alloc_fw_dma(sc); in iwp_attach()
721 ic = &sc->sc_ic; in iwp_attach()
770 iwp_overwrite_ic_default(sc); in iwp_attach()
782 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX, in iwp_attach()
783 iwp_rx_softintr, (caddr_t)sc); in iwp_attach()
790 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwp_intr, in iwp_attach()
791 (caddr_t)sc, NULL); in iwp_attach()
798 err = ddi_intr_enable(sc->sc_intr_htable[0]); in iwp_attach()
823 macp->m_driver = sc; in iwp_attach()
863 sc->sc_mf_thread_switch = 1; in iwp_attach()
864 if (NULL == sc->sc_mf_thread) { in iwp_attach()
865 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0, in iwp_attach()
866 iwp_thread, sc, 0, &p0, TS_RUN, minclsyspri); in iwp_attach()
869 atomic_or_32(&sc->sc_flags, IWP_F_ATTACHED); in iwp_attach()
874 (void) ddi_intr_disable(sc->sc_intr_htable[0]); in iwp_attach()
876 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); in iwp_attach()
878 (void) ddi_intr_remove_softint(sc->sc_soft_hdl); in iwp_attach()
879 sc->sc_soft_hdl = NULL; in iwp_attach()
883 iwp_free_fw_dma(sc); in iwp_attach()
885 iwp_ring_free(sc); in iwp_attach()
887 iwp_free_kw(sc); in iwp_attach()
889 iwp_free_shared(sc); in iwp_attach()
891 iwp_destroy_locks(sc); in iwp_attach()
893 (void) ddi_intr_free(sc->sc_intr_htable[0]); in iwp_attach()
895 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); in iwp_attach()
897 ddi_regs_map_free(&sc->sc_handle); in iwp_attach()
899 ddi_regs_map_free(&sc->sc_cfg_handle); in iwp_attach()
909 iwp_sc_t *sc; in iwp_detach() local
913 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); in iwp_detach()
914 ASSERT(sc != NULL); in iwp_detach()
915 ic = &sc->sc_ic; in iwp_detach()
921 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_detach()
922 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_detach()
924 atomic_or_32(&sc->sc_flags, IWP_F_SUSPEND); in iwp_detach()
926 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_detach()
927 iwp_stop(sc); in iwp_detach()
939 if (!(sc->sc_flags & IWP_F_ATTACHED)) { in iwp_detach()
946 sc->sc_mf_thread_switch = 0; in iwp_detach()
948 mutex_enter(&sc->sc_mt_lock); in iwp_detach()
949 while (sc->sc_mf_thread != NULL) { in iwp_detach()
950 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0) { in iwp_detach()
954 mutex_exit(&sc->sc_mt_lock); in iwp_detach()
956 err = mac_disable(sc->sc_ic.ic_mach); in iwp_detach()
964 iwp_stop(sc); in iwp_detach()
971 iwp_release_calib_buffer(sc); in iwp_detach()
976 (void) mac_unregister(sc->sc_ic.ic_mach); in iwp_detach()
978 mutex_enter(&sc->sc_glock); in iwp_detach()
979 iwp_free_fw_dma(sc); in iwp_detach()
980 iwp_ring_free(sc); in iwp_detach()
981 iwp_free_kw(sc); in iwp_detach()
982 iwp_free_shared(sc); in iwp_detach()
983 mutex_exit(&sc->sc_glock); in iwp_detach()
985 (void) ddi_intr_disable(sc->sc_intr_htable[0]); in iwp_detach()
986 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]); in iwp_detach()
987 (void) ddi_intr_free(sc->sc_intr_htable[0]); in iwp_detach()
988 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t)); in iwp_detach()
990 (void) ddi_intr_remove_softint(sc->sc_soft_hdl); in iwp_detach()
991 sc->sc_soft_hdl = NULL; in iwp_detach()
996 ieee80211_detach(&sc->sc_ic); in iwp_detach()
998 iwp_destroy_locks(sc); in iwp_detach()
1000 ddi_regs_map_free(&sc->sc_handle); in iwp_detach()
1001 ddi_regs_map_free(&sc->sc_cfg_handle); in iwp_detach()
1012 iwp_destroy_locks(iwp_sc_t *sc) in iwp_destroy_locks() argument
1014 cv_destroy(&sc->sc_mt_cv); in iwp_destroy_locks()
1015 cv_destroy(&sc->sc_cmd_cv); in iwp_destroy_locks()
1016 cv_destroy(&sc->sc_put_seg_cv); in iwp_destroy_locks()
1017 cv_destroy(&sc->sc_ucode_cv); in iwp_destroy_locks()
1018 mutex_destroy(&sc->sc_mt_lock); in iwp_destroy_locks()
1019 mutex_destroy(&sc->sc_tx_lock); in iwp_destroy_locks()
1020 mutex_destroy(&sc->sc_glock); in iwp_destroy_locks()
1027 iwp_alloc_dma_mem(iwp_sc_t *sc, size_t memsize, in iwp_alloc_dma_mem() argument
1037 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p, in iwp_alloc_dma_mem()
1104 iwp_alloc_fw_dma(iwp_sc_t *sc) in iwp_alloc_fw_dma() argument
1118 if (LE_32(sc->sc_hdr->init_textsz) > RTC_INST_SIZE) { in iwp_alloc_fw_dma()
1121 LE_32(sc->sc_hdr->init_textsz)); in iwp_alloc_fw_dma()
1126 if (LE_32(sc->sc_hdr->init_datasz) > RTC_DATA_SIZE) { in iwp_alloc_fw_dma()
1129 LE_32(sc->sc_hdr->init_datasz)); in iwp_alloc_fw_dma()
1134 if (LE_32(sc->sc_hdr->textsz) > RTC_INST_SIZE) { in iwp_alloc_fw_dma()
1137 LE_32(sc->sc_hdr->textsz)); in iwp_alloc_fw_dma()
1142 if (LE_32(sc->sc_hdr->datasz) > RTC_DATA_SIZE) { in iwp_alloc_fw_dma()
1145 LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1153 t = (char *)(sc->sc_hdr + 1); in iwp_alloc_fw_dma()
1154 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz), in iwp_alloc_fw_dma()
1157 &sc->sc_dma_fw_text); in iwp_alloc_fw_dma()
1164 dma_p = &sc->sc_dma_fw_text; in iwp_alloc_fw_dma()
1171 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz)); in iwp_alloc_fw_dma()
1176 t += LE_32(sc->sc_hdr->textsz); in iwp_alloc_fw_dma()
1177 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), in iwp_alloc_fw_dma()
1180 &sc->sc_dma_fw_data); in iwp_alloc_fw_dma()
1187 dma_p = &sc->sc_dma_fw_data; in iwp_alloc_fw_dma()
1194 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1196 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz), in iwp_alloc_fw_dma()
1199 &sc->sc_dma_fw_data_bak); in iwp_alloc_fw_dma()
1206 dma_p = &sc->sc_dma_fw_data_bak; in iwp_alloc_fw_dma()
1214 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz)); in iwp_alloc_fw_dma()
1219 t += LE_32(sc->sc_hdr->datasz); in iwp_alloc_fw_dma()
1220 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz), in iwp_alloc_fw_dma()
1223 &sc->sc_dma_fw_init_text); in iwp_alloc_fw_dma()
1230 dma_p = &sc->sc_dma_fw_init_text; in iwp_alloc_fw_dma()
1238 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz)); in iwp_alloc_fw_dma()
1243 t += LE_32(sc->sc_hdr->init_textsz); in iwp_alloc_fw_dma()
1244 err = iwp_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz), in iwp_alloc_fw_dma()
1247 &sc->sc_dma_fw_init_data); in iwp_alloc_fw_dma()
1254 dma_p = &sc->sc_dma_fw_init_data; in iwp_alloc_fw_dma()
1262 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz)); in iwp_alloc_fw_dma()
1264 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz); in iwp_alloc_fw_dma()
1270 iwp_free_fw_dma(iwp_sc_t *sc) in iwp_free_fw_dma() argument
1272 iwp_free_dma_mem(&sc->sc_dma_fw_text); in iwp_free_fw_dma()
1273 iwp_free_dma_mem(&sc->sc_dma_fw_data); in iwp_free_fw_dma()
1274 iwp_free_dma_mem(&sc->sc_dma_fw_data_bak); in iwp_free_fw_dma()
1275 iwp_free_dma_mem(&sc->sc_dma_fw_init_text); in iwp_free_fw_dma()
1276 iwp_free_dma_mem(&sc->sc_dma_fw_init_data); in iwp_free_fw_dma()
1283 iwp_alloc_shared(iwp_sc_t *sc) in iwp_alloc_shared() argument
1293 err = iwp_alloc_dma_mem(sc, sizeof (iwp_shared_t), in iwp_alloc_shared()
1296 &sc->sc_dma_sh); in iwp_alloc_shared()
1301 sc->sc_shared = (iwp_shared_t *)sc->sc_dma_sh.mem_va; in iwp_alloc_shared()
1304 dma_p = &sc->sc_dma_sh; in iwp_alloc_shared()
1313 iwp_free_shared(sc); in iwp_alloc_shared()
1318 iwp_free_shared(iwp_sc_t *sc) in iwp_free_shared() argument
1320 iwp_free_dma_mem(&sc->sc_dma_sh); in iwp_free_shared()
1327 iwp_alloc_kw(iwp_sc_t *sc) in iwp_alloc_kw() argument
1337 err = iwp_alloc_dma_mem(sc, IWP_KW_SIZE, in iwp_alloc_kw()
1340 &sc->sc_dma_kw); in iwp_alloc_kw()
1346 dma_p = &sc->sc_dma_kw; in iwp_alloc_kw()
1355 iwp_free_kw(sc); in iwp_alloc_kw()
1360 iwp_free_kw(iwp_sc_t *sc) in iwp_free_kw() argument
1362 iwp_free_dma_mem(&sc->sc_dma_kw); in iwp_free_kw()
1369 iwp_alloc_rx_ring(iwp_sc_t *sc) in iwp_alloc_rx_ring() argument
1378 ring = &sc->sc_rxq; in iwp_alloc_rx_ring()
1384 err = iwp_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t), in iwp_alloc_rx_ring()
1409 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, in iwp_alloc_rx_ring()
1441 iwp_free_rx_ring(sc); in iwp_alloc_rx_ring()
1449 iwp_reset_rx_ring(iwp_sc_t *sc) in iwp_reset_rx_ring() argument
1453 iwp_mac_access_enter(sc); in iwp_reset_rx_ring()
1454 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); in iwp_reset_rx_ring()
1456 if (IWP_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24)) { in iwp_reset_rx_ring()
1467 iwp_mac_access_exit(sc); in iwp_reset_rx_ring()
1469 sc->sc_rxq.cur = 0; in iwp_reset_rx_ring()
1473 iwp_free_rx_ring(iwp_sc_t *sc) in iwp_free_rx_ring() argument
1478 if (sc->sc_rxq.data[i].dma_data.dma_hdl) { in iwp_free_rx_ring()
1479 IWP_DMA_SYNC(sc->sc_rxq.data[i].dma_data, in iwp_free_rx_ring()
1483 iwp_free_dma_mem(&sc->sc_rxq.data[i].dma_data); in iwp_free_rx_ring()
1486 if (sc->sc_rxq.dma_desc.dma_hdl) { in iwp_free_rx_ring()
1487 IWP_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV); in iwp_free_rx_ring()
1490 iwp_free_dma_mem(&sc->sc_rxq.dma_desc); in iwp_free_rx_ring()
1497 iwp_alloc_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring, in iwp_alloc_tx_ring() argument
1519 err = iwp_alloc_dma_mem(sc, in iwp_alloc_tx_ring()
1545 err = iwp_alloc_dma_mem(sc, in iwp_alloc_tx_ring()
1582 err = iwp_alloc_dma_mem(sc, sc->sc_dmabuf_sz, in iwp_alloc_tx_ring()
1621 iwp_reset_tx_ring(iwp_sc_t *sc, iwp_tx_ring_t *ring) in iwp_reset_tx_ring() argument
1626 iwp_mac_access_enter(sc); in iwp_reset_tx_ring()
1628 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0); in iwp_reset_tx_ring()
1630 if (IWP_READ(sc, IWP_FH_TSSR_TX_STATUS_REG) & in iwp_reset_tx_ring()
1645 iwp_mac_access_exit(sc); in iwp_reset_tx_ring()
1648 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_reset_tx_ring()
1691 iwp_ring_init(iwp_sc_t *sc) in iwp_ring_init() argument
1700 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS, in iwp_ring_init()
1710 err = iwp_alloc_tx_ring(sc, &sc->sc_txq[IWP_CMD_QUEUE_NUM], in iwp_ring_init()
1716 err = iwp_alloc_rx_ring(sc); in iwp_ring_init()
1726 iwp_ring_free(iwp_sc_t *sc) in iwp_ring_free() argument
1730 iwp_free_rx_ring(sc); in iwp_ring_free()
1732 iwp_free_tx_ring(&sc->sc_txq[i]); in iwp_ring_free()
1794 iwp_sc_t *sc; in iwp_newstate() local
1803 sc = (iwp_sc_t *)ic; in iwp_newstate()
1807 mutex_enter(&sc->sc_glock); in iwp_newstate()
1813 atomic_or_32(&sc->sc_flags, IWP_F_SCANNING); in iwp_newstate()
1814 iwp_set_led(sc, 2, 10, 2); in iwp_newstate()
1820 sc->sc_config.assoc_id = 0; in iwp_newstate()
1821 sc->sc_config.filter_flags &= in iwp_newstate()
1827 LE_16(sc->sc_config.chan), in iwp_newstate()
1828 LE_32(sc->sc_config.flags), in iwp_newstate()
1829 LE_32(sc->sc_config.filter_flags))); in iwp_newstate()
1831 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_newstate()
1836 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1837 mutex_exit(&sc->sc_glock); in iwp_newstate()
1845 err = iwp_cmd(sc, REPLY_ADD_STA, &node, in iwp_newstate()
1850 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1851 mutex_exit(&sc->sc_glock); in iwp_newstate()
1856 mutex_exit(&sc->sc_glock); in iwp_newstate()
1858 err = sc->sc_newstate(ic, nstate, arg); in iwp_newstate()
1859 mutex_enter(&sc->sc_glock); in iwp_newstate()
1860 if ((err != 0) || ((err = iwp_scan(sc)) != 0)) { in iwp_newstate()
1863 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1866 mutex_exit(&sc->sc_glock); in iwp_newstate()
1871 sc->sc_clk = 0; in iwp_newstate()
1876 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1882 sc->sc_config.assoc_id = 0; in iwp_newstate()
1883 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); in iwp_newstate()
1890 if ((err = iwp_hw_set_before_auth(sc)) != 0) { in iwp_newstate()
1893 mutex_exit(&sc->sc_glock); in iwp_newstate()
1900 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1905 iwp_set_led(sc, 2, 10, 10); in iwp_newstate()
1912 err = iwp_run_state_config(sc); in iwp_newstate()
1916 mutex_exit(&sc->sc_glock); in iwp_newstate()
1924 atomic_or_32(&sc->sc_flags, IWP_F_RATE_AUTO_CTL); in iwp_newstate()
1936 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_newstate()
1942 iwp_set_led(sc, 2, 0, 1); in iwp_newstate()
1947 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1952 iwp_set_led(sc, 2, 1, 0); in iwp_newstate()
1957 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_newstate()
1962 mutex_exit(&sc->sc_glock); in iwp_newstate()
1964 return (sc->sc_newstate(ic, nstate, arg)); in iwp_newstate()
1971 iwp_mac_access_enter(iwp_sc_t *sc) in iwp_mac_access_enter() argument
1976 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_mac_access_enter()
1977 IWP_WRITE(sc, CSR_GP_CNTRL, in iwp_mac_access_enter()
1982 if ((IWP_READ(sc, CSR_GP_CNTRL) & in iwp_mac_access_enter()
2003 iwp_mac_access_exit(iwp_sc_t *sc) in iwp_mac_access_exit() argument
2005 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_mac_access_exit()
2006 IWP_WRITE(sc, CSR_GP_CNTRL, in iwp_mac_access_exit()
2024 iwp_mem_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) in iwp_mem_write() argument
2026 IWP_WRITE(sc, HBUS_TARG_MEM_WADDR, addr); in iwp_mem_write()
2027 IWP_WRITE(sc, HBUS_TARG_MEM_WDAT, data); in iwp_mem_write()
2034 iwp_reg_read(iwp_sc_t *sc, uint32_t addr) in iwp_reg_read() argument
2036 IWP_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24)); in iwp_reg_read()
2037 return (IWP_READ(sc, HBUS_TARG_PRPH_RDAT)); in iwp_reg_read()
2044 iwp_reg_write(iwp_sc_t *sc, uint32_t addr, uint32_t data) in iwp_reg_write() argument
2046 IWP_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24)); in iwp_reg_write()
2047 IWP_WRITE(sc, HBUS_TARG_PRPH_WDAT, data); in iwp_reg_write()
2059 iwp_load_init_firmware(iwp_sc_t *sc) in iwp_load_init_firmware() argument
2064 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2069 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_text.cookie.dmac_address, in iwp_load_init_firmware()
2070 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_init_text.cookie.dmac_size); in iwp_load_init_firmware()
2080 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2081 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_init_firmware()
2086 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2092 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2097 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_init_data.cookie.dmac_address, in iwp_load_init_firmware()
2098 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_init_data.cookie.dmac_size); in iwp_load_init_firmware()
2110 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2111 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_init_firmware()
2116 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_init_firmware()
2122 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_init_firmware()
2128 iwp_load_run_firmware(iwp_sc_t *sc) in iwp_load_run_firmware() argument
2133 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2138 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_text.cookie.dmac_address, in iwp_load_run_firmware()
2139 RTC_INST_LOWER_BOUND, sc->sc_dma_fw_text.cookie.dmac_size); in iwp_load_run_firmware()
2149 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2150 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_run_firmware()
2155 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2161 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2166 err = iwp_put_seg_fw(sc, sc->sc_dma_fw_data_bak.cookie.dmac_address, in iwp_load_run_firmware()
2167 RTC_DATA_LOWER_BOUND, sc->sc_dma_fw_data.cookie.dmac_size); in iwp_load_run_firmware()
2179 while (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2180 if (cv_timedwait(&sc->sc_put_seg_cv, &sc->sc_glock, clk) < 0) { in iwp_load_run_firmware()
2185 if (!(sc->sc_flags & IWP_F_PUT_SEG)) { in iwp_load_run_firmware()
2191 atomic_and_32(&sc->sc_flags, ~IWP_F_PUT_SEG); in iwp_load_run_firmware()
2201 iwp_rx_phy_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_rx_phy_intr() argument
2204 sc->sc_rx_phy_res.flag = 1; in iwp_rx_phy_intr()
2206 (void) memcpy(sc->sc_rx_phy_res.buf, (uint8_t *)(desc + 1), in iwp_rx_phy_intr()
2215 iwp_rx_mpdu_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_rx_mpdu_intr() argument
2217 ieee80211com_t *ic = &sc->sc_ic; in iwp_rx_mpdu_intr()
2219 iwp_rx_ring_t *ring = &sc->sc_rxq; in iwp_rx_mpdu_intr()
2237 stat = (iwp_rx_phy_res_t *)sc->sc_rx_phy_res.buf; in iwp_rx_mpdu_intr()
2285 if ((len < 16) || (len > sc->sc_dmabuf_sz)) { in iwp_rx_mpdu_intr()
2300 sc->sc_rx_err++; in iwp_rx_mpdu_intr()
2308 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2); in iwp_rx_mpdu_intr()
2311 sc->sc_assoc_id)); in iwp_rx_mpdu_intr()
2331 sc->sc_rx_nobuf++; in iwp_rx_mpdu_intr()
2346 iwp_tx_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_tx_intr() argument
2348 ieee80211com_t *ic = &sc->sc_ic; in iwp_tx_intr()
2349 iwp_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3]; in iwp_tx_intr()
2365 sc->sc_tx_retries++; in iwp_tx_intr()
2368 sc->sc_tx_retries)); in iwp_tx_intr()
2371 mutex_enter(&sc->sc_mt_lock); in iwp_tx_intr()
2372 sc->sc_tx_timer = 0; in iwp_tx_intr()
2373 mutex_exit(&sc->sc_mt_lock); in iwp_tx_intr()
2375 mutex_enter(&sc->sc_tx_lock); in iwp_tx_intr()
2382 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count >> 3))) { in iwp_tx_intr()
2383 sc->sc_need_reschedule = 0; in iwp_tx_intr()
2384 mutex_exit(&sc->sc_tx_lock); in iwp_tx_intr()
2386 mutex_enter(&sc->sc_tx_lock); in iwp_tx_intr()
2389 mutex_exit(&sc->sc_tx_lock); in iwp_tx_intr()
2396 iwp_cmd_intr(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_cmd_intr() argument
2402 if (sc->sc_cmd_accum > 0) { in iwp_cmd_intr()
2403 sc->sc_cmd_accum--; in iwp_cmd_intr()
2407 mutex_enter(&sc->sc_glock); in iwp_cmd_intr()
2409 sc->sc_cmd_flag = SC_CMD_FLG_DONE; in iwp_cmd_intr()
2411 cv_signal(&sc->sc_cmd_cv); in iwp_cmd_intr()
2413 mutex_exit(&sc->sc_glock); in iwp_cmd_intr()
2425 iwp_ucode_alive(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_ucode_alive() argument
2431 struct iwp_calib_results *res_p = &sc->sc_calib_results; in iwp_ucode_alive()
2455 (void) memcpy(&sc->sc_card_alive_init, ar, in iwp_ucode_alive()
2461 mutex_enter(&sc->sc_glock); in iwp_ucode_alive()
2463 rv = iwp_alive_common(sc); in iwp_ucode_alive()
2467 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2481 rv = iwp_cmd(sc, CALIBRATION_CFG_CMD, &cmd, sizeof (cmd), 1); in iwp_ucode_alive()
2485 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2489 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2496 (void) memcpy(&sc->sc_card_alive_run, ar, in iwp_ucode_alive()
2499 mutex_enter(&sc->sc_glock); in iwp_ucode_alive()
2504 rv = iwp_alive_common(sc); in iwp_ucode_alive()
2508 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2516 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2522 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2533 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2539 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2550 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2557 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2568 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, in iwp_ucode_alive()
2575 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2582 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); in iwp_ucode_alive()
2583 cv_signal(&sc->sc_ucode_cv); in iwp_ucode_alive()
2585 mutex_exit(&sc->sc_glock); in iwp_ucode_alive()
2598 iwp_sc_t *sc; in iwp_rx_softintr() local
2607 sc = (iwp_sc_t *)arg; in iwp_rx_softintr()
2608 ic = &sc->sc_ic; in iwp_rx_softintr()
2614 index = (sc->sc_shared->val0) & 0xfff; in iwp_rx_softintr()
2616 while (sc->sc_rxq.cur != index) { in iwp_rx_softintr()
2617 data = &sc->sc_rxq.data[sc->sc_rxq.cur]; in iwp_rx_softintr()
2623 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx, in iwp_rx_softintr()
2632 iwp_cmd_intr(sc, desc); in iwp_rx_softintr()
2637 iwp_rx_phy_intr(sc, desc); in iwp_rx_softintr()
2641 iwp_rx_mpdu_intr(sc, desc); in iwp_rx_softintr()
2645 iwp_tx_intr(sc, desc); in iwp_rx_softintr()
2649 iwp_ucode_alive(sc, desc); in iwp_rx_softintr()
2669 sc->sc_ostate = sc->sc_ic.ic_state; in iwp_rx_softintr()
2670 ieee80211_new_state(&sc->sc_ic, in iwp_rx_softintr()
2672 atomic_or_32(&sc->sc_flags, in iwp_rx_softintr()
2703 sc->sc_scan_pending++; in iwp_rx_softintr()
2716 iwp_save_calib_result(sc, desc); in iwp_rx_softintr()
2720 mutex_enter(&sc->sc_glock); in iwp_rx_softintr()
2721 atomic_or_32(&sc->sc_flags, IWP_F_FW_INIT); in iwp_rx_softintr()
2722 cv_signal(&sc->sc_ucode_cv); in iwp_rx_softintr()
2723 mutex_exit(&sc->sc_glock); in iwp_rx_softintr()
2744 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE; in iwp_rx_softintr()
2752 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7)); in iwp_rx_softintr()
2757 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_rx_softintr()
2769 iwp_sc_t *sc; in iwp_intr() local
2775 sc = (iwp_sc_t *)arg; in iwp_intr()
2777 r = IWP_READ(sc, CSR_INT); in iwp_intr()
2785 rfh = IWP_READ(sc, CSR_FH_INT_STATUS); in iwp_intr()
2793 IWP_WRITE(sc, CSR_INT_MASK, 0); in iwp_intr()
2798 IWP_WRITE(sc, CSR_INT, r); in iwp_intr()
2799 IWP_WRITE(sc, CSR_FH_INT_STATUS, rfh); in iwp_intr()
2804 iwp_stop(sc); in iwp_intr()
2805 sc->sc_ostate = sc->sc_ic.ic_state; in iwp_intr()
2808 if (!IWP_CHK_FAST_RECOVER(sc)) { in iwp_intr()
2809 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1); in iwp_intr()
2812 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); in iwp_intr()
2817 uint32_t tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_intr()
2825 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL); in iwp_intr()
2830 mutex_enter(&sc->sc_glock); in iwp_intr()
2831 atomic_or_32(&sc->sc_flags, IWP_F_PUT_SEG); in iwp_intr()
2832 cv_signal(&sc->sc_put_seg_cv); in iwp_intr()
2833 mutex_exit(&sc->sc_glock); in iwp_intr()
2846 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_intr()
2925 iwp_sc_t *sc; in iwp_m_tx() local
2932 sc = (iwp_sc_t *)arg; in iwp_m_tx()
2933 ic = &sc->sc_ic; in iwp_m_tx()
2935 if (sc->sc_flags & IWP_F_SUSPEND) { in iwp_m_tx()
2945 if ((sc->sc_flags & IWP_F_HW_ERR_RECOVER) && in iwp_m_tx()
2946 IWP_CHK_FAST_RECOVER(sc)) { in iwp_m_tx()
2972 iwp_sc_t *sc; in iwp_send() local
2990 sc = (iwp_sc_t *)ic; in iwp_send()
2992 if (sc->sc_flags & IWP_F_SUSPEND) { in iwp_send()
3001 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3002 ring = &sc->sc_txq[0]; in iwp_send()
3016 sc->sc_need_reschedule = 1; in iwp_send()
3017 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3023 sc->sc_tx_nobuf++; in iwp_send()
3030 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3040 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3042 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3043 sc->sc_need_reschedule = 0; in iwp_send()
3044 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3046 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3048 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3073 sc->sc_tx_err++; in iwp_send()
3075 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3077 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3078 sc->sc_need_reschedule = 0; in iwp_send()
3079 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3081 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3083 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3117 sc->sc_tx_err++; in iwp_send()
3119 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3121 if ((sc->sc_need_reschedule) && (ring->queued <= 0)) { in iwp_send()
3122 sc->sc_need_reschedule = 0; in iwp_send()
3123 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3125 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3127 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3262 mutex_enter(&sc->sc_tx_lock); in iwp_send()
3287 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_send()
3291 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_send()
3300 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->desc_cur); in iwp_send()
3302 mutex_exit(&sc->sc_tx_lock); in iwp_send()
3313 mutex_enter(&sc->sc_mt_lock); in iwp_send()
3314 if (0 == sc->sc_tx_timer) { in iwp_send()
3315 sc->sc_tx_timer = 4; in iwp_send()
3317 mutex_exit(&sc->sc_mt_lock); in iwp_send()
3329 iwp_sc_t *sc; in iwp_m_ioctl() local
3336 sc = (iwp_sc_t *)arg; in iwp_m_ioctl()
3337 ic = &sc->sc_ic; in iwp_m_ioctl()
3350 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_m_ioctl()
3351 iwp_m_stop(sc); in iwp_m_ioctl()
3352 (void) iwp_m_start(sc); in iwp_m_ioctl()
3367 iwp_sc_t *sc; in iwp_m_getprop() local
3373 sc = (iwp_sc_t *)arg; in iwp_m_getprop()
3375 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num, in iwp_m_getprop()
3385 iwp_sc_t *sc; in iwp_m_propinfo() local
3387 sc = (iwp_sc_t *)arg; in iwp_m_propinfo()
3388 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh); in iwp_m_propinfo()
3395 iwp_sc_t *sc; in iwp_m_setprop() local
3402 sc = (iwp_sc_t *)arg; in iwp_m_setprop()
3403 ic = &sc->sc_ic; in iwp_m_setprop()
3410 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_m_setprop()
3411 iwp_m_stop(sc); in iwp_m_setprop()
3412 (void) iwp_m_start(sc); in iwp_m_setprop()
3428 iwp_sc_t *sc; in iwp_m_stat() local
3435 sc = (iwp_sc_t *)arg; in iwp_m_stat()
3436 ic = &sc->sc_ic; in iwp_m_stat()
3438 mutex_enter(&sc->sc_glock); in iwp_m_stat()
3448 *val = sc->sc_tx_nobuf; in iwp_m_stat()
3451 *val = sc->sc_rx_nobuf; in iwp_m_stat()
3454 *val = sc->sc_rx_err; in iwp_m_stat()
3470 *val = sc->sc_tx_err; in iwp_m_stat()
3473 *val = sc->sc_tx_retries; in iwp_m_stat()
3485 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3488 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3492 mutex_exit(&sc->sc_glock); in iwp_m_stat()
3504 iwp_sc_t *sc; in iwp_m_start() local
3511 sc = (iwp_sc_t *)arg; in iwp_m_start()
3512 ic = &sc->sc_ic; in iwp_m_start()
3514 err = iwp_init(sc); in iwp_m_start()
3521 atomic_or_32(&sc->sc_flags, IWP_F_HW_ERR_RECOVER); in iwp_m_start()
3527 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); in iwp_m_start()
3538 iwp_sc_t *sc; in iwp_m_stop() local
3544 sc = (iwp_sc_t *)arg; in iwp_m_stop()
3545 ic = &sc->sc_ic; in iwp_m_stop()
3547 iwp_stop(sc); in iwp_m_stop()
3552 iwp_release_calib_buffer(sc); in iwp_m_stop()
3556 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_m_stop()
3557 atomic_and_32(&sc->sc_flags, ~IWP_F_RATE_AUTO_CTL); in iwp_m_stop()
3559 atomic_and_32(&sc->sc_flags, ~IWP_F_RUNNING); in iwp_m_stop()
3560 atomic_and_32(&sc->sc_flags, ~IWP_F_SCANNING); in iwp_m_stop()
3569 iwp_sc_t *sc; in iwp_m_unicst() local
3576 sc = (iwp_sc_t *)arg; in iwp_m_unicst()
3577 ic = &sc->sc_ic; in iwp_m_unicst()
3581 mutex_enter(&sc->sc_glock); in iwp_m_unicst()
3582 err = iwp_config(sc); in iwp_m_unicst()
3583 mutex_exit(&sc->sc_glock); in iwp_m_unicst()
3615 iwp_thread(iwp_sc_t *sc) in iwp_thread() argument
3617 ieee80211com_t *ic = &sc->sc_ic; in iwp_thread()
3625 while (sc->sc_mf_thread_switch) { in iwp_thread()
3626 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_thread()
3628 atomic_and_32(&sc->sc_flags, ~IWP_F_RADIO_OFF); in iwp_thread()
3630 atomic_or_32(&sc->sc_flags, IWP_F_RADIO_OFF); in iwp_thread()
3636 if (sc->sc_flags & IWP_F_RADIO_OFF) { in iwp_thread()
3645 (sc->sc_flags & IWP_F_HW_ERR_RECOVER)) { in iwp_thread()
3650 iwp_stop(sc); in iwp_thread()
3652 if (IWP_CHK_FAST_RECOVER(sc)) { in iwp_thread()
3654 bcopy(&sc->sc_config, &sc->sc_config_save, in iwp_thread()
3655 sizeof (sc->sc_config)); in iwp_thread()
3661 err = iwp_init(sc); in iwp_thread()
3671 atomic_or_32(&sc->sc_flags, IWP_F_RUNNING); in iwp_thread()
3675 if (!IWP_CHK_FAST_RECOVER(sc) || in iwp_thread()
3676 iwp_fast_recover(sc) != IWP_SUCCESS) { in iwp_thread()
3677 atomic_and_32(&sc->sc_flags, in iwp_thread()
3681 if (sc->sc_ostate != IEEE80211_S_INIT) { in iwp_thread()
3689 (sc->sc_flags & IWP_F_SCANNING) && sc->sc_scan_pending) { in iwp_thread()
3693 sc->sc_scan_pending--; in iwp_thread()
3702 (sc->sc_flags & IWP_F_RATE_AUTO_CTL)) { in iwp_thread()
3704 if (clk > sc->sc_clk + drv_usectohz(1000000)) { in iwp_thread()
3705 iwp_amrr_timeout(sc); in iwp_thread()
3711 mutex_enter(&sc->sc_mt_lock); in iwp_thread()
3712 if (sc->sc_tx_timer) { in iwp_thread()
3715 sc->sc_tx_timer--; in iwp_thread()
3716 if (0 == sc->sc_tx_timer) { in iwp_thread()
3717 atomic_or_32(&sc->sc_flags, in iwp_thread()
3719 sc->sc_ostate = IEEE80211_S_RUN; in iwp_thread()
3727 mutex_exit(&sc->sc_mt_lock); in iwp_thread()
3730 mutex_enter(&sc->sc_mt_lock); in iwp_thread()
3731 sc->sc_mf_thread = NULL; in iwp_thread()
3732 cv_signal(&sc->sc_mt_cv); in iwp_thread()
3733 mutex_exit(&sc->sc_mt_lock); in iwp_thread()
3741 iwp_cmd(iwp_sc_t *sc, int code, const void *buf, int size, int async) in iwp_cmd() argument
3743 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; in iwp_cmd()
3748 ASSERT(mutex_owned(&sc->sc_glock)); in iwp_cmd()
3768 sc->sc_cmd_accum++; in iwp_cmd()
3774 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_cmd()
3777 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_cmd()
3781 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwp_cmd()
3789 while (sc->sc_cmd_flag != SC_CMD_FLG_DONE) { in iwp_cmd()
3790 if (cv_timedwait(&sc->sc_cmd_cv, in iwp_cmd()
3791 &sc->sc_glock, clk) < 0) { in iwp_cmd()
3796 if (SC_CMD_FLG_DONE == sc->sc_cmd_flag) { in iwp_cmd()
3797 sc->sc_cmd_flag = SC_CMD_FLG_NONE; in iwp_cmd()
3800 sc->sc_cmd_flag = SC_CMD_FLG_NONE; in iwp_cmd()
3810 iwp_set_led(iwp_sc_t *sc, uint8_t id, uint8_t off, uint8_t on) in iwp_set_led() argument
3819 (void) iwp_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1); in iwp_set_led()
3826 iwp_hw_set_before_auth(iwp_sc_t *sc) in iwp_hw_set_before_auth() argument
3828 ieee80211com_t *ic = &sc->sc_ic; in iwp_hw_set_before_auth()
3836 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid); in iwp_hw_set_before_auth()
3837 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan)); in iwp_hw_set_before_auth()
3839 sc->sc_config.ofdm_ht_triple_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3840 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3841 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0; in iwp_hw_set_before_auth()
3844 sc->sc_config.cck_basic_rates = 0x03; in iwp_hw_set_before_auth()
3845 sc->sc_config.ofdm_basic_rates = 0; in iwp_hw_set_before_auth()
3848 sc->sc_config.cck_basic_rates = 0; in iwp_hw_set_before_auth()
3849 sc->sc_config.ofdm_basic_rates = 0x15; in iwp_hw_set_before_auth()
3851 sc->sc_config.cck_basic_rates = 0x0f; in iwp_hw_set_before_auth()
3852 sc->sc_config.ofdm_basic_rates = 0xff; in iwp_hw_set_before_auth()
3855 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK | in iwp_hw_set_before_auth()
3859 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK); in iwp_hw_set_before_auth()
3861 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK); in iwp_hw_set_before_auth()
3865 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_hw_set_before_auth()
3867 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_hw_set_before_auth()
3874 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags), in iwp_hw_set_before_auth()
3875 LE_32(sc->sc_config.filter_flags), in iwp_hw_set_before_auth()
3876 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates, in iwp_hw_set_before_auth()
3877 sc->sc_config.bssid[0], sc->sc_config.bssid[1], in iwp_hw_set_before_auth()
3878 sc->sc_config.bssid[2], sc->sc_config.bssid[3], in iwp_hw_set_before_auth()
3879 sc->sc_config.bssid[4], sc->sc_config.bssid[5])); in iwp_hw_set_before_auth()
3881 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_hw_set_before_auth()
3885 "failed to config chan%d\n", sc->sc_config.chan); in iwp_hw_set_before_auth()
3892 err = iwp_add_ap_sta(sc); in iwp_hw_set_before_auth()
3905 iwp_scan(iwp_sc_t *sc) in iwp_scan() argument
3907 ieee80211com_t *ic = &sc->sc_ic; in iwp_scan()
3908 iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM]; in iwp_scan()
4071 sc->sc_shared->queues_byte_cnt_tbls[ring->qid] in iwp_scan()
4074 sc->sc_shared->queues_byte_cnt_tbls[ring->qid]. in iwp_scan()
4082 IWP_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); in iwp_scan()
4091 iwp_config(iwp_sc_t *sc) in iwp_config() argument
4093 ieee80211com_t *ic = &sc->sc_ic; in iwp_config()
4106 err = iwp_cmd(sc, POWER_TABLE_CMD, &powertable, in iwp_config()
4121 err = iwp_cmd(sc, REPLY_BT_CONFIG, &bt, in iwp_config()
4132 (void) memset(&sc->sc_config, 0, sizeof (iwp_rxon_cmd_t)); in iwp_config()
4133 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr); in iwp_config()
4134 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr); in iwp_config()
4135 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan)); in iwp_config()
4136 sc->sc_config.flags = LE_32(RXON_FLG_BAND_24G_MSK); in iwp_config()
4137 sc->sc_config.flags &= LE_32(~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | in iwp_config()
4142 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS; in iwp_config()
4143 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4149 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS; in iwp_config()
4151 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK); in iwp_config()
4152 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4157 sc->sc_config.dev_type = RXON_DEV_TYPE_AP; in iwp_config()
4160 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER; in iwp_config()
4161 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK | in iwp_config()
4169 sc->sc_config.cck_basic_rates = 0x0f; in iwp_config()
4174 sc->sc_config.ofdm_basic_rates = 0xff; in iwp_config()
4176 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK | in iwp_config()
4181 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_config()
4196 err = iwp_cmd(sc, REPLY_REMOVE_STA, &rm_sta, sizeof (iwp_rem_sta_t), 0); in iwp_config()
4212 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0); in iwp_config()
4233 iwp_sc_t *sc; in iwp_quiesce() local
4235 sc = ddi_get_soft_state(iwp_soft_state_p, ddi_get_instance(dip)); in iwp_quiesce()
4236 if (NULL == sc) { in iwp_quiesce()
4249 atomic_or_32(&sc->sc_flags, IWP_F_QUIESCED); in iwp_quiesce()
4254 iwp_stop(sc); in iwp_quiesce()
4260 iwp_stop_master(iwp_sc_t *sc) in iwp_stop_master() argument
4265 tmp = IWP_READ(sc, CSR_RESET); in iwp_stop_master()
4266 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER); in iwp_stop_master()
4268 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_stop_master()
4275 if (IWP_READ(sc, CSR_RESET) & in iwp_stop_master()
4291 iwp_power_up(iwp_sc_t *sc) in iwp_power_up() argument
4295 iwp_mac_access_enter(sc); in iwp_power_up()
4296 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_power_up()
4299 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_power_up()
4300 iwp_mac_access_exit(sc); in iwp_power_up()
4310 iwp_preinit(iwp_sc_t *sc) in iwp_preinit() argument
4320 IWP_WRITE(sc, CSR_INT, 0xffffffff); in iwp_preinit()
4322 tmp = IWP_READ(sc, CSR_GIO_CHICKEN_BITS); in iwp_preinit()
4323 IWP_WRITE(sc, CSR_GIO_CHICKEN_BITS, in iwp_preinit()
4326 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_preinit()
4327 IWP_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwp_preinit()
4333 if (IWP_READ(sc, CSR_GP_CNTRL) & in iwp_preinit()
4344 iwp_mac_access_enter(sc); in iwp_preinit()
4346 iwp_reg_write(sc, ALM_APMG_CLK_EN, APMG_CLK_REG_VAL_DMA_CLK_RQT); in iwp_preinit()
4349 tmp = iwp_reg_read(sc, ALM_APMG_PCIDEV_STT); in iwp_preinit()
4350 iwp_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp | in iwp_preinit()
4352 iwp_mac_access_exit(sc); in iwp_preinit()
4354 radio_cfg = IWP_READ_EEP_SHORT(sc, EEP_SP_RADIO_CONFIGURATION); in iwp_preinit()
4356 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_preinit()
4357 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_preinit()
4368 IWP_WRITE(sc, CSR_INT_COALESCING, 512 / 32); in iwp_preinit()
4370 (void) iwp_power_up(sc); in iwp_preinit()
4372 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) { in iwp_preinit()
4373 tmp = ddi_get32(sc->sc_cfg_handle, in iwp_preinit()
4374 (uint32_t *)(sc->sc_cfg_base + 0xe8)); in iwp_preinit()
4375 ddi_put32(sc->sc_cfg_handle, in iwp_preinit()
4376 (uint32_t *)(sc->sc_cfg_base + 0xe8), in iwp_preinit()
4380 vlink = ddi_get8(sc->sc_cfg_handle, in iwp_preinit()
4381 (uint8_t *)(sc->sc_cfg_base + 0xf0)); in iwp_preinit()
4382 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0), in iwp_preinit()
4385 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_preinit()
4388 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, tmp); in iwp_preinit()
4393 iwp_mac_access_enter(sc); in iwp_preinit()
4394 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_preinit()
4396 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_preinit()
4399 tmp = iwp_reg_read(sc, ALM_APMG_PS_CTL); in iwp_preinit()
4401 iwp_reg_write(sc, ALM_APMG_PS_CTL, tmp); in iwp_preinit()
4402 iwp_mac_access_exit(sc); in iwp_preinit()
4404 if (PA_TYPE_MIX == sc->sc_chip_param.pa_type) { in iwp_preinit()
4405 IWP_WRITE(sc, CSR_GP_DRIVER_REG, in iwp_preinit()
4409 if (PA_TYPE_INTER == sc->sc_chip_param.pa_type) { in iwp_preinit()
4411 IWP_WRITE(sc, CSR_GP_DRIVER_REG, in iwp_preinit()
4422 iwp_eep_sem_down(iwp_sc_t *sc) in iwp_eep_sem_down() argument
4428 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_eep_sem_down()
4429 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_eep_sem_down()
4433 if (IWP_READ(sc, CSR_HW_IF_CONFIG_REG) & in iwp_eep_sem_down()
4447 iwp_eep_sem_up(iwp_sc_t *sc) in iwp_eep_sem_up() argument
4451 tmp = IWP_READ(sc, CSR_HW_IF_CONFIG_REG); in iwp_eep_sem_up()
4452 IWP_WRITE(sc, CSR_HW_IF_CONFIG_REG, in iwp_eep_sem_up()
4460 iwp_eep_load(iwp_sc_t *sc) in iwp_eep_load() argument
4464 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map); in iwp_eep_load()
4465 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map; in iwp_eep_load()
4470 eep_gp = IWP_READ(sc, CSR_EEPROM_GP); in iwp_eep_load()
4478 rr = iwp_eep_sem_down(sc); in iwp_eep_load()
4486 IWP_WRITE(sc, CSR_EEPROM_REG, addr<<1); in iwp_eep_load()
4487 tmp = IWP_READ(sc, CSR_EEPROM_REG); in iwp_eep_load()
4488 IWP_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2)); in iwp_eep_load()
4491 rv = IWP_READ(sc, CSR_EEPROM_REG); in iwp_eep_load()
4501 iwp_eep_sem_up(sc); in iwp_eep_load()
4508 iwp_eep_sem_up(sc); in iwp_eep_load()
4516 iwp_get_mac_from_eep(iwp_sc_t *sc) in iwp_get_mac_from_eep() argument
4518 ieee80211com_t *ic = &sc->sc_ic; in iwp_get_mac_from_eep()
4520 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->sc_eep_map[EEP_MAC_ADDRESS]); in iwp_get_mac_from_eep()
4532 iwp_init(iwp_sc_t *sc) in iwp_init() argument
4540 iwp_release_calib_buffer(sc); in iwp_init()
4542 mutex_enter(&sc->sc_glock); in iwp_init()
4543 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4545 err = iwp_init_common(sc); in iwp_init()
4547 mutex_exit(&sc->sc_glock); in iwp_init()
4554 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va, in iwp_init()
4555 sc->sc_dma_fw_data.mem_va, in iwp_init()
4556 sc->sc_dma_fw_data.alength); in iwp_init()
4559 err = iwp_load_init_firmware(sc); in iwp_init()
4563 mutex_exit(&sc->sc_glock); in iwp_init()
4570 IWP_WRITE(sc, CSR_RESET, 0); in iwp_init()
4573 while (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4574 if (cv_timedwait(&sc->sc_ucode_cv, in iwp_init()
4575 &sc->sc_glock, clk) < 0) { in iwp_init()
4580 if (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4583 mutex_exit(&sc->sc_glock); in iwp_init()
4587 mutex_exit(&sc->sc_glock); in iwp_init()
4592 iwp_stop(sc); in iwp_init()
4594 mutex_enter(&sc->sc_glock); in iwp_init()
4595 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4597 err = iwp_init_common(sc); in iwp_init()
4599 mutex_exit(&sc->sc_glock); in iwp_init()
4606 err = iwp_load_run_firmware(sc); in iwp_init()
4610 mutex_exit(&sc->sc_glock); in iwp_init()
4617 IWP_WRITE(sc, CSR_RESET, 0); in iwp_init()
4620 while (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4621 if (cv_timedwait(&sc->sc_ucode_cv, in iwp_init()
4622 &sc->sc_glock, clk) < 0) { in iwp_init()
4627 if (!(sc->sc_flags & IWP_F_FW_INIT)) { in iwp_init()
4630 mutex_exit(&sc->sc_glock); in iwp_init()
4634 mutex_exit(&sc->sc_glock); in iwp_init()
4638 mutex_enter(&sc->sc_glock); in iwp_init()
4639 atomic_and_32(&sc->sc_flags, ~IWP_F_FW_INIT); in iwp_init()
4645 err = iwp_config(sc); in iwp_init()
4649 mutex_exit(&sc->sc_glock); in iwp_init()
4656 mutex_exit(&sc->sc_glock); in iwp_init()
4664 iwp_stop(iwp_sc_t *sc) in iwp_stop() argument
4670 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_stop()
4671 mutex_enter(&sc->sc_glock); in iwp_stop()
4674 IWP_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); in iwp_stop()
4678 IWP_WRITE(sc, CSR_INT_MASK, 0); in iwp_stop()
4679 IWP_WRITE(sc, CSR_INT, CSR_INI_SET_MASK); in iwp_stop()
4680 IWP_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff); in iwp_stop()
4686 iwp_reset_tx_ring(sc, &sc->sc_txq[i]); in iwp_stop()
4692 iwp_reset_rx_ring(sc); in iwp_stop()
4694 iwp_mac_access_enter(sc); in iwp_stop()
4695 iwp_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT); in iwp_stop()
4696 iwp_mac_access_exit(sc); in iwp_stop()
4700 iwp_stop_master(sc); in iwp_stop()
4702 mutex_enter(&sc->sc_mt_lock); in iwp_stop()
4703 sc->sc_tx_timer = 0; in iwp_stop()
4704 mutex_exit(&sc->sc_mt_lock); in iwp_stop()
4706 tmp = IWP_READ(sc, CSR_RESET); in iwp_stop()
4707 IWP_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET); in iwp_stop()
4710 if (!(sc->sc_flags & IWP_F_QUIESCED)) { in iwp_stop()
4711 mutex_exit(&sc->sc_glock); in iwp_stop()
4754 iwp_amrr_timeout(iwp_sc_t *sc) in iwp_amrr_timeout() argument
4756 ieee80211com_t *ic = &sc->sc_ic; in iwp_amrr_timeout()
4767 sc->sc_clk = ddi_get_lbolt(); in iwp_amrr_timeout()
4829 iwp_eep_addr_trans(iwp_sc_t *sc, uint32_t indi_addr) in iwp_eep_addr_trans() argument
4836 return (&sc->sc_eep_map[di_addr]); in iwp_eep_addr_trans()
4841 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_GENERAL); in iwp_eep_addr_trans()
4844 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_HOST); in iwp_eep_addr_trans()
4847 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_REGULATORY); in iwp_eep_addr_trans()
4850 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_CALIBRATION); in iwp_eep_addr_trans()
4853 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_PROCESS_ADJST); in iwp_eep_addr_trans()
4856 temp = IWP_READ_EEP_SHORT(sc, EEP_LINK_OTHERS); in iwp_eep_addr_trans()
4867 return (&sc->sc_eep_map[di_addr]); in iwp_eep_addr_trans()
4874 iwp_put_seg_fw(iwp_sc_t *sc, uint32_t addr_s, uint32_t addr_d, uint32_t len) in iwp_put_seg_fw() argument
4877 iwp_mac_access_enter(sc); in iwp_put_seg_fw()
4879 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4882 IWP_WRITE(sc, IWP_FH_SRVC_CHNL_SRAM_ADDR_REG(IWP_FH_SRVC_CHNL), addr_d); in iwp_put_seg_fw()
4884 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL0_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4887 IWP_WRITE(sc, IWP_FH_TFDIB_CTRL1_REG(IWP_FH_SRVC_CHNL), len); in iwp_put_seg_fw()
4889 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_BUF_STS_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4894 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(IWP_FH_SRVC_CHNL), in iwp_put_seg_fw()
4899 iwp_mac_access_exit(sc); in iwp_put_seg_fw()
4908 iwp_alive_common(iwp_sc_t *sc) in iwp_alive_common() argument
4919 iwp_mac_access_enter(sc); in iwp_alive_common()
4924 sc->sc_scd_base = iwp_reg_read(sc, IWP_SCD_SRAM_BASE_ADDR); in iwp_alive_common()
4926 for (base = sc->sc_scd_base + IWP_SCD_CONTEXT_DATA_OFFSET; in iwp_alive_common()
4927 base < sc->sc_scd_base + IWP_SCD_TX_STTS_BITMAP_OFFSET; in iwp_alive_common()
4929 iwp_mem_write(sc, base, 0); in iwp_alive_common()
4932 for (; base < sc->sc_scd_base + IWP_SCD_TRANSLATE_TBL_OFFSET; in iwp_alive_common()
4934 iwp_mem_write(sc, base, 0); in iwp_alive_common()
4938 iwp_mem_write(sc, base + i, 0); in iwp_alive_common()
4941 iwp_reg_write(sc, IWP_SCD_DRAM_BASE_ADDR, in iwp_alive_common()
4942 sc->sc_dma_sh.cookie.dmac_address >> 10); in iwp_alive_common()
4944 iwp_reg_write(sc, IWP_SCD_QUEUECHAIN_SEL, in iwp_alive_common()
4947 iwp_reg_write(sc, IWP_SCD_AGGR_SEL, 0); in iwp_alive_common()
4950 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(i), 0); in iwp_alive_common()
4951 IWP_WRITE(sc, HBUS_TARG_WRPTR, 0 | (i << 8)); in iwp_alive_common()
4952 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
4954 iwp_mem_write(sc, sc->sc_scd_base + in iwp_alive_common()
4964 iwp_reg_write(sc, IWP_SCD_INTERRUPT_MASK, (1 << IWP_NUM_QUEUES) - 1); in iwp_alive_common()
4966 iwp_reg_write(sc, (IWP_SCD_BASE + 0x10), in iwp_alive_common()
4969 IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8)); in iwp_alive_common()
4970 iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0); in iwp_alive_common()
4977 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), in iwp_alive_common()
4984 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM), in iwp_alive_common()
4991 iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(i), in iwp_alive_common()
4998 iwp_mac_access_exit(sc); in iwp_alive_common()
5002 rv = iwp_cmd(sc, COEX_PRIORITY_TABLE_CMD, &w_cmd, sizeof (w_cmd), 1); in iwp_alive_common()
5012 c_cmd.data.cap_pin1 = LE_16(sc->sc_eep_calib->xtal_calib[0]); in iwp_alive_common()
5013 c_cmd.data.cap_pin2 = LE_16(sc->sc_eep_calib->xtal_calib[1]); in iwp_alive_common()
5015 rv = iwp_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &c_cmd, sizeof (c_cmd), 1); in iwp_alive_common()
5035 iwp_save_calib_result(iwp_sc_t *sc, iwp_rx_desc_t *desc) in iwp_save_calib_result() argument
5037 struct iwp_calib_results *res_p = &sc->sc_calib_results; in iwp_save_calib_result()
5110 iwp_release_calib_buffer(iwp_sc_t *sc) in iwp_release_calib_buffer() argument
5112 if (sc->sc_calib_results.lo_res != NULL) { in iwp_release_calib_buffer()
5113 kmem_free(sc->sc_calib_results.lo_res, in iwp_release_calib_buffer()
5114 sc->sc_calib_results.lo_res_len); in iwp_release_calib_buffer()
5115 sc->sc_calib_results.lo_res = NULL; in iwp_release_calib_buffer()
5118 if (sc->sc_calib_results.tx_iq_res != NULL) { in iwp_release_calib_buffer()
5119 kmem_free(sc->sc_calib_results.tx_iq_res, in iwp_release_calib_buffer()
5120 sc->sc_calib_results.tx_iq_res_len); in iwp_release_calib_buffer()
5121 sc->sc_calib_results.tx_iq_res = NULL; in iwp_release_calib_buffer()
5124 if (sc->sc_calib_results.tx_iq_perd_res != NULL) { in iwp_release_calib_buffer()
5125 kmem_free(sc->sc_calib_results.tx_iq_perd_res, in iwp_release_calib_buffer()
5126 sc->sc_calib_results.tx_iq_perd_res_len); in iwp_release_calib_buffer()
5127 sc->sc_calib_results.tx_iq_perd_res = NULL; in iwp_release_calib_buffer()
5130 if (sc->sc_calib_results.base_band_res != NULL) { in iwp_release_calib_buffer()
5131 kmem_free(sc->sc_calib_results.base_band_res, in iwp_release_calib_buffer()
5132 sc->sc_calib_results.base_band_res_len); in iwp_release_calib_buffer()
5133 sc->sc_calib_results.base_band_res = NULL; in iwp_release_calib_buffer()
5142 iwp_init_common(iwp_sc_t *sc) in iwp_init_common() argument
5147 (void) iwp_preinit(sc); in iwp_init_common()
5149 tmp = IWP_READ(sc, CSR_GP_CNTRL); in iwp_init_common()
5159 iwp_mac_access_enter(sc); in iwp_init_common()
5160 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); in iwp_init_common()
5162 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); in iwp_init_common()
5163 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG, in iwp_init_common()
5164 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8); in iwp_init_common()
5166 IWP_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG, in iwp_init_common()
5167 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address + in iwp_init_common()
5170 IWP_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, in iwp_init_common()
5176 iwp_mac_access_exit(sc); in iwp_init_common()
5177 IWP_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, in iwp_init_common()
5183 iwp_mac_access_enter(sc); in iwp_init_common()
5184 iwp_reg_write(sc, IWP_SCD_TXFACT, 0); in iwp_init_common()
5189 IWP_WRITE(sc, IWP_FH_KW_MEM_ADDR_REG, in iwp_init_common()
5190 sc->sc_dma_kw.cookie.dmac_address >> 4); in iwp_init_common()
5193 IWP_WRITE(sc, FH_MEM_CBBC_QUEUE(qid), in iwp_init_common()
5194 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8); in iwp_init_common()
5195 IWP_WRITE(sc, IWP_FH_TCSR_CHNL_TX_CONFIG_REG(qid), in iwp_init_common()
5200 iwp_mac_access_exit(sc); in iwp_init_common()
5205 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5206 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, in iwp_init_common()
5212 IWP_WRITE(sc, CSR_INT, 0xffffffff); in iwp_init_common()
5217 IWP_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK); in iwp_init_common()
5219 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5220 IWP_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwp_init_common()
5226 iwp_fast_recover(iwp_sc_t *sc) in iwp_fast_recover() argument
5228 ieee80211com_t *ic = &sc->sc_ic; in iwp_fast_recover()
5231 mutex_enter(&sc->sc_glock); in iwp_fast_recover()
5234 bcopy(&sc->sc_config_save, &sc->sc_config, in iwp_fast_recover()
5235 sizeof (sc->sc_config)); in iwp_fast_recover()
5237 sc->sc_config.assoc_id = 0; in iwp_fast_recover()
5238 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK); in iwp_fast_recover()
5240 if ((err = iwp_hw_set_before_auth(sc)) != IWP_SUCCESS) { in iwp_fast_recover()
5243 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5247 bcopy(&sc->sc_config_save, &sc->sc_config, in iwp_fast_recover()
5248 sizeof (sc->sc_config)); in iwp_fast_recover()
5251 err = iwp_run_state_config(sc); in iwp_fast_recover()
5255 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5259 iwp_set_led(sc, 2, 0, 1); in iwp_fast_recover()
5261 mutex_exit(&sc->sc_glock); in iwp_fast_recover()
5263 atomic_and_32(&sc->sc_flags, ~IWP_F_HW_ERR_RECOVER); in iwp_fast_recover()
5274 iwp_run_state_config(iwp_sc_t *sc) in iwp_run_state_config() argument
5276 struct ieee80211com *ic = &sc->sc_ic; in iwp_run_state_config()
5283 sc->sc_config.assoc_id = in->in_associd & 0x3fff; in iwp_run_state_config()
5289 sc->sc_config.flags &= in iwp_run_state_config()
5294 sc->sc_config.flags |= in iwp_run_state_config()
5299 sc->sc_config.flags |= in iwp_run_state_config()
5303 sc->sc_config.filter_flags |= in iwp_run_state_config()
5307 sc->sc_config.filter_flags |= in iwp_run_state_config()
5314 sc->sc_config.chan, sc->sc_config.flags, in iwp_run_state_config()
5315 sc->sc_config.filter_flags)); in iwp_run_state_config()
5317 err = iwp_cmd(sc, REPLY_RXON, &sc->sc_config, in iwp_run_state_config()
5333 iwp_overwrite_ic_default(iwp_sc_t *sc) in iwp_overwrite_ic_default() argument
5335 ieee80211com_t *ic = &sc->sc_ic; in iwp_overwrite_ic_default()
5337 sc->sc_newstate = ic->ic_newstate; in iwp_overwrite_ic_default()
5348 iwp_add_ap_sta(iwp_sc_t *sc) in iwp_add_ap_sta() argument
5350 ieee80211com_t *ic = &sc->sc_ic; in iwp_add_ap_sta()
5363 err = iwp_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1); in iwp_add_ap_sta()
5377 iwp_eep_ver_chk(iwp_sc_t *sc) in iwp_eep_ver_chk() argument
5379 if ((IWP_READ_EEP_SHORT(sc, EEP_VERSION) < 0x011a) || in iwp_eep_ver_chk()
5380 (sc->sc_eep_calib->tx_pow_calib_hdr.calib_version < 4)) { in iwp_eep_ver_chk()
5393 iwp_set_chip_param(iwp_sc_t *sc) in iwp_set_chip_param() argument
5395 if ((0x008d == sc->sc_dev_id) || in iwp_set_chip_param()
5396 (0x008e == sc->sc_dev_id)) { in iwp_set_chip_param()
5397 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5400 sc->sc_chip_param.tx_ant = ANT_A | ANT_B; in iwp_set_chip_param()
5401 sc->sc_chip_param.rx_ant = ANT_A | ANT_B; in iwp_set_chip_param()
5403 sc->sc_chip_param.pa_type = PA_TYPE_MIX; in iwp_set_chip_param()
5406 if ((0x422c == sc->sc_dev_id) || in iwp_set_chip_param()
5407 (0x4239 == sc->sc_dev_id)) { in iwp_set_chip_param()
5408 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5411 sc->sc_chip_param.tx_ant = ANT_B | ANT_C; in iwp_set_chip_param()
5412 sc->sc_chip_param.rx_ant = ANT_B | ANT_C; in iwp_set_chip_param()
5414 sc->sc_chip_param.pa_type = PA_TYPE_INTER; in iwp_set_chip_param()
5417 if ((0x422b == sc->sc_dev_id) || in iwp_set_chip_param()
5418 (0x4238 == sc->sc_dev_id)) { in iwp_set_chip_param()
5419 sc->sc_chip_param.phy_mode = PHY_MODE_G | in iwp_set_chip_param()
5422 sc->sc_chip_param.tx_ant = ANT_A | ANT_B | ANT_C; in iwp_set_chip_param()
5423 sc->sc_chip_param.rx_ant = ANT_A | ANT_B | ANT_C; in iwp_set_chip_param()
5425 sc->sc_chip_param.pa_type = PA_TYPE_SYSTEM; in iwp_set_chip_param()