Lines Matching refs:mask
70 #define WRITE_TCAM_REG_MASK0(handle, mask) \ argument
71 REG_PIO_WRITE64(handle, PFC_TCAM_MASK0, mask)
72 #define WRITE_TCAM_REG_MASK1(handle, mask) \ argument
73 REG_PIO_WRITE64(handle, PFC_TCAM_MASK1, mask)
218 } key, mask; member
225 #define mask_reg0 mask.regs.reg0
226 #define mask_reg1 mask.regs.reg1
230 #define mask0 mask.regs.reg0
231 #define mask1 mask.regs.reg1
242 #define ip4_class_mask mask.ipv4.class_code
243 #define ip4_class_mask_l mask.ipv4.class_code_l
244 #define ip4_blade_id_mask mask.ipv4.blade_id
245 #define ip4_noport_mask mask.ipv4.noport
246 #define ip4_proto_mask mask.ipv4.protocol
247 #define ip4_l4_hdr_mask mask.ipv4.l4_hdr
248 #define ip4_l4_hdr_mask_l mask.ipv4.l4_hdr_l
249 #define ip4_dest_mask mask.ipv4.ip_daddr
258 #define ip6_class_mask mask.ipv6.class_code
259 #define ip6_class_mask_l mask.ipv6.class_code_l
260 #define ip6_blade_id_mask mask.ipv6.blade_id
261 #define ip6_proto_mask mask.ipv6.protocol
262 #define ip6_l4_hdr_mask mask.ipv6.l4_hdr
263 #define ip6_l4_hdr_mask_l mask.ipv6.l4_hdr_l
270 #define ether_class_mask mask.enet.class_code
271 #define ether_class_mask_l mask.enet.class_code_l
272 #define ether_blade_id_mask mask.enet.blade_id
273 #define ether_ethframe_mask mask.enet.eframe