Lines Matching refs:adapter
95 (void) t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
101 (void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
159 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); in pm3393_interrupt_enable()
161 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_enable()
165 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
167 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
198 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); in pm3393_interrupt_disable()
200 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_disable()
241 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer); in pm3393_interrupt_clear()
243 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); in pm3393_interrupt_clear()
247 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); in pm3393_interrupt_clear()
249 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); in pm3393_interrupt_clear()
266 CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n", in pm3393_interrupt_handler()
392 extern void link_changed(adapter_t *adapter, int port_id); in pm3393_enable_port()
393 link_changed(cmac->adapter, 0); in pm3393_enable_port()
556 (void) t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
557 (void) t1_tpi_read((mac)->adapter, OFFSET(((name)+1)), &val1); \
558 (void) t1_tpi_read((mac)->adapter, OFFSET(((name)+2)), &val2); \
729 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index) in pm3393_mac_create() argument
739 cmac->adapter = adapter; in pm3393_mac_create()
742 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); in pm3393_mac_create()
743 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); in pm3393_mac_create()
744 (void) t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); in pm3393_mac_create()
745 (void) t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */ in pm3393_mac_create()
746 (void) t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); in pm3393_mac_create()
747 (void) t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); in pm3393_mac_create()
748 (void) t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800); in pm3393_mac_create()
749 (void) t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800); in pm3393_mac_create()
750 (void) t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800); in pm3393_mac_create()
751 (void) t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800); in pm3393_mac_create()
752 (void) t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800); in pm3393_mac_create()
753 (void) t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800); in pm3393_mac_create()
754 (void) t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800); in pm3393_mac_create()
755 (void) t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800); in pm3393_mac_create()
756 (void) t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800); in pm3393_mac_create()
757 (void) t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800); in pm3393_mac_create()
758 (void) t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800); in pm3393_mac_create()
759 (void) t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800); in pm3393_mac_create()
760 (void) t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800); in pm3393_mac_create()
761 (void) t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800); in pm3393_mac_create()
762 (void) t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00); in pm3393_mac_create()
763 (void) t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */ in pm3393_mac_create()
765 (void) t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */ in pm3393_mac_create()
766 (void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */ in pm3393_mac_create()
767 (void) t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */ in pm3393_mac_create()
768 (void) t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */ in pm3393_mac_create()
769 (void) t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */ in pm3393_mac_create()
770 (void) t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */ in pm3393_mac_create()
771 (void) t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */ in pm3393_mac_create()
772 (void) t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */ in pm3393_mac_create()
773 (void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */ in pm3393_mac_create()
774 (void) t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
775 (void) t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
776 …(void) t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The ot… in pm3393_mac_create()
777 (void) t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
779 (void) t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */ in pm3393_mac_create()
780 (void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */ in pm3393_mac_create()
781 (void) t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */ in pm3393_mac_create()
782 (void) t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */ in pm3393_mac_create()
783 (void) t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */ in pm3393_mac_create()
784 (void) t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */ in pm3393_mac_create()
785 (void) t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */ in pm3393_mac_create()
786 (void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */ in pm3393_mac_create()
787 (void) t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
788 (void) t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
789 …(void) t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The … in pm3393_mac_create()
791 (void) t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */ in pm3393_mac_create()
792 (void) t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */ in pm3393_mac_create()
793 (void) t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */ in pm3393_mac_create()
794 (void) t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */ in pm3393_mac_create()
795 (void) t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */ in pm3393_mac_create()
796 (void) t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */ in pm3393_mac_create()
798 (void) t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */ in pm3393_mac_create()
799 (void) t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */ in pm3393_mac_create()
801 …(void) t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port stat… in pm3393_mac_create()
802 …(void) t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interr… in pm3393_mac_create()
804 (void) t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ in pm3393_mac_create()
806 (void) t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); in pm3393_mac_create()
807 (void) t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ in pm3393_mac_create()
808 (void) t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */ in pm3393_mac_create()
809 (void) t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ in pm3393_mac_create()
813 (void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */ in pm3393_mac_create()
814 (void) t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */ in pm3393_mac_create()
815 (void) t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */ in pm3393_mac_create()
816 (void) t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */ in pm3393_mac_create()
817 (void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */ in pm3393_mac_create()
819 (void) t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */ in pm3393_mac_create()
820 (void) t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */ in pm3393_mac_create()
821 (void) t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */ in pm3393_mac_create()
826 static int pm3393_mac_reset(adapter_t * adapter) in pm3393_mac_reset() argument
868 (void) t1_tpi_read(adapter, A_ELMER0_GPO, &val); in pm3393_mac_reset()
870 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in pm3393_mac_reset()
883 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in pm3393_mac_reset()
894 (void) t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val); in pm3393_mac_reset()
917 CH_DBG(adapter, HW, in pm3393_mac_reset()