Lines Matching refs:pdev
50 #define PXP2_SET_FIRST_LAST_ILT(pdev, blk, first, last) \ argument
52 if (CHIP_IS_E1(pdev)) { \
53 …REG_WR(pdev,(PORT_ID(pdev) ? PXP2_REG_PSWRQ_##blk##1_L2P: PXP2_REG_PSWRQ_##blk##0_L2P),((last)<<10…
55 REG_WR(pdev,PXP2_REG_RQ_##blk##_FIRST_ILT,(first)); \
56 REG_WR(pdev,PXP2_REG_RQ_##blk##_LAST_ILT,(last)); \
135 void lm_reset_set_inprogress(struct _lm_device_t *pdev) in lm_reset_set_inprogress() argument
137 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_reset_set_inprogress()
143 void lm_reset_clear_inprogress(struct _lm_device_t *pdev) in lm_reset_clear_inprogress() argument
145 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_reset_clear_inprogress()
151 u8_t lm_pm_reset_is_inprogress(struct _lm_device_t *pdev) in lm_pm_reset_is_inprogress() argument
153 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_pm_reset_is_inprogress()
159 void lm_read_attn_regs(lm_device_t *pdev, u32_t * attn_sig_af_inv_arr, u32_t arr_size);
160 u8_t lm_recoverable_error(lm_device_t *pdev, u32_t * attn_sig, u32_t arr_size);
173 u8_t lm_er_handling_pending(struct _lm_device_t *pdev) in lm_er_handling_pending() argument
177 if (!pdev->params.enable_error_recovery || CHIP_IS_E1x(pdev)) in lm_er_handling_pending()
182 lm_read_attn_regs(pdev, attn_sig_af_inv_arr, ARRSIZE(attn_sig_af_inv_arr)); in lm_er_handling_pending()
184 return lm_recoverable_error(pdev, attn_sig_af_inv_arr, ARRSIZE(attn_sig_af_inv_arr)); in lm_er_handling_pending()
187 u8_t lm_reset_is_inprogress(struct _lm_device_t *pdev) in lm_reset_is_inprogress() argument
190 lm_pm_reset_is_inprogress(pdev) || in lm_reset_is_inprogress()
191 lm_er_handling_pending(pdev) || in lm_reset_is_inprogress()
192 lm_fl_reset_is_inprogress(PFDEV(pdev)) || in lm_reset_is_inprogress()
193 pdev->panic || in lm_reset_is_inprogress()
194 (IS_VFDEV(pdev) ? lm_fl_reset_is_inprogress(pdev) : FALSE); in lm_reset_is_inprogress()
204 void lm_fl_reset_set_inprogress(struct _lm_device_t *pdev) in lm_fl_reset_set_inprogress() argument
206 pdev->params.is_flr = TRUE; in lm_fl_reset_set_inprogress()
207 if (IS_PFDEV(pdev)) in lm_fl_reset_set_inprogress()
209 DbgMessage(pdev, FATAL, "PF[%d] is under FLR\n",FUNC_ID(pdev)); in lm_fl_reset_set_inprogress()
213 DbgMessage(pdev, FATAL, "VF[%d] is under FLR\n",ABS_VFID(pdev)); in lm_fl_reset_set_inprogress()
218 void lm_fl_reset_clear_inprogress(struct _lm_device_t *pdev) in lm_fl_reset_clear_inprogress() argument
220 pdev->params.is_flr = FALSE; in lm_fl_reset_clear_inprogress()
224 u8_t lm_fl_reset_is_inprogress(struct _lm_device_t *pdev) in lm_fl_reset_is_inprogress() argument
226 return pdev->params.is_flr; in lm_fl_reset_is_inprogress()
229 u8_t lm_is_function_after_flr(struct _lm_device_t * pdev) in lm_is_function_after_flr() argument
232 is_after_flr = pdev->params.is_flr; in lm_is_function_after_flr()
235 if (IS_PFDEV(pdev)) in lm_is_function_after_flr()
237 DbgMessage(pdev, FATAL, "PF[%d] was FLRed\n",FUNC_ID(pdev)); in lm_is_function_after_flr()
241 DbgMessage(pdev, FATAL, "VF[%d] was FLRed\n",ABS_VFID(pdev)); in lm_is_function_after_flr()
249 lm_status_t lm_cleanup_after_flr(struct _lm_device_t * pdev) in lm_cleanup_after_flr() argument
266 if (CHIP_REV_IS_EMUL(pdev)) in lm_cleanup_after_flr()
270 else if (CHIP_REV_IS_FPGA(pdev)) in lm_cleanup_after_flr()
280 pdev->flr_stats.default_wait_interval_ms = DEFAULT_WAIT_INTERVAL_MICSEC; in lm_cleanup_after_flr()
281 if (IS_PFDEV(pdev)) in lm_cleanup_after_flr()
283 DbgMessage(pdev, FATAL, "lm_cleanup_after_flr PF[%d] >>>\n",FUNC_ID(pdev)); in lm_cleanup_after_flr()
284 pdev->flr_stats.is_pf = TRUE; in lm_cleanup_after_flr()
286 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in lm_cleanup_after_flr()
290 …pdev->flr_stats.cfc_usage_counter = REG_WAIT_VERIFY_VAL(pdev, CFC_REG_NUM_LCIDS_INSIDE_PF, 0, wait… in lm_cleanup_after_flr()
291 …DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed CFC per pf usage counter\n",pdev->flr_stats.cf… in lm_cleanup_after_flr()
295 … pdev->flr_stats.dq_usage_counter = REG_WAIT_VERIFY_VAL(pdev, DORQ_REG_PF_USAGE_CNT, 0, wait_ms); in lm_cleanup_after_flr()
296 …DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed DQ per pf usage counter\n", pdev->flr_stats.dq… in lm_cleanup_after_flr()
299 …pdev->flr_stats.qm_usage_counter = REG_WAIT_VERIFY_VAL(pdev, QM_REG_PF_USG_CNT_0 + 4*FUNC_ID(pdev)… in lm_cleanup_after_flr()
300 …DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed QM per pf usage counter\n", pdev->flr_stats.qm… in lm_cleanup_after_flr()
304 …pdev->flr_stats.tm_vnic_usage_counter = REG_WAIT_VERIFY_VAL(pdev, TM_REG_LIN0_VNIC_UC + 4*PORT_ID(… in lm_cleanup_after_flr()
305 DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed TM%d(VNIC) per pf usage counter\n", in lm_cleanup_after_flr()
306 … pdev->flr_stats.tm_vnic_usage_counter, DEFAULT_WAIT_INTERVAL_MICSEC, PORT_ID(pdev)); in lm_cleanup_after_flr()
308 …pdev->flr_stats.tm_num_scans_usage_counter = REG_WAIT_VERIFY_VAL(pdev, TM_REG_LIN0_NUM_SCANS + 4*P… in lm_cleanup_after_flr()
309 DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed TM%d(NUM_SCANS) per pf usage counter\n", in lm_cleanup_after_flr()
310 … pdev->flr_stats.tm_num_scans_usage_counter, DEFAULT_WAIT_INTERVAL_MICSEC, PORT_ID(pdev)); in lm_cleanup_after_flr()
312 …pdev->flr_stats.dmae_cx = REG_WAIT_VERIFY_VAL(pdev, lm_dmae_idx_to_go_cmd(DMAE_WB_ACCESS_FUNCTION_… in lm_cleanup_after_flr()
313 DbgMessage(pdev, FATAL, "%d*%dms waiting for zeroed DMAE_REG_GO_C%d \n", in lm_cleanup_after_flr()
314 …pdev->flr_stats.tm_num_scans_usage_counter, DEFAULT_WAIT_INTERVAL_MICSEC, DMAE_WB_ACCESS_FUNCTION_… in lm_cleanup_after_flr()
318 DbgMessage(pdev, FATAL, "lm_cleanup_after_flr VF[%d] >>>\n",ABS_VFID(pdev)); in lm_cleanup_after_flr()
332 pretend_value = ABS_FUNC_ID(pdev) | (1<<3) | (ABS_VFID(pdev) << 4); in lm_cleanup_after_flr()
333 lm_status = lm_pretend_func(PFDEV(pdev), pretend_value); in lm_cleanup_after_flr()
336 …pdev->flr_stats.dq_usage_counter = REG_WAIT_VERIFY_VAL(PFDEV(pdev), DORQ_REG_VF_USAGE_CNT, 0, wait… in lm_cleanup_after_flr()
337 lm_pretend_func(PFDEV(pdev), ABS_FUNC_ID(pdev)); in lm_cleanup_after_flr()
338 …DbgMessage(pdev, FATAL, "%d*%dms waiting for DQ per vf usage counter\n", pdev->flr_stats.dq_usage_… in lm_cleanup_after_flr()
342 DbgMessage(pdev, FATAL, "lm_pretend_func(%x) returns %d\n",pretend_value,lm_status); in lm_cleanup_after_flr()
343 … DbgMessage(pdev, FATAL, "VF[%d]: could not read DORQ_REG_VF_USAGE_CNT\n", ABS_VFID(pdev)); in lm_cleanup_after_flr()
351 function_for_clean_up = IS_VFDEV(pdev) ? FW_VFID(pdev) : FUNC_ID(pdev); in lm_cleanup_after_flr()
353 …LM_INTMEM_READ32(PFDEV(pdev),CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(function_for_clean_up),&cleanup_… in lm_cleanup_after_flr()
354 DbgMessage(pdev, FATAL, "CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET is %x",cleanup_complete); in lm_cleanup_after_flr()
365 DbgMessage(pdev, FATAL, "Final cleanup\n"); in lm_cleanup_after_flr()
367 REG_WR(PFDEV(pdev),XSDM_REG_OPERATION_GEN, final_cleanup.command); in lm_cleanup_after_flr()
368 …pdev->flr_stats.final_cleanup_complete = REG_WAIT_VERIFY_VAL(PFDEV(pdev), BAR_CSTRORM_INTMEM + CST… in lm_cleanup_after_flr()
369 …DbgMessage(pdev, FATAL, "%d*%dms waiting for final cleanup compete\n", pdev->flr_stats.final_clean… in lm_cleanup_after_flr()
371 …LM_INTMEM_WRITE32(PFDEV(pdev),CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(function_for_clean_up),0, BAR_C… in lm_cleanup_after_flr()
401 … pbf_reg_pN_tq_occupancy = (CHIP_IS_E3B0(pdev))? PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY; in lm_cleanup_after_flr()
402 …pbf_reg_pN_tq_lines_freed_cnt = (CHIP_IS_E3B0(pdev)) ? PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_… in lm_cleanup_after_flr()
405 …pbf_reg_pN_tq_occupancy = (CHIP_IS_E3B0(pdev)) ? PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY; in lm_cleanup_after_flr()
406 …pbf_reg_pN_tq_lines_freed_cnt = (CHIP_IS_E3B0(pdev)) ? PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_… in lm_cleanup_after_flr()
409 …pbf_reg_pN_tq_occupancy = (CHIP_IS_E3B0(pdev)) ? PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPAN… in lm_cleanup_after_flr()
410 …pbf_reg_pN_tq_lines_freed_cnt = (CHIP_IS_E3B0(pdev)) ? PBF_REG_TQ_LINES_FREED_CNT_LB_Q : PBF_REG_P… in lm_cleanup_after_flr()
413 pdev->flr_stats.pbf_queue[idx] = 0; in lm_cleanup_after_flr()
414 tq_freed_cnt_last = tq_freed_cnt_start = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_cleanup_after_flr()
415 tq_occ = tq_to_free = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_cleanup_after_flr()
416 DbgMessage(pdev, FATAL, "TQ_OCCUPANCY[%d] : s:%x\n", (idx == 2) ? 4 : idx, tq_to_free); in lm_cleanup_after_flr()
417 …DbgMessage(pdev, FATAL, "TQ_LINES_FREED_CNT[%d]: s:%x\n", (idx == 2) ? 4 : idx, tq_freed_cnt_start… in lm_cleanup_after_flr()
420 if (pdev->flr_stats.pbf_queue[idx]++ < wait_ms/DEFAULT_WAIT_INTERVAL_MICSEC) in lm_cleanup_after_flr()
422 mm_wait(PFDEV(pdev), DEFAULT_WAIT_INTERVAL_MICSEC); in lm_cleanup_after_flr()
423 tq_occ = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_occupancy); in lm_cleanup_after_flr()
424 tq_freed_cnt_last = REG_RD(PFDEV(pdev), pbf_reg_pN_tq_lines_freed_cnt); in lm_cleanup_after_flr()
428 … DbgMessage(pdev, FATAL, "TQ_OCCUPANCY[%d] : c:%x\n", (idx == 2) ? 4 : idx, tq_occ); in lm_cleanup_after_flr()
429 …DbgMessage(pdev, FATAL, "TQ_LINES_FREED_CNT[%d]: c:%x\n", (idx == 2) ? 4 : idx, tq_freed_cnt_last); in lm_cleanup_after_flr()
434 DbgMessage(pdev, FATAL, "%d*%dms waiting for PBF command queue[%d] is flushed\n", in lm_cleanup_after_flr()
435 … pdev->flr_stats.pbf_queue[idx], DEFAULT_WAIT_INTERVAL_MICSEC, (idx == 2) ? 4 : idx); in lm_cleanup_after_flr()
455 pbf_reg_pN_init_crd = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD; in lm_cleanup_after_flr()
456 pbf_reg_pN_credit = (CHIP_IS_E3B0(pdev)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT; in lm_cleanup_after_flr()
457 …pbf_reg_pN_internal_crd_freed = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : PBF_REG… in lm_cleanup_after_flr()
460 pbf_reg_pN_init_crd = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD; in lm_cleanup_after_flr()
461 pbf_reg_pN_credit = (CHIP_IS_E3B0(pdev)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT; in lm_cleanup_after_flr()
462 …pbf_reg_pN_internal_crd_freed = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : PBF_REG… in lm_cleanup_after_flr()
465 … pbf_reg_pN_init_crd = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD; in lm_cleanup_after_flr()
466 pbf_reg_pN_credit = (CHIP_IS_E3B0(pdev)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT; in lm_cleanup_after_flr()
467 …pbf_reg_pN_internal_crd_freed = (CHIP_IS_E3B0(pdev)) ? PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : PBF_R… in lm_cleanup_after_flr()
470 pdev->flr_stats.pbf_transmit_buffer[idx] = 0; in lm_cleanup_after_flr()
471 …inernal_freed_crd_last = inernal_freed_crd_start = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_fre… in lm_cleanup_after_flr()
472 credit_last = credit_start = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_cleanup_after_flr()
473 init_crd = REG_RD(PFDEV(pdev), pbf_reg_pN_init_crd); in lm_cleanup_after_flr()
474 DbgMessage(pdev, FATAL, "INIT CREDIT[%d] : %x\n", (idx == 2) ? 4 : idx, init_crd); in lm_cleanup_after_flr()
475 … DbgMessage(pdev, FATAL, "CREDIT[%d] : s:%x\n", (idx == 2) ? 4 : idx, credit_start); in lm_cleanup_after_flr()
476 …DbgMessage(pdev, FATAL, "INTERNAL_CRD_FREED[%d]: s:%x\n", (idx == 2) ? 4 : idx, inernal_freed_crd_… in lm_cleanup_after_flr()
480 if (pdev->flr_stats.pbf_transmit_buffer[idx]++ < wait_ms/DEFAULT_WAIT_INTERVAL_MICSEC) in lm_cleanup_after_flr()
482 mm_wait(PFDEV(pdev), DEFAULT_WAIT_INTERVAL_MICSEC); in lm_cleanup_after_flr()
483 credit_last = REG_RD(PFDEV(pdev), pbf_reg_pN_credit); in lm_cleanup_after_flr()
484 inernal_freed_crd_last = REG_RD(PFDEV(pdev), pbf_reg_pN_internal_crd_freed); in lm_cleanup_after_flr()
488 … DbgMessage(pdev, FATAL, "CREDIT[%d] : c:%x\n", (idx == 2) ? 4 : idx, credit_last); in lm_cleanup_after_flr()
489 …DbgMessage(pdev, FATAL, "INTERNAL_CRD_FREED[%d]: c:%x\n", (idx == 2) ? 4 : idx, inernal_freed_crd_… in lm_cleanup_after_flr()
494 DbgMessage(pdev, FATAL, "%d*%dms waiting for PBF transmission buffer[%d] is flushed\n", in lm_cleanup_after_flr()
495 … pdev->flr_stats.pbf_transmit_buffer[idx], DEFAULT_WAIT_INTERVAL_MICSEC, (idx == 2) ? 4 : idx); in lm_cleanup_after_flr()
501 mm_wait(pdev, 10000*factor); in lm_cleanup_after_flr()
506 pcie_caps_offset = mm_get_cap_offset(pdev, PCI_CAP_PCIE); in lm_cleanup_after_flr()
510 mm_read_pci(pdev, pcie_caps_offset + PCIE_DEV_CTRL, &dev_control_and_status); in lm_cleanup_after_flr()
511 … DbgMessage(pdev, FATAL, "Device Control&Status of PCIe caps is %x\n",dev_control_and_status); in lm_cleanup_after_flr()
518 DbgMessage(pdev, FATAL, "Function mm_get_cap_offset is not implemented yet\n"); in lm_cleanup_after_flr()
529 if (IS_PFDEV(pdev)) in lm_cleanup_after_flr()
534 tmp = REG_RD(pdev,CFC_REG_WEAK_ENABLE_PF); in lm_cleanup_after_flr()
535 DbgMessage(pdev, FATAL, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n",tmp); in lm_cleanup_after_flr()
537 tmp = REG_RD(pdev,PBF_REG_DISABLE_PF); in lm_cleanup_after_flr()
538 DbgMessage(pdev, FATAL, "PBF_REG_DISABLE_PF is 0x%x\n",tmp); in lm_cleanup_after_flr()
540 tmp = REG_RD(pdev,IGU_REG_PCI_PF_MSI_EN); in lm_cleanup_after_flr()
541 DbgMessage(pdev, FATAL, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n",tmp); in lm_cleanup_after_flr()
543 tmp = REG_RD(pdev,IGU_REG_PCI_PF_MSIX_EN); in lm_cleanup_after_flr()
544 DbgMessage(pdev, FATAL, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n",tmp); in lm_cleanup_after_flr()
546 tmp = REG_RD(pdev,IGU_REG_PCI_PF_MSIX_FUNC_MASK); in lm_cleanup_after_flr()
547 DbgMessage(pdev, FATAL, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n",tmp); in lm_cleanup_after_flr()
549 tmp = REG_RD(pdev,PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in lm_cleanup_after_flr()
550 DbgMessage(pdev, FATAL, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n",tmp); in lm_cleanup_after_flr()
552 tmp = REG_RD(pdev,PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in lm_cleanup_after_flr()
553 DbgMessage(pdev, FATAL, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n",tmp); in lm_cleanup_after_flr()
555 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in lm_cleanup_after_flr()
556 mm_wait(pdev,999999); in lm_cleanup_after_flr()
558 m_en = REG_RD(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in lm_cleanup_after_flr()
559 DbgMessage(pdev, FATAL, "M:0x%x\n",m_en); in lm_cleanup_after_flr()
562 if (IS_VFDEV(pdev)) in lm_cleanup_after_flr()
566 lm_status = lm_vf_recycle_resc_in_pf(pdev); in lm_cleanup_after_flr()
567 lm_set_con_state(pdev, LM_SW_LEADING_RSS_CID(pdev), LM_CON_STATE_CLOSE); in lm_cleanup_after_flr()
571 lm_fl_reset_clear_inprogress(pdev); in lm_cleanup_after_flr()
580 u32_t lm_inc_cnt_grc_timeout_ignore(struct _lm_device_t *pdev, u32_t val) in lm_inc_cnt_grc_timeout_ignore() argument
582 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_inc_cnt_grc_timeout_ignore()
591 static int ecore_gunzip(struct _lm_device_t *pdev, const u8 *zbuf, int len) in ecore_gunzip() argument
594 UNREFERENCED_PARAMETER_(pdev); in ecore_gunzip()
601 static void ecore_reg_wr_ind(struct _lm_device_t *pdev, u32 addr, u32 val) in ecore_reg_wr_ind() argument
603 lm_reg_wr_ind(pdev, addr, val); in ecore_reg_wr_ind()
606 static void ecore_write_dmae_phys_len(struct _lm_device_t *pdev, in ecore_write_dmae_phys_len() argument
610 lm_dmae_reg_wr_phys(pdev, lm_dmae_get(pdev, LM_DMAE_DEFAULT)->context, in ecore_write_dmae_phys_len()
615 static void rbc_reset_workaround(lm_device_t *pdev) in rbc_reset_workaround() argument
622 if (CHIP_IS_E1x(pdev)) in rbc_reset_workaround()
625 mm_wait(pdev, (DEFAULT_WAIT_INTERVAL_MICSEC *2)); in rbc_reset_workaround()
627 val = REG_RD(pdev,MISC_REG_RESET_REG_1) ; in rbc_reset_workaround()
632 … REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP); in rbc_reset_workaround()
634 mm_wait(pdev, (DEFAULT_WAIT_INTERVAL_MICSEC *2)); in rbc_reset_workaround()
636 val = REG_RD(pdev,MISC_REG_RESET_REG_1) ; in rbc_reset_workaround()
638 … DbgMessage(pdev, WARN, "rbc_reset_workaround: MISC_REG_RESET_REG_1 after set= 0x%x\n",val); in rbc_reset_workaround()
645 void lm_set_nig_reset_called(struct _lm_device_t *pdev) in lm_set_nig_reset_called() argument
647 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_set_nig_reset_called()
653 void lm_clear_nig_reset_called(struct _lm_device_t *pdev) in lm_clear_nig_reset_called() argument
655 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_clear_nig_reset_called()
661 u8_t lm_is_nig_reset_called(struct _lm_device_t *pdev) in lm_is_nig_reset_called() argument
663 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_is_nig_reset_called()
672 void lm_reset_path( IN struct _lm_device_t *pdev, in lm_reset_path() argument
701 const u8_t idx_max = CHIP_IS_E3(pdev) ? ARRSIZE(reg_arr_e3) : ARRSIZE(reg_arr_e1_e2) ; in lm_reset_path()
702 const u32_t* reg_arr_ptr = CHIP_IS_E3(pdev) ? reg_arr_e3 : reg_arr_e1_e2 ; in lm_reset_path()
704 DbgMessage(pdev, WARN, "lm_reset_path:%sreset [begin]\n", b_with_nig ? " (with NIG) " : " "); in lm_reset_path()
714 restore_arr[idx] = REG_RD( pdev, reg_arr_ptr[idx] ); in lm_reset_path()
715 REG_WR( pdev, reg_arr_ptr[idx], 0 ); in lm_reset_path()
727 mm_wait( pdev, 200000 ); in lm_reset_path()
734 val |= ( REG_RD( pdev, offset ) ) << idx ; in lm_reset_path()
739 if (lm_is_mcp_detected(pdev)) in lm_reset_path()
746 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear ); in lm_reset_path()
748 if (CHIP_IS_E3(pdev)) in lm_reset_path()
756 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, reg_2_clear); in lm_reset_path()
760 lm_set_nig_reset_called(pdev); in lm_reset_path()
762 … REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_SET, MISC_REGISTERS_RESET_REG_1_RST_NIG); in lm_reset_path()
767 REG_WR( pdev, reg_arr_ptr[idx], restore_arr[idx] ); in lm_reset_path()
771 pdev->vars.b_is_dmae_ready = FALSE; in lm_reset_path()
773 DbgMessage(pdev, WARN, "lm_reset_path:%sreset [end]\n", b_with_nig ? " (with NIG) ": " "); in lm_reset_path()
781 …DbgMessage(pdev, WARN, "lm_reset_path:%sreset rbcp wait [begin]\n", b_with_nig ? " (with NIG) ": "… in lm_reset_path()
782 rbc_reset_workaround(pdev); in lm_reset_path()
783 …DbgMessage(pdev, WARN, "lm_reset_path:%sreset rbcp wait [end]\n", b_with_nig ? " (with NIG) ": " "… in lm_reset_path()
797 static void lm_reset_prev_interrupted_dmae(struct _lm_device_t *pdev) in lm_reset_prev_interrupted_dmae() argument
801 if ( CHIP_IS_E1x(pdev) ) in lm_reset_prev_interrupted_dmae()
808 val = REG_RD(pdev, PGLUE_B_REG_PGLUE_B_INT_STS); in lm_reset_prev_interrupted_dmae()
812 …DbgMessage(pdev, WARNi, "lm_reset_prev_interrupted_dmae: was error bit was found to be set in pglu… in lm_reset_prev_interrupted_dmae()
813 REG_WR(pdev, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << FUNC_ID(pdev)); in lm_reset_prev_interrupted_dmae()
818 static u8_t lm_reset_device_if_undi_func_hide_helper( struct _lm_device_t *pdev, in lm_reset_device_if_undi_func_hide_helper() argument
852 LM_MFCFG_READ(pdev, offset, &mf_config); in lm_reset_device_if_undi_func_hide_helper()
862 void lm_reset_device_if_undi_active(struct _lm_device_t *pdev) in lm_reset_device_if_undi_active() argument
879 const lm_chip_port_mode_t port_mode = CHIP_PORT_MODE(pdev); in lm_reset_device_if_undi_active()
882 …const u8_t func_mb_id = FUNC_MAILBOX_ID(pdev); // Stor… in lm_reset_device_if_undi_active()
883 const u8_t path_id = PATH_ID(pdev); in lm_reset_device_if_undi_active()
890 lm_reset_prev_interrupted_dmae(pdev); in lm_reset_device_if_undi_active()
898 if( LM_STATUS_SUCCESS == lm_hw_lock(pdev, HW_LOCK_RESOURCE_RESET, TRUE) ) in lm_reset_device_if_undi_active()
900 rst_dorq_val = REG_RD(pdev,MISC_REG_RESET_REG_1); in lm_reset_device_if_undi_active()
905 val = REG_RD(pdev,DORQ_REG_NORM_CID_OFST); in lm_reset_device_if_undi_active()
908 … DbgMessage(pdev, WARN, "lm_reset_device_if_undi_active: DORQ_REG_NORM_CID_OFST val = 0x%x\n",val); in lm_reset_device_if_undi_active()
912 REG_WR( pdev, DORQ_REG_NORM_CID_OFST ,0 ); in lm_reset_device_if_undi_active()
920 lm_hw_unlock_ex(pdev, HW_LOCK_RESOURCE_RESET, FALSE ); in lm_reset_device_if_undi_active()
932 … DbgMessage(pdev, WARN, "lm_reset_device_if_undi_active: UNDI is active! need to reset device\n"); in lm_reset_device_if_undi_active()
934 if (GET_FLAGS( pdev->params.test_mode, TEST_MODE_NO_MCP)) in lm_reset_device_if_undi_active()
946 …vnics_per_port = (LM_CHIP_PORT_MODE_4 == port_mode )? 2 : pdev->params.vnics_per_port; // for 4-po… in lm_reset_device_if_undi_active()
952 vnics_per_port = pdev->params.vnics_per_port;; // Always symetric in case not 4 port mode. in lm_reset_device_if_undi_active()
979 if( CHIP_IS_E1(pdev) ) in lm_reset_device_if_undi_active()
986 b_hidden = lm_reset_device_if_undi_func_hide_helper( pdev, in lm_reset_device_if_undi_active()
987 CHIP_NUM(pdev), in lm_reset_device_if_undi_active()
1005 … pdev->params.pfunc_mb_id = FUNC_MAILBOX_ID_PARAM( port, vnic, CHIP_NUM(pdev), port_mode ); in lm_reset_device_if_undi_active()
1007 if( !CHIP_IS_E1(pdev) ) in lm_reset_device_if_undi_active()
1009 b_hidden = lm_reset_device_if_undi_func_hide_helper( pdev, in lm_reset_device_if_undi_active()
1010 CHIP_NUM(pdev), in lm_reset_device_if_undi_active()
1024 lm_mcp_cmd_init(pdev); in lm_reset_device_if_undi_active()
1026 resp = lm_loader_lock(pdev, opcode_arr[opcode_idx] ); in lm_reset_device_if_undi_active()
1037 if ( CHIP_IS_E1x(pdev) ) in lm_reset_device_if_undi_active()
1041 REG_WR(pdev,HC_REG_CONFIG_0+(4*port),0x1000); in lm_reset_device_if_undi_active()
1048 REG_WR(pdev,MISC_REG_AEU_MASK_ATTN_FUNC_0+(4*port),0); in lm_reset_device_if_undi_active()
1058 swap_val = REG_RD(pdev,NIG_REG_PORT_SWAP); in lm_reset_device_if_undi_active()
1059 swap_en = REG_RD(pdev,NIG_REG_STRAP_OVERRIDE); in lm_reset_device_if_undi_active()
1062 lm_reset_path( pdev, TRUE ); in lm_reset_device_if_undi_active()
1065 REG_WR(pdev,NIG_REG_PORT_SWAP,swap_val); in lm_reset_device_if_undi_active()
1066 REG_WR(pdev,NIG_REG_STRAP_OVERRIDE,swap_en); in lm_reset_device_if_undi_active()
1069 lm_loader_unlock(pdev, opcode_arr[opcode_idx], ¶m_loader ) ; in lm_reset_device_if_undi_active()
1081 pdev->params.pfunc_mb_id = func_mb_id; in lm_reset_device_if_undi_active()
1083 lm_hw_unlock(pdev, HW_LOCK_RESOURCE_RESET); in lm_reset_device_if_undi_active()
1100 lm_status_t lm_disable_function_in_nig(struct _lm_device_t *pdev) in lm_disable_function_in_nig() argument
1106 …const u32_t nig_mem_enable_base_offset = (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : NIG_REG_… in lm_disable_function_in_nig()
1107 …const u32_t nig_mem2_enable_base_offset = (PORT_ID(pdev) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE : NIG_R… in lm_disable_function_in_nig()
1109 if (!IS_MULTI_VNIC(pdev)) in lm_disable_function_in_nig()
1111 DbgBreakIf(!IS_MULTI_VNIC(pdev)); in lm_disable_function_in_nig()
1115 if (IS_MF_SD_MODE(pdev)) in lm_disable_function_in_nig()
1118 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_EN : NIG_REG_LLH0_FUNC_EN), 0); in lm_disable_function_in_nig()
1119 …lm_set_func_en(pdev, FALSE); /* if function should be enabled it will be set when wol is configure… in lm_disable_function_in_nig()
1121 else if (IS_MF_SI_MODE(pdev) || IS_MF_AFEX_MODE(pdev)) in lm_disable_function_in_nig()
1127 REG_WR(pdev, nig_mem_enable_base_offset + nig_entry_idx*sizeof(u32_t), 0); in lm_disable_function_in_nig()
1131 REG_WR(pdev, nig_mem2_enable_base_offset + nig_entry_idx*sizeof(u32_t), 0); in lm_disable_function_in_nig()
1151 lm_status_t lm_function_stop(struct _lm_device_t *pdev) in lm_function_stop() argument
1157 DbgMessage(pdev, INFORMeq|INFORMl2sp, "#lm_function_stop\n"); in lm_function_stop()
1160 pdev->eq_info.function_state = FUNCTION_STOP_POSTED; in lm_function_stop()
1162 lm_status = lm_sq_post(pdev, in lm_function_stop()
1174 lm_status = lm_wait_state_change(pdev, &pdev->eq_info.function_state, FUNCTION_STOP_COMPLETED); in lm_function_stop()
1179 lm_status_t lm_chip_stop(struct _lm_device_t *pdev) in lm_chip_stop() argument
1182 const u32_t fwd_cid = FWD_CID(pdev); in lm_chip_stop()
1185 if (IS_VFDEV(pdev)) in lm_chip_stop()
1190 if (lm_fl_reset_is_inprogress(pdev)) in lm_chip_stop()
1192 lm_set_con_state(pdev, fwd_cid, LM_CON_STATE_CLOSE); in lm_chip_stop()
1193 DbgMessage(pdev, WARN, "lm_chip_stop: Under FLR: \"close\" leading and FWD conns.\n"); in lm_chip_stop()
1196 if ((lm_status = lm_close_forward_con(pdev)) != LM_STATUS_SUCCESS) in lm_chip_stop()
1198 DbgMessage(pdev, FATAL, "lm_chip_stop: ERROR closing FWD connection!!!\n"); in lm_chip_stop()
1201 if (pdev->params.multi_vnics_mode) in lm_chip_stop()
1203 lm_disable_function_in_nig(pdev); in lm_chip_stop()
1206 lm_status = lm_function_stop(pdev); in lm_chip_stop()
1210 DbgMessage(pdev, FATAL, "lm_chip_stop: ERROR closing function!!!\n"); in lm_chip_stop()
1215 lm_sq_change_state(pdev, SQ_STATE_BLOCKED); in lm_chip_stop()
1222 static void clear_pf_enable(lm_device_t *pdev) in clear_pf_enable() argument
1224 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in clear_pf_enable()
1225 REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); in clear_pf_enable()
1229 static void uninit_pxp2_blk(lm_device_t *pdev) in uninit_pxp2_blk() argument
1234 if(ERR_IF(!pdev)) in uninit_pxp2_blk()
1249 temp = FUNC_ID(pdev) * ILT_NUM_PAGE_ENTRIES_PER_FUNC; in uninit_pxp2_blk()
1250 rq_onchip_at_reg = CHIP_IS_E1(pdev) ? PXP2_REG_RQ_ONCHIP_AT : PXP2_REG_RQ_ONCHIP_AT_B0; in uninit_pxp2_blk()
1251 on_chip_addr2_val = CHIP_IS_E1x(pdev)? 0 : ONCHIP_ADDR0_VALID(); in uninit_pxp2_blk()
1255 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,0); in uninit_pxp2_blk()
1256 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,on_chip_addr2_val); in uninit_pxp2_blk()
1259 PXP2_SET_FIRST_LAST_ILT(pdev, CDU, 0, 0); in uninit_pxp2_blk()
1260 PXP2_SET_FIRST_LAST_ILT(pdev, QM, 0, 0); in uninit_pxp2_blk()
1261 PXP2_SET_FIRST_LAST_ILT(pdev, SRC, 0, 0); in uninit_pxp2_blk()
1264 if (!CHIP_IS_E1x(pdev) && VNIC_ID(pdev) == 3) in uninit_pxp2_blk()
1266 PXP2_SET_FIRST_LAST_ILT(pdev, TM, 0, ILT_NUM_PAGE_ENTRIES - 1); in uninit_pxp2_blk()
1270 PXP2_SET_FIRST_LAST_ILT(pdev, TM, 0, 0); in uninit_pxp2_blk()
1286 lm_status_t lm_reset_function_part(struct _lm_device_t *pdev, u8_t cleanup) in lm_reset_function_part() argument
1291 const u8_t port = PORT_ID(pdev); in lm_reset_function_part()
1292 const u8_t func = FUNC_ID(pdev); in lm_reset_function_part()
1296 if (IS_MULTI_VNIC(pdev) && IS_PMF(pdev)) in lm_reset_function_part()
1298 DbgMessage(pdev, WARN, in lm_reset_function_part()
1299 "lm_reset_function_part: Func %d is no longer PMF \n", FUNC_ID(pdev)); in lm_reset_function_part()
1301 if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) in lm_reset_function_part()
1303 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0); in lm_reset_function_part()
1304 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0); in lm_reset_function_part()
1308 REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, 0); in lm_reset_function_part()
1309 REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, 0); in lm_reset_function_part()
1311 MM_ACQUIRE_PHY_LOCK(pdev); in lm_reset_function_part()
1312 lm_stats_on_pmf_update(pdev,FALSE); in lm_reset_function_part()
1313 MM_RELEASE_PHY_LOCK(pdev); in lm_reset_function_part()
1317 if (INTR_BLK_TYPE(pdev) == INTR_BLK_HC) in lm_reset_function_part()
1319 REG_WR(pdev,HC_REG_CONFIG_0+(4*port),0x1000); in lm_reset_function_part()
1323 REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER + (4*port),0); in lm_reset_function_part()
1326 mm_wait(pdev, LM_TIMERS_SCAN_TIME); /* 1m */ in lm_reset_function_part()
1328 val=REG_RD(pdev,TM_REG_LIN0_SCAN_ON+(4*port)); in lm_reset_function_part()
1336 if(CHIP_IS_E1x(pdev) && lm_reset_is_inprogress(pdev) ) in lm_reset_function_part()
1342 DbgMessage(pdev, INFORMi, "timer status on %d \n",val); in lm_reset_function_part()
1345 if (!lm_reset_is_inprogress(pdev)) in lm_reset_function_part()
1352 lm_stats_fw_reset(pdev) ; in lm_reset_function_part()
1357 if (!CHIP_IS_E1x(pdev)) in lm_reset_function_part()
1359 clear_pf_enable(pdev); in lm_reset_function_part()
1360 pdev->vars.b_is_dmae_ready = FALSE; /* Can't access dmae since bus-master is disabled */ in lm_reset_function_part()
1362 uninit_pxp2_blk(pdev); in lm_reset_function_part()
1367 if (!lm_reset_is_inprogress(pdev)) in lm_reset_function_part()
1369 LM_INTMEM_WRITE8(pdev, XSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 0, BAR_XSTRORM_INTMEM); in lm_reset_function_part()
1370 LM_INTMEM_WRITE8(pdev, CSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 0, BAR_CSTRORM_INTMEM); in lm_reset_function_part()
1371 LM_INTMEM_WRITE8(pdev, TSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 0, BAR_TSTRORM_INTMEM); in lm_reset_function_part()
1372 LM_INTMEM_WRITE8(pdev, USTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 0, BAR_USTRORM_INTMEM); in lm_reset_function_part()
1374 LM_FOREACH_SB_ID(pdev, sb_id) in lm_reset_function_part()
1376 LM_INTMEM_WRITE8(pdev, CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(LM_FW_SB_ID(pdev, sb_id)), in lm_reset_function_part()
1380 LM_INTMEM_WRITE8(pdev, CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), in lm_reset_function_part()
1389 lm_status_t lm_reset_port_part(struct _lm_device_t *pdev) in lm_reset_port_part() argument
1393 const u8_t port = PORT_ID(pdev); in lm_reset_port_part()
1398 REG_WR(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*port,0x0); in lm_reset_port_part()
1401 REG_WR(pdev, NIG_REG_LLH0_BRB1_DRV_MASK + 4*port,0x0); in lm_reset_port_part()
1404 REG_WR(pdev, NIG_REG_LLH0_BRB1_NOT_MCP + 4*32*port,0x0); in lm_reset_port_part()
1408 if(IS_DCB_ENABLED(pdev)) in lm_reset_port_part()
1410 elink_ets_disabled(&pdev->params.link, in lm_reset_port_part()
1411 &pdev->vars.link); in lm_reset_port_part()
1415 MM_ACQUIRE_PHY_LOCK(pdev); in lm_reset_port_part()
1416 lm_reset_link(pdev); in lm_reset_port_part()
1417 MM_RELEASE_PHY_LOCK(pdev); in lm_reset_port_part()
1419 REG_WR(pdev,MISC_REG_AEU_MASK_ATTN_FUNC_0+(4*port),0); in lm_reset_port_part()
1422 if (!lm_reset_is_inprogress(pdev)) in lm_reset_port_part()
1425 mm_wait(pdev,LM_UNLOAD_TIME); in lm_reset_port_part()
1427 val=REG_RD(pdev,BRB1_REG_PORT_NUM_OCC_BLOCKS_0+(4*port)); in lm_reset_port_part()
1431 …DbgMessage(pdev, INFORMi, "lm_reset_function_part BRB1 is not empty %d blooks are occupied\n",val); in lm_reset_port_part()
1436 if (!CHIP_IS_E1x(pdev)) in lm_reset_port_part()
1438 clear_pf_enable(pdev); in lm_reset_port_part()
1439 pdev->vars.b_is_dmae_ready = FALSE; /* Can't access dmae since bus-master is disabled */ in lm_reset_port_part()
1442 uninit_pxp2_blk(pdev); in lm_reset_port_part()
1460 static INLINE u8_t lm_reset_nig_valid_offset(lm_device_t * pdev, in lm_reset_nig_valid_offset() argument
1474 if (CHIP_IS_E1(pdev)) in lm_reset_nig_valid_offset()
1478 else if (CHIP_IS_E1H(pdev)) in lm_reset_nig_valid_offset()
1482 else if (CHIP_IS_E2(pdev)) in lm_reset_nig_valid_offset()
1494 lm_status_t lm_pretend_func( struct _lm_device_t *pdev, u16_t pretend_func_num ) in lm_pretend_func() argument
1498 if (CHIP_IS_E1(pdev)) in lm_pretend_func()
1503 if(CHIP_IS_E1H(pdev) && (pretend_func_num >= E1H_FUNC_MAX)) in lm_pretend_func()
1508 switch (ABS_FUNC_ID(pdev)) in lm_pretend_func()
1553 REG_WR(pdev, offset, pretend_func_num ); in lm_pretend_func()
1554 REG_WAIT_VERIFY_VAL(pdev, offset, pretend_func_num, 200); in lm_pretend_func()
1579 static void lm_reset_nig_process(IN struct _lm_device_t *pdev, in lm_reset_nig_process() argument
1591 if (!IS_MF_SD_MODE(pdev)) in lm_reset_nig_process()
1600 if (lm_reset_nig_valid_offset(pdev, data, LM_RESET_NIG_OP_RESTORE)) in lm_reset_nig_process()
1604 reg_port_arr[idx] = lm_get_func_en(pdev, func_id); in lm_reset_nig_process()
1612 static void lm_reset_nig_values_for_func_save_restore( IN struct _lm_device_t *pdev, in lm_reset_nig_values_for_func_save_restore() argument
1626 u8_t abs_func_id = ABS_FUNC_ID(pdev); in lm_reset_nig_values_for_func_save_restore()
1640 lm_reset_nig_process(pdev,reg_offsets_port,reg_port_arr,reg_port_arr_size, pretend_func_id); in lm_reset_nig_values_for_func_save_restore()
1650 lm_pretend_func( pdev, pretend_func_id ); in lm_reset_nig_values_for_func_save_restore()
1656 if (lm_reset_nig_valid_offset(pdev, data, save_or_restore)) in lm_reset_nig_values_for_func_save_restore()
1660 reg_port_arr[idx] = REG_RD(pdev, data->offset ); in lm_reset_nig_values_for_func_save_restore()
1664 REG_WR(pdev, data->offset, reg_port_arr[idx] ); in lm_reset_nig_values_for_func_save_restore()
1675 REG_RD_IND( pdev, offset, &val_32[0] ); in lm_reset_nig_values_for_func_save_restore()
1676 REG_RD_IND( pdev, offset+4, &val_32[1] ); in lm_reset_nig_values_for_func_save_restore()
1684 REG_WR_IND( pdev, offset, val_32[0] ); in lm_reset_nig_values_for_func_save_restore()
1685 REG_WR_IND( pdev, offset+4, val_32[1] ); in lm_reset_nig_values_for_func_save_restore()
1691 lm_pretend_func( pdev, abs_func_id ); in lm_reset_nig_values_for_func_save_restore()
1703 lm_reset_device_with_nig(struct _lm_device_t *pdev) in lm_reset_device_with_nig() argument
1708 …u8_t abs_func_id = ABS_FUNC_ID(pdev); // f… in lm_reset_device_with_nig()
1710 const u8_t path_id = PATH_ID(pdev); in lm_reset_device_with_nig()
1711 const u32_t chip_num = CHIP_NUM(pdev); in lm_reset_device_with_nig()
1712 const lm_chip_port_mode_t chip_port_mode = CHIP_PORT_MODE(pdev); in lm_reset_device_with_nig()
1757 …abs_func_vector = lm_get_abs_func_vector( chip_num, chip_port_mode, IS_MULTI_VNIC(pdev), path_id ); in lm_reset_device_with_nig()
1777 lm_reset_nig_values_for_func_save_restore( pdev, in lm_reset_device_with_nig()
1793 if (lm_reset_nig_valid_offset(pdev, &non_split_offsets[idx], LM_RESET_NIG_OP_SAVE)) in lm_reset_device_with_nig()
1795 non_split_vals[idx] = REG_RD( pdev, non_split_offsets[idx].offset ); in lm_reset_device_with_nig()
1801 lm_reset_path( pdev, TRUE ); in lm_reset_device_with_nig()
1806 … if (lm_reset_nig_valid_offset(pdev, &non_split_offsets[idx], LM_RESET_NIG_OP_RESTORE)) in lm_reset_device_with_nig()
1808 REG_WR(pdev, non_split_offsets[idx].offset, non_split_vals[idx]); in lm_reset_device_with_nig()
1819 lm_reset_common_part(struct _lm_device_t *pdev) in lm_reset_common_part() argument
1822 if (lm_pm_reset_is_inprogress(pdev)) in lm_reset_common_part()
1825 lm_reset_device_with_nig(pdev); in lm_reset_common_part()
1829 lm_reset_path( pdev, FALSE ); in lm_reset_common_part()
1835 lm_er_disable_close_the_gate(pdev); in lm_reset_common_part()
1838 void lm_chip_reset(struct _lm_device_t *pdev, lm_reason_t reason) in lm_chip_reset() argument
1843 u32_t enabled_wols = mm_get_wol_flags(pdev); in lm_chip_reset()
1845 DbgMessage(pdev, INFORMi , "### lm_chip_reset\n"); in lm_chip_reset()
1848 if (IS_VFDEV(pdev)) in lm_chip_reset()
1850 lm_status_t lm_status = lm_vf_chip_reset(pdev,reason); in lm_chip_reset()
1853 DbgMessage(pdev, FATAL, "lm_chip_reset: ERROR (%d) resetting VF!!!\n",lm_status); in lm_chip_reset()
1877 if( GET_FLAGS( pdev->hw_info.port_feature_config, PORT_FEATURE_WOL_ENABLED ) ) in lm_chip_reset()
1893 if ( !CHIP_IS_E1(pdev) ) in lm_chip_reset()
1895 if (CHIP_IS_E2(pdev) || CHIP_IS_E1H(pdev)) in lm_chip_reset()
1897 val = REG_RD( pdev, MISC_REG_E1HMF_MODE); in lm_chip_reset()
1902 val = REG_RD( pdev, MISC_REG_E1HMF_MODE_P0 + PORT_ID(pdev)*4); in lm_chip_reset()
1906 if (!lm_fl_reset_is_inprogress(pdev)) in lm_chip_reset()
1908 DbgBreakIf( pdev->params.multi_vnics_mode ^ val ); in lm_chip_reset()
1912 if (lm_fl_reset_is_inprogress(pdev)) in lm_chip_reset()
1914 if (TEST_MODE_NO_MCP == GET_FLAGS(pdev->params.test_mode, TEST_MODE_NO_MCP)) in lm_chip_reset()
1916 DbgMessage(pdev, FATAL, "lm_chip_reset under FLR: NO MCP\n"); in lm_chip_reset()
1917 lm_loader_lock(pdev, opcode); in lm_chip_reset()
1918 lm_loader_unlock(pdev, opcode, NULL); in lm_chip_reset()
1921 DbgMessage(pdev, FATAL, "lm_chip_reset under FLR: return\n"); in lm_chip_reset()
1926 lm_set_d3_mpkt(pdev, enabled_wols) ; in lm_chip_reset()
1928 resp = lm_loader_lock(pdev, opcode ) ; in lm_chip_reset()
1930 if (!IS_ASSIGNED_TO_VM_PFDEV(pdev)) in lm_chip_reset()
1932 lm_pcie_state_save_for_d3(pdev); in lm_chip_reset()
1936 lm_set_d3_nwuf(pdev, enabled_wols) ; in lm_chip_reset()
1941 lm_reset_function_part(pdev, TRUE /* cleanup*/); in lm_chip_reset()
1944 lm_reset_function_part(pdev, FALSE /* cleanup */ ); in lm_chip_reset()
1945 lm_reset_port_part(pdev); in lm_chip_reset()
1948 lm_reset_function_part(pdev, FALSE /* cleanup */); in lm_chip_reset()
1949 lm_reset_port_part(pdev); in lm_chip_reset()
1951 mm_dbus_stop_if_started(pdev); in lm_chip_reset()
1952 lm_reset_common_part(pdev); in lm_chip_reset()
1955 DbgMessage(pdev, WARN, "wrong loader response=0x%x\n", resp); in lm_chip_reset()
1959 pdev->vars.b_is_dmae_ready = FALSE ; in lm_chip_reset()
1962 pdev->vars.is_pmf = NOT_PMF; in lm_chip_reset()
1964 resp = lm_loader_unlock(pdev, opcode, NULL ) ; in lm_chip_reset()
1968 DbgMessage(pdev, WARN, "wrong loader response=0x%x\n", resp); in lm_chip_reset()
1983 lm_status_t lm_function_start(struct _lm_device_t *pdev) in lm_function_start() argument
1988 DbgMessage(pdev, INFORMeq|INFORMl2sp, "#lm_function_start\n"); in lm_function_start()
1990 pdev->eq_info.function_state = FUNCTION_START_POSTED; in lm_function_start()
1992 if (CHK_NULL(pdev) || CHK_NULL(pdev->slowpath_info.slowpath_data.func_start_data)) in lm_function_start()
1997 func_start_data = pdev->slowpath_info.slowpath_data.func_start_data; in lm_function_start()
1999 if (pdev->params.multi_vnics_mode) in lm_function_start()
2001 DbgBreakIf(pdev->params.mf_mode >= MAX_MF_MODE); in lm_function_start()
2002 func_start_data->function_mode = pdev->params.mf_mode; in lm_function_start()
2009 func_start_data->sd_vlan_tag = mm_cpu_to_le16(pdev->params.ovlan); in lm_function_start()
2019 if (IS_MF_SD_MODE(pdev) && IS_SD_BD_MODE(pdev)) in lm_function_start()
2021 const u8_t port = PORT_ID(pdev); in lm_function_start()
2025 REG_WR(pdev, PRS_REG_VLAN_TYPE_0, 0x88a8); in lm_function_start()
2026 REG_WR(pdev, PBF_REG_VLAN_TYPE_0, 0x88a8); in lm_function_start()
2027 REG_WR(pdev, offset , 0x88a8); in lm_function_start()
2030 func_start_data->sd_vlan_eth_type = mm_cpu_to_le16(pdev->params.sd_vlan_eth_type); in lm_function_start()
2032 func_start_data->path_id = PATH_ID(pdev); in lm_function_start()
2036 if(MM_DCB_MP_L2_IS_ENABLE(pdev)) in lm_function_start()
2048 if (ENCAP_OFFLOAD_DISABLED == pdev->encap_info.current_encap_offload_state) in lm_function_start()
2060 if ((IS_SD_UFP_MODE(pdev) || IS_SD_BD_MODE(pdev)) && in lm_function_start()
2061 GET_FLAGS(pdev->params.mf_proto_support_flags, LM_PROTO_SUPPORT_FCOE)) in lm_function_start()
2069 if (IS_SD_UFP_MODE(pdev) || IS_SD_BD_MODE(pdev)) in lm_function_start()
2076 lm_status = lm_sq_post(pdev, in lm_function_start()
2081 LM_SLOWPATH_PHYS(pdev, func_start_data).as_u64); in lm_function_start()
2088 lm_status = lm_wait_state_change(pdev, &pdev->eq_info.function_state, FUNCTION_START_COMPLETED); in lm_function_start()
2093 lm_status_t lm_chip_start(struct _lm_device_t *pdev) in lm_chip_start() argument
2096 u8_t min_bw = (u8_t)pdev->params.bandwidth_min; in lm_chip_start()
2097 u8_t max_bw = (u8_t)pdev->params.bandwidth_max; in lm_chip_start()
2099 DbgMessage(pdev, INFORMi, "lm_chip_start\n"); in lm_chip_start()
2101 if (IS_VFDEV(pdev)) in lm_chip_start()
2110 lm_status = lm_mcp_set_mf_bw(pdev, min_bw, max_bw); in lm_chip_start()
2118 lm_sq_change_state(pdev, SQ_STATE_NORMAL); in lm_chip_start()
2120 lm_status = lm_function_start(pdev); in lm_chip_start()
2127 REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER + 4*PORT_ID(pdev),1); in lm_chip_start()
2129 lm_status = lm_establish_forward_con(pdev); in lm_chip_start()
2138 DbgMessage(pdev, FATAL, "lm_chip_start on_err:\n"); in lm_chip_start()
2139 lm_function_stop(pdev); in lm_chip_start()
2140 REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER + 4*PORT_ID(pdev),0); in lm_chip_start()
2158 void lm_setup_read_mgmt_stats_ptr( struct _lm_device_t *pdev, IN const u32_t mailbox_num, OUT u32_t… in lm_setup_read_mgmt_stats_ptr() argument
2160 if (GET_FLAGS( pdev->params.test_mode, TEST_MODE_NO_MCP)) in lm_setup_read_mgmt_stats_ptr()
2180 LM_SHMEM_READ(pdev, in lm_setup_read_mgmt_stats_ptr()
2188 …DbgMessage(pdev, FATAL , "lm_read_fw_stats_ptr: boot code earlier than v4.0.8 fw_mb=%p-->NULL\n", … in lm_setup_read_mgmt_stats_ptr()
2191 …DbgMessage(pdev, WARN , "lm_read_fw_stats_ptr: pdev->vars.fw_func_stats_ptr=%p\n", *fw_func_stats_… in lm_setup_read_mgmt_stats_ptr()
2197 LM_SHMEM_READ(pdev, in lm_setup_read_mgmt_stats_ptr()
2199 port_mb[PORT_ID(pdev)].port_stx), in lm_setup_read_mgmt_stats_ptr()
2202 …DbgMessage(pdev, WARN, "lm_read_fw_stats_ptr: pdev->vars.fw_port_stats_ptr=%p\n", *fw_port_stats_p… in lm_setup_read_mgmt_stats_ptr()
2216 lm_init_get_modes_bitmap(struct _lm_device_t *pdev) in lm_init_get_modes_bitmap() argument
2221 if (CHIP_REV_IS_ASIC(pdev)) in lm_init_get_modes_bitmap()
2225 else if (CHIP_REV_IS_FPGA(pdev)) in lm_init_get_modes_bitmap()
2229 else if (CHIP_REV_IS_EMUL(pdev)) in lm_init_get_modes_bitmap()
2238 if (CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_4) in lm_init_get_modes_bitmap()
2242 …else if ((CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_2)||(CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE… in lm_init_get_modes_bitmap()
2251 DbgMessage(pdev, INFORMi, "chipid is 0x%x, rev is 0x%x\n", CHIP_NUM(pdev), CHIP_REV(pdev)); in lm_init_get_modes_bitmap()
2252 if (CHIP_IS_E2(pdev)) in lm_init_get_modes_bitmap()
2254 DbgMessage(pdev, INFORMi, "chip is E2\n"); in lm_init_get_modes_bitmap()
2257 else if (CHIP_IS_E3(pdev)) in lm_init_get_modes_bitmap()
2259 DbgMessage(pdev, INFORMi, "chip is E3\n"); in lm_init_get_modes_bitmap()
2261 if (CHIP_REV_IS_ASIC(pdev)) in lm_init_get_modes_bitmap()
2263 DbgMessage(pdev, INFORMi, "chip is ASIC\n"); in lm_init_get_modes_bitmap()
2264 chip_rev = CHIP_REV(pdev); in lm_init_get_modes_bitmap()
2268 chip_rev = CHIP_REV_SIM(pdev); in lm_init_get_modes_bitmap()
2269 DbgMessage(pdev, INFORMi, "chip is EMUL/FPGA. modified chip_rev is 0x%x\n", chip_rev); in lm_init_get_modes_bitmap()
2274 DbgMessage(pdev, INFORMi, "chip is E3 Ax\n"); in lm_init_get_modes_bitmap()
2279 DbgMessage(pdev, INFORMi, "chip is E3 Bx\n"); in lm_init_get_modes_bitmap()
2283 switch (pdev->params.e3_cos_modes) in lm_init_get_modes_bitmap()
2302 DbgMessage(pdev, INFORMi, "chip is not E2/E3\n"); in lm_init_get_modes_bitmap()
2306 if (pdev->params.multi_vnics_mode) in lm_init_get_modes_bitmap()
2309 switch(pdev->params.mf_mode) in lm_init_get_modes_bitmap()
2359 lm_ncsi_get_shmem_address( struct _lm_device_t *pdev) in lm_ncsi_get_shmem_address() argument
2366 LM_SHMEM2_READ( pdev, offset, &shmem2_size ); in lm_ncsi_get_shmem_address()
2372 LM_SHMEM2_READ(pdev, offset, &ncsi_oem_data_addr); in lm_ncsi_get_shmem_address()
2390 lm_ncsi_drv_ver_to_scratchpad( struct _lm_device_t *pdev, u32_t ver_32 ) in lm_ncsi_drv_ver_to_scratchpad() argument
2392 const u32_t ncsi_oem_data_addr = lm_ncsi_get_shmem_address(pdev); in lm_ncsi_drv_ver_to_scratchpad()
2400 REG_WR(pdev, ncsi_oem_data_addr + offset, ver_32); in lm_ncsi_drv_ver_to_scratchpad()
2406 lm_ncsi_prev_drv_ver_is_win8_inbox( struct _lm_device_t *pdev) in lm_ncsi_prev_drv_ver_is_win8_inbox() argument
2408 const u32_t ncsi_oem_data_addr = lm_ncsi_get_shmem_address(pdev); in lm_ncsi_prev_drv_ver_is_win8_inbox()
2435 val = REG_RD(pdev, ncsi_oem_data_addr + offset_unused); in lm_ncsi_prev_drv_ver_is_win8_inbox()
2448 val = REG_RD(pdev, ncsi_oem_data_addr + offset + str_idx); in lm_ncsi_prev_drv_ver_is_win8_inbox()
2508 lm_ncsi_fcoe_cap_to_scratchpad( struct _lm_device_t *pdev) in lm_ncsi_fcoe_cap_to_scratchpad() argument
2510 const u32_t ncsi_oem_data_addr = lm_ncsi_get_shmem_address(pdev); in lm_ncsi_fcoe_cap_to_scratchpad()
2511 const u8_t path_id = PATH_ID(pdev); in lm_ncsi_fcoe_cap_to_scratchpad()
2512 const u8_t port_id = PORT_ID(pdev); in lm_ncsi_fcoe_cap_to_scratchpad()
2515 const u32_t bc_rev = LM_GET_BC_REV_MAJOR(pdev); in lm_ncsi_fcoe_cap_to_scratchpad()
2517 …u32_t* buf32 = (u32_t*)(&pdev->vars.stats.stats_mirror.stats_d… in lm_ncsi_fcoe_cap_to_scratchpad()
2518 …static const u8_t idx_max = sizeof(pdev->vars.stats.stats_mirror.stats_drv.… in lm_ncsi_fcoe_cap_to_scratchpad()
2521 … sizeof(pdev->vars.stats.stats_mirror.stats_drv.drv_info_to_shmem.fcoe_capabilities) ); in lm_ncsi_fcoe_cap_to_scratchpad()
2542 REG_WR(pdev, in lm_ncsi_fcoe_cap_to_scratchpad()
2550 static void init_misc_common(lm_device_t *pdev) in init_misc_common() argument
2556 if (CHIP_IS_E3(pdev)) in init_misc_common()
2564 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,reset_reg_1_val); in init_misc_common()
2566 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_2_SET,reset_reg_2_val); in init_misc_common()
2568 ECORE_INIT_COMN(pdev, MISC); in init_misc_common()
2570 if (!CHIP_IS_E1(pdev)) /* multi-function not supported in E1 */ in init_misc_common()
2573 if (CHIP_IS_E2(pdev) || CHIP_IS_E1H(pdev)) in init_misc_common()
2575 REG_WR(pdev,MISC_REG_E1HMF_MODE , (pdev->params.multi_vnics_mode ? 1 : 0)); in init_misc_common()
2584 if (!CHIP_IS_E1x(pdev)) in init_misc_common()
2591 for (abs_func_id = PATH_ID(pdev); abs_func_id < E2_FUNC_MAX*2; abs_func_id+=2) in init_misc_common()
2593 if (abs_func_id == ABS_FUNC_ID(pdev)) in init_misc_common()
2595 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in init_misc_common()
2598 lm_pretend_func(pdev, abs_func_id); in init_misc_common()
2600 clear_pf_enable(pdev); in init_misc_common()
2602 lm_pretend_func(pdev, ABS_FUNC_ID(pdev)); in init_misc_common()
2608 if (pdev->params.enable_error_recovery && !CHIP_IS_E1x(pdev)) in init_misc_common()
2610 lm_hw_clear_all_locks(pdev); in init_misc_common()
2612 REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 0); in init_misc_common()
2618 static void init_aeu_port(lm_device_t *pdev) in init_aeu_port() argument
2623 if(ERR_IF(!pdev)) in init_aeu_port()
2628 ECORE_INIT_PORT(pdev, MISC_AEU); in init_aeu_port()
2634 val = (pdev->params.multi_vnics_mode ? 0xF7 : 0x7); in init_aeu_port()
2635 if(!CHIP_IS_E1(pdev)) in init_aeu_port()
2640 …REG_WR(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0), val); in init_aeu_port()
2643 val = REG_RD(pdev, MISC_REG_SPIO_EVENT_EN); in init_aeu_port()
2647 … offset = (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0) ; in init_aeu_port()
2648 val=REG_RD(pdev, offset ); in init_aeu_port()
2651 REG_WR(pdev, offset, val ) ; in init_aeu_port()
2654 if (pdev->params.enable_error_recovery && !CHIP_IS_E1x(pdev)) in init_aeu_port()
2658 … offset = (PORT_ID(pdev) ? MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 : MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0) ; in init_aeu_port()
2659 val = REG_RD(pdev, offset); in init_aeu_port()
2661 REG_WR(pdev, offset, val); in init_aeu_port()
2665 static void init_pxp_common(lm_device_t *pdev) in init_pxp_common() argument
2667 if(ERR_IF(!pdev)) in init_pxp_common()
2672 ECORE_INIT_COMN(pdev, PXP); in init_pxp_common()
2673 if( CHIP_NUM(pdev) <= CHIP_NUM_5710 ) in init_pxp_common()
2676 REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0); in init_pxp_common()
2681 static void init_pxp2_common(lm_device_t *pdev) in init_pxp2_common() argument
2683 u32_t wait_ms = (CHIP_REV_IS_ASIC(pdev)) ? 200 : 200000; in init_pxp2_common()
2686 if(ERR_IF(!pdev)) in init_pxp2_common()
2692 ECORE_INIT_COMN(pdev, PXP2); in init_pxp2_common()
2696 REG_WR(pdev, PXP2_REG_RQ_QM_ENDIAN_M, 1); in init_pxp2_common()
2697 REG_WR(pdev, PXP2_REG_RQ_TM_ENDIAN_M, 1); in init_pxp2_common()
2698 REG_WR(pdev, PXP2_REG_RQ_SRC_ENDIAN_M, 1); in init_pxp2_common()
2699 REG_WR(pdev, PXP2_REG_RQ_CDU_ENDIAN_M, 1); in init_pxp2_common()
2700 REG_WR(pdev, PXP2_REG_RQ_DBG_ENDIAN_M, 1); in init_pxp2_common()
2702 REG_WR(pdev, PXP2_REG_RD_QM_SWAP_MODE, 1); in init_pxp2_common()
2703 REG_WR(pdev, PXP2_REG_RD_TM_SWAP_MODE, 1); in init_pxp2_common()
2704 REG_WR(pdev, PXP2_REG_RD_SRC_SWAP_MODE, 1); in init_pxp2_common()
2705 REG_WR(pdev, PXP2_REG_RD_CDURD_SWAP_MODE, 1); in init_pxp2_common()
2707 ecore_init_pxp_arb(pdev, pdev->hw_info.max_read_req_size, pdev->hw_info.max_payload_size); in init_pxp2_common()
2709 REG_WR(pdev,PXP2_REG_RQ_CDU_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE)); in init_pxp2_common()
2710 REG_WR(pdev,PXP2_REG_RQ_TM_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE)); in init_pxp2_common()
2711 REG_WR(pdev,PXP2_REG_RQ_QM_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE)); in init_pxp2_common()
2712 REG_WR(pdev,PXP2_REG_RQ_SRC_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE)); in init_pxp2_common()
2715 if (CHIP_REV_IS_FPGA(pdev) && CHIP_IS_E1H(pdev)) in init_pxp2_common()
2717 REG_WR(pdev,PXP2_REG_PGL_TAGS_LIMIT,0x1); in init_pxp2_common()
2721 REG_WAIT_VERIFY_VAL(pdev,PXP2_REG_RQ_CFG_DONE, 1, wait_ms); in init_pxp2_common()
2722 REG_WAIT_VERIFY_VAL(pdev,PXP2_REG_RD_INIT_DONE,1, wait_ms); in init_pxp2_common()
2724 REG_WR(pdev,PXP2_REG_RQ_DISABLE_INPUTS,0); in init_pxp2_common()
2725 REG_WR(pdev,PXP2_REG_RD_DISABLE_INPUTS,0); in init_pxp2_common()
2730 if (!CHIP_IS_E1x(pdev)) in init_pxp2_common()
2735 REG_WR(pdev,PXP2_REG_RQ_ONCHIP_AT_B0+i*8, 0); in init_pxp2_common()
2736 REG_WR(pdev,PXP2_REG_RQ_ONCHIP_AT_B0+i*8+4,ONCHIP_ADDR0_VALID()); in init_pxp2_common()
2739 if (pdev->params.multi_vnics_mode) in init_pxp2_common()
2741 lm_pretend_func(pdev, (PATH_ID(pdev) + 6)); in init_pxp2_common()
2742 PXP2_SET_FIRST_LAST_ILT(pdev, TM, 0, ILT_NUM_PAGE_ENTRIES - 1); in init_pxp2_common()
2743 lm_pretend_func(pdev, ABS_FUNC_ID(pdev)); in init_pxp2_common()
2748 REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN,1); /* for 128B cache line value should be 2 */ in init_pxp2_common()
2749 REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN_RD,1); /* for 128B cache line value should be 2 */ in init_pxp2_common()
2750 REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN_SEL,1); in init_pxp2_common()
2754 static void init_pglue_b_common(lm_device_t *pdev) in init_pglue_b_common() argument
2756 ECORE_INIT_COMN(pdev, PGLUE_B); in init_pglue_b_common()
2759 static void init_atc_common(lm_device_t *pdev) in init_atc_common() argument
2761 u32_t wait_ms = (CHIP_REV_IS_ASIC(pdev)) ? 200 : 200000; in init_atc_common()
2762 if (!CHIP_IS_E1x(pdev)) in init_atc_common()
2764 ECORE_INIT_COMN(pdev, ATC); in init_atc_common()
2766 REG_WAIT_VERIFY_VAL(pdev, ATC_REG_ATC_INIT_DONE ,1,wait_ms ); in init_atc_common()
2770 static void init_pxp2_func(lm_device_t *pdev) in init_pxp2_func() argument
2780 ECORE_INIT_FUNC(pdev, PXP2); in init_pxp2_func()
2782 addr_table[0] = pdev->vars.context_cdu_phys_addr_table; in init_pxp2_func()
2783 addr_table[1] = pdev->vars.timers_linear_phys_addr_table; in init_pxp2_func()
2784 addr_table[2] = pdev->vars.qm_queues_phys_addr_table; in init_pxp2_func()
2785 addr_table[3] = pdev->vars.searcher_t1_phys_addr_table; in init_pxp2_func()
2786 num_pages[0] = pdev->vars.context_cdu_num_pages; in init_pxp2_func()
2787 num_pages[1] = pdev->vars.timers_linear_num_pages; in init_pxp2_func()
2788 num_pages[2] = pdev->vars.qm_queues_num_pages; in init_pxp2_func()
2789 num_pages[3] = pdev->vars.searcher_t1_num_pages; in init_pxp2_func()
2791 temp = FUNC_ID(pdev) * ILT_NUM_PAGE_ENTRIES_PER_FUNC; in init_pxp2_func()
2792 rq_onchip_at_reg = CHIP_IS_E1(pdev) ? PXP2_REG_RQ_ONCHIP_AT : PXP2_REG_RQ_ONCHIP_AT_B0; in init_pxp2_func()
2800 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8,ONCHIP_ADDR1(addr_table[k][i].as_u64)); in init_pxp2_func()
2801 REG_WR_IND(pdev,rq_onchip_at_reg+temp*8+4,ONCHIP_ADDR2(addr_table[k][i].as_u64)); in init_pxp2_func()
2806 DbgBreakIf(!(temp<((u32_t)ILT_NUM_PAGE_ENTRIES_PER_FUNC*(FUNC_ID(pdev)+1)))); in init_pxp2_func()
2808 PXP2_SET_FIRST_LAST_ILT(pdev, CDU, first_ilt[0], last_ilt[0]); in init_pxp2_func()
2809 PXP2_SET_FIRST_LAST_ILT(pdev, TM, first_ilt[1], last_ilt[1]); in init_pxp2_func()
2810 PXP2_SET_FIRST_LAST_ILT(pdev, QM, first_ilt[2], last_ilt[2]); in init_pxp2_func()
2811 PXP2_SET_FIRST_LAST_ILT(pdev, SRC, first_ilt[3], last_ilt[3]); in init_pxp2_func()
2813 if (!CHIP_IS_E1x(pdev)) in init_pxp2_func()
2817 mm_wait(pdev, 20000); in init_pxp2_func()
2823 static void init_dmae_common(lm_device_t *pdev) in init_dmae_common() argument
2825 if(ERR_IF(!pdev)) in init_dmae_common()
2830 ECORE_INIT_COMN( pdev, DMAE); in init_dmae_common()
2835 REG_WR_DMAE_LEN_ZERO(pdev, TSEM_REG_PRAM, 8); in init_dmae_common()
2836 pdev->vars.b_is_dmae_ready = TRUE ; in init_dmae_common()
2839 static void init_qm_common(lm_device_t *pdev) in init_qm_common() argument
2844 if(ERR_IF(!pdev)) in init_qm_common()
2849 ECORE_INIT_COMN( pdev, QM); in init_qm_common()
2854 REG_WR_IND(pdev,QM_REG_PTRTBL +8*i ,0); in init_qm_common()
2855 REG_WR_IND(pdev,QM_REG_PTRTBL +8*i +4 ,0); in init_qm_common()
2859 if (CHIP_IS_E1H(pdev)) in init_qm_common()
2863 REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i ,0); in init_qm_common()
2864 REG_WR_IND(pdev,QM_REG_PTRTBL_EXT_A +8*i +4 ,0); in init_qm_common()
2869 REG_WR(pdev,QM_REG_SOFT_RESET,1); in init_qm_common()
2870 REG_WR(pdev,QM_REG_SOFT_RESET,0); in init_qm_common()
2896 …REG_WR(pdev,QM_REG_BASEADDR +4*(func*QM_QUEUES_PER_FUNC+i) , pdev->hw_info.max_common_conns * 4*i); in init_qm_common()
2900 if (CHIP_IS_E1H(pdev)) in init_qm_common()
2906 …REG_WR(pdev,QM_REG_BASEADDR_EXT_A +4*(func*QM_QUEUES_PER_FUNC+i) , pdev->hw_info.max_common_conns … in init_qm_common()
2912 static void init_qm_func(lm_device_t *pdev) in init_qm_func() argument
2914 ECORE_INIT_FUNC( pdev, QM); in init_qm_func()
2916 if (!CHIP_IS_E1x(pdev)) in init_qm_func()
2920 REG_WR(pdev, QM_REG_PF_EN, 1); in init_qm_func()
2924 static void init_qm_port(lm_device_t *pdev) in init_qm_port() argument
2926 if(ERR_IF(!pdev)) in init_qm_port()
2931 ECORE_INIT_PORT(pdev, QM); in init_qm_port()
2934 …REG_WR(pdev, (PORT_ID(pdev) ? QM_REG_CONNNUM_1 : QM_REG_CONNNUM_0), pdev->hw_info.max_common_conns… in init_qm_port()
2937 static void init_tm_port(lm_device_t *pdev) in init_tm_port() argument
2939 if(ERR_IF(!pdev)) in init_tm_port()
2944 ECORE_INIT_PORT(pdev, TM); in init_tm_port()
2947 REG_WR(pdev,(PORT_ID(pdev) ? TM_REG_LIN1_SCAN_TIME : TM_REG_LIN0_SCAN_TIME), 20); in init_tm_port()
2949 …REG_WR(pdev,(PORT_ID(pdev) ? TM_REG_LIN1_MAX_ACTIVE_CID : TM_REG_LIN0_MAX_ACTIVE_CID), (pdev->hw_i… in init_tm_port()
2953 static void init_dq_common(lm_device_t *pdev) in init_dq_common() argument
2955 if(ERR_IF(!pdev)) in init_dq_common()
2960 ECORE_INIT_COMN(pdev, DORQ); in init_dq_common()
2964 REG_WR(pdev,DORQ_REG_DPM_CID_OFST,LM_DQ_CID_BITS); in init_dq_common()
2965 if (CHIP_REV_IS_ASIC(pdev)) in init_dq_common()
2968 REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0); in init_dq_common()
2972 void init_dq_func(lm_device_t *pdev) in init_dq_func() argument
2974 ECORE_INIT_FUNC(pdev, DORQ); in init_dq_func()
2976 …if (!CHIP_IS_E1x(pdev) && (IS_BASIC_VIRT_MODE_MASTER_PFDEV(pdev) || IS_CHANNEL_VIRT_MODE_MASTER_PF… in init_dq_func()
2978 … REG_WR(pdev, DORQ_REG_MAX_RVFID_SIZE, 6); // As long as we want to use absolute VF-id number in init_dq_func()
2979 …REG_WR(pdev, DORQ_REG_VF_NORM_VF_BASE, 0); //(a VF-id that is unique within the port), like t… in init_dq_func()
2982 REG_WR(pdev, DORQ_REG_VF_NORM_CID_BASE, LM_VF_CID_BASE(pdev)); /*64 for single connection. in init_dq_func()
2986 …REG_WR(pdev, DORQ_REG_VF_NORM_CID_WND_SIZE, LM_VF_CID_WND_SIZE(pdev)); /* should reflect the maxim… in init_dq_func()
2990 …REG_WR(pdev, DORQ_REG_VF_NORM_CID_OFST, LM_DQ_CID_BITS - 3); /*means the number of bits in a VF… in init_dq_func()
2993 REG_WR(pdev, DORQ_REG_VF_NORM_CID_OFST, LM_VF_DQ_CID_BITS); in init_dq_func()
3002 REG_WR(pdev, DORQ_REG_VF_TYPE_MASK_0, 0x71); in init_dq_func()
3003 REG_WR(pdev, DORQ_REG_VF_TYPE_VALUE_0, 0); in init_dq_func()
3004 REG_WR(pdev, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); in init_dq_func()
3005 REG_WR(pdev, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); in init_dq_func()
3008 REG_WR(pdev, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000); in init_dq_func()
3009 REG_WR(pdev, DORQ_REG_VF_USAGE_CT_LIMIT, 64); in init_dq_func()
3014 static void init_brb1_common(lm_device_t *pdev) in init_brb1_common() argument
3016 ECORE_INIT_COMN(pdev, BRB1); in init_brb1_common()
3019 static void init_pbf_common(lm_device_t *pdev) in init_pbf_common() argument
3021 ECORE_INIT_COMN(pdev, PBF); in init_pbf_common()
3023 if (!CHIP_IS_E1x(pdev)) in init_pbf_common()
3025 if (IS_MF_AFEX_MODE(pdev)) in init_pbf_common()
3027 REG_WR(pdev, PBF_REG_HDRS_AFTER_BASIC, 0xE); in init_pbf_common()
3028 REG_WR(pdev, PBF_REG_MUST_HAVE_HDRS, 0xA); in init_pbf_common()
3029 REG_WR(pdev, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in init_pbf_common()
3030 REG_WR(pdev, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in init_pbf_common()
3031 REG_WR(pdev, PBF_REG_TAG_LEN_0, 0x4); in init_pbf_common()
3036 …REG_WR(pdev, PBF_REG_HDRS_AFTER_BASIC, (pdev->params.path_has_ovlan ? 7 : 6)); //Bit-map indicatin… in init_pbf_common()
3041 static void init_pbf_func(lm_device_t *pdev) in init_pbf_func() argument
3043 ECORE_INIT_FUNC(pdev, PBF); in init_pbf_func()
3044 if (!CHIP_IS_E1x(pdev)) in init_pbf_func()
3046 REG_WR(pdev,PBF_REG_DISABLE_PF,0); in init_pbf_func()
3050 static void init_brb_port(lm_device_t *pdev) in init_brb_port() argument
3056 port=PORT_ID(pdev); in init_brb_port()
3058 ECORE_INIT_PORT( pdev, BRB1); in init_brb_port()
3060 if (CHIP_IS_E1x(pdev)) in init_brb_port()
3063 if (CHIP_REV_IS_EMUL(pdev) || (CHIP_REV_IS_FPGA(pdev) && CHIP_IS_E1(pdev))) in init_brb_port()
3071 if (IS_MULTI_VNIC(pdev)) in init_brb_port()
3079 if (pdev->params.mtu_max <= 4096) in init_brb_port()
3087 low = 96 + (pdev->params.mtu_max*4)/256; in init_brb_port()
3094 REG_WR(pdev,BRB1_REG_PAUSE_LOW_THRESHOLD_0+port*4,low); in init_brb_port()
3095 REG_WR(pdev,BRB1_REG_PAUSE_HIGH_THRESHOLD_0+port*4,high); in init_brb_port()
3098 if (CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_4) in init_brb_port()
3100 REG_WR(pdev, (PORT_ID(pdev)? BRB1_REG_MAC_GUARANTIED_1 : BRB1_REG_MAC_GUARANTIED_0), 40); in init_brb_port()
3106 static void init_prs_common(lm_device_t *pdev) in init_prs_common() argument
3108 if(ERR_IF(!pdev)) in init_prs_common()
3113 ECORE_INIT_COMN( pdev, PRS); in init_prs_common()
3115 if (!CHIP_IS_E1(pdev)) in init_prs_common()
3117 REG_WR(pdev,PRS_REG_E1HOV_MODE, (pdev->params.path_has_ovlan ? 1 : 0)); in init_prs_common()
3120 if (!CHIP_IS_E1x(pdev)) in init_prs_common()
3122 if (IS_MF_AFEX_MODE(pdev)) in init_prs_common()
3124 if (!CHIP_IS_E3B0(pdev)) //on E3 B0 this initialization happens in port phase. in init_prs_common()
3126 REG_WR(pdev, PRS_REG_HDRS_AFTER_BASIC, 0xE); in init_prs_common()
3127 REG_WR(pdev, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in init_prs_common()
3128 REG_WR(pdev, PRS_REG_MUST_HAVE_HDRS, 0xA); in init_prs_common()
3131 REG_WR(pdev, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in init_prs_common()
3132 REG_WR(pdev, PRS_REG_TAG_LEN_0, 0x4); in init_prs_common()
3136 if (!CHIP_IS_E3B0(pdev)) //on E3 B0 this initialization happens in port phase. in init_prs_common()
3139 …REG_WR(pdev, PRS_REG_HDRS_AFTER_BASIC, (pdev->params.path_has_ovlan ? 7 : 6)); //Bit-map indicatin… in init_prs_common()
3146 static void init_prs_port(lm_device_t *pdev) in init_prs_port() argument
3148 ECORE_INIT_PORT(pdev, PRS); in init_prs_port()
3150 if (IS_MF_AFEX_MODE(pdev)) in init_prs_port()
3152 if (CHIP_IS_E3B0(pdev)) //on E3 B0 this initialization happens in port phase. in init_prs_port()
3154 …REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_BASIC_PORT_0 :PRS_REG_HDRS_AFTER_BASIC_PORT_… in init_prs_port()
3155 …REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_TAG_0_PORT_0 :PRS_REG_HDRS_AFTER_TAG_0_PORT_… in init_prs_port()
3156 …REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_MUST_HAVE_HDRS_PORT_0 :PRS_REG_MUST_HAVE_HDRS_PORT_1 … in init_prs_port()
3161 if (CHIP_IS_E3B0(pdev)) //on E3 B0 this initialization happens in port phase. in init_prs_port()
3164 …REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_BASIC_PORT_0:PRS_REG_HDRS_AFTER_BASIC_PORT_1… in init_prs_port()
3169 static void init_prs_func(lm_device_t *pdev) in init_prs_func() argument
3171 if(ERR_IF(!pdev)) in init_prs_func()
3176 ECORE_INIT_FUNC( pdev, PRS); in init_prs_func()
3180 static void init_semi_common(lm_device_t *pdev) in init_semi_common() argument
3183 if (!CHIP_IS_E1x(pdev)) in init_semi_common()
3187 REG_WR(pdev, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in init_semi_common()
3190 REG_WR(pdev, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in init_semi_common()
3196 ECORE_INIT_COMN(pdev, TSEM); in init_semi_common()
3197 ECORE_INIT_COMN(pdev, CSEM); in init_semi_common()
3198 ECORE_INIT_COMN(pdev, USEM); in init_semi_common()
3199 ECORE_INIT_COMN(pdev, XSEM); in init_semi_common()
3202 static void init_semi_port(lm_device_t *pdev) in init_semi_port() argument
3204 ECORE_INIT_PORT(pdev, TSEM); in init_semi_port()
3205 ECORE_INIT_PORT(pdev, USEM); in init_semi_port()
3206 ECORE_INIT_PORT(pdev, CSEM); in init_semi_port()
3207 ECORE_INIT_PORT(pdev, XSEM); in init_semi_port()
3215 kuku= REG_RD(pdev, XSEM_REG_PASSIVE_BUFFER); in init_semi_port()
3216 kuku = REG_RD(pdev, XSEM_REG_PASSIVE_BUFFER + 4); in init_semi_port()
3217 kuku = REG_RD(pdev, XSEM_REG_PASSIVE_BUFFER + 8); in init_semi_port()
3219 kuku = REG_RD(pdev, CSEM_REG_PASSIVE_BUFFER ); in init_semi_port()
3220 kuku = REG_RD(pdev, CSEM_REG_PASSIVE_BUFFER + 4); in init_semi_port()
3221 kuku = REG_RD(pdev, CSEM_REG_PASSIVE_BUFFER + 8); in init_semi_port()
3223 kuku = REG_RD(pdev, TSEM_REG_PASSIVE_BUFFER ); in init_semi_port()
3224 kuku = REG_RD(pdev, TSEM_REG_PASSIVE_BUFFER + 4); in init_semi_port()
3225 kuku = REG_RD(pdev, TSEM_REG_PASSIVE_BUFFER + 8); in init_semi_port()
3227 kuku = REG_RD(pdev, USEM_REG_PASSIVE_BUFFER ); in init_semi_port()
3228 kuku = REG_RD(pdev, USEM_REG_PASSIVE_BUFFER + 4); in init_semi_port()
3229 kuku = REG_RD(pdev, USEM_REG_PASSIVE_BUFFER + 8); in init_semi_port()
3233 static void init_semi_func(lm_device_t *pdev) in init_semi_func() argument
3235 ECORE_INIT_FUNC(pdev, TSEM); in init_semi_func()
3236 ECORE_INIT_FUNC(pdev, USEM); in init_semi_func()
3237 ECORE_INIT_FUNC(pdev, CSEM); in init_semi_func()
3238 ECORE_INIT_FUNC(pdev, XSEM); in init_semi_func()
3240 if (!CHIP_IS_E1x(pdev)) in init_semi_func()
3242 REG_WR(pdev,TSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS)); in init_semi_func()
3243 REG_WR(pdev,USEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS)); in init_semi_func()
3244 REG_WR(pdev,CSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS)); in init_semi_func()
3245 REG_WR(pdev,XSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS)); in init_semi_func()
3251 static void init_pbf_port(lm_device_t *pdev) in init_pbf_port() argument
3253 if(ERR_IF(!pdev)) in init_pbf_port()
3258 ECORE_INIT_PORT(pdev, PBF); in init_pbf_port()
3261 if (CHIP_IS_E1x(pdev)) in init_pbf_port()
3263 REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_PAUSE_ENABLE : PBF_REG_P0_PAUSE_ENABLE),0); in init_pbf_port()
3265 …REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_ARB_THRSH : PBF_REG_P0_ARB_THRSH),(MAXIMUM_PACKET_SIZE/16)… in init_pbf_port()
3267 …REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_INIT_CRD : PBF_REG_P0_INIT_CRD),(MAXIMUM_PACKET_SIZE/16) +… in init_pbf_port()
3269 REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_INIT_P1 : PBF_REG_INIT_P0),1); in init_pbf_port()
3270 mm_wait(pdev,5); in init_pbf_port()
3271 REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_INIT_P1 : PBF_REG_INIT_P0),0); in init_pbf_port()
3276 static void init_src_common(lm_device_t *pdev) in init_src_common() argument
3278 if(ERR_IF(!pdev)) in init_src_common()
3283 REG_WR(pdev,SRC_REG_SOFT_RST,1); in init_src_common()
3285 ECORE_INIT_COMN(pdev, SRC); in init_src_common()
3287 REG_WR(pdev,SRC_REG_KEYSEARCH_0,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[0])); in init_src_common()
3288 REG_WR(pdev,SRC_REG_KEYSEARCH_1,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[4])); in init_src_common()
3289 REG_WR(pdev,SRC_REG_KEYSEARCH_2,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[8])); in init_src_common()
3290 … REG_WR(pdev,SRC_REG_KEYSEARCH_3,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[12])); in init_src_common()
3291 … REG_WR(pdev,SRC_REG_KEYSEARCH_4,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[16])); in init_src_common()
3292 … REG_WR(pdev,SRC_REG_KEYSEARCH_5,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[20])); in init_src_common()
3293 … REG_WR(pdev,SRC_REG_KEYSEARCH_6,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[24])); in init_src_common()
3294 … REG_WR(pdev,SRC_REG_KEYSEARCH_7,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[28])); in init_src_common()
3295 … REG_WR(pdev,SRC_REG_KEYSEARCH_8,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[32])); in init_src_common()
3296 … REG_WR(pdev,SRC_REG_KEYSEARCH_9,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[36])); in init_src_common()
3298 REG_WR(pdev,SRC_REG_SOFT_RST,0); in init_src_common()
3301 static void init_src_func(lm_device_t *pdev) in init_src_func() argument
3305 ECORE_INIT_FUNC(pdev, SRC); in init_src_func()
3307 …REG_WR(pdev, (PORT_ID(pdev) ? SRC_REG_COUNTFREE1 : SRC_REG_COUNTFREE0) ,pdev->vars.searcher_t2_nu… in init_src_func()
3308 …REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_FIRSTFREE1 : SRC_REG_FIRSTFREE0),pdev->vars.searcher_t2… in init_src_func()
3309 …REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_FIRSTFREE1 : SRC_REG_FIRSTFREE0)+4,pdev->vars.searcher_… in init_src_func()
3310 …src_addr.as_u64 = pdev->vars.searcher_t2_phys_addr_table[pdev->vars.searcher_t2_num_pages-1].as_u64 in init_src_func()
3311 + pdev->params.ilt_client_page_size - 64 ; in init_src_func()
3312 REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_LASTFREE1 : SRC_REG_LASTFREE0),src_addr.as_u32.low); in init_src_func()
3313 … REG_WR_IND(pdev, (PORT_ID(pdev) ? SRC_REG_LASTFREE1 : SRC_REG_LASTFREE0)+4,src_addr.as_u32.high); in init_src_func()
3314 …REG_WR(pdev, (PORT_ID(pdev) ? SRC_REG_NUMBER_HASH_BITS1 : SRC_REG_NUMBER_HASH_BITS0),pdev->contex… in init_src_func()
3317 static void init_cdu_common(lm_device_t *pdev) in init_cdu_common() argument
3321 if(ERR_IF(!pdev)) in init_cdu_common()
3326 ECORE_INIT_COMN(pdev, CDU); in init_cdu_common()
3328 val = (pdev->params.num_context_in_page<<24) + in init_cdu_common()
3329 (pdev->params.context_waste_size<<12) + in init_cdu_common()
3330 pdev->params.context_line_size; in init_cdu_common()
3331 REG_WR(pdev,CDU_REG_CDU_GLOBAL_PARAMS,val); in init_cdu_common()
3333 REG_WR(pdev,CDU_REG_CDU_CONTROL0,0X1UL); in init_cdu_common()
3334 REG_WR(pdev,CDU_REG_CDU_CHK_MASK0,0X0003d000UL); /* enable region 2 */ in init_cdu_common()
3335 REG_WR(pdev,CDU_REG_CDU_CHK_MASK1,0X0000003dUL); /* enable region 4 */ in init_cdu_common()
3340 static void init_cfc_common(lm_device_t *pdev) in init_cfc_common() argument
3343 if(ERR_IF(!pdev)) in init_cfc_common()
3348 ECORE_INIT_COMN(pdev, CFC); in init_cfc_common()
3352 cfc_init_reg |= (pdev->params.cfc_last_lcid << CFC_INIT_REG_REG_LL_INIT_LAST_LCID_SIZE); in init_cfc_common()
3355 REG_WR(pdev, CFC_REG_INIT_REG, cfc_init_reg); in init_cfc_common()
3359 …if (!CHIP_IS_E1x(pdev) && (IS_BASIC_VIRT_MODE_MASTER_PFDEV(pdev) || IS_CHANNEL_VIRT_MODE_MASTER_PF… in init_cfc_common()
3366 REG_WR(pdev, CFC_REG_DISABLE_ON_ERROR, 0xffdf); in init_cfc_common()
3367 REG_WR(pdev, CFC_REG_CFC_INT_MASK, 0x2); in init_cfc_common()
3368 REG_WR(pdev, CFC_REG_DORQ_MASK_PCIERR, 0x1); in init_cfc_common()
3369 REG_WR(pdev, CFC_REG_DORQ_MASK_VALERR, 0x1); in init_cfc_common()
3373 REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0); in init_cfc_common()
3374 REG_WR(pdev, CFC_REG_DORQ_MASK_PCIERR, 0); in init_cfc_common()
3375 REG_WR(pdev, CFC_REG_DORQ_MASK_VALERR, 0); in init_cfc_common()
3378 REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0); in init_cfc_common()
3384 REG_WR(pdev,CFC_REG_DEBUG0 ,0x20020000); in init_cfc_common()
3385 REG_WR(pdev,CFC_REG_INTERFACES ,0x280000); in init_cfc_common()
3386 REG_WR(pdev,CFC_REG_INTERFACES ,0); in init_cfc_common()
3392 static void init_hc_port(lm_device_t *pdev) in init_hc_port() argument
3394 if(ERR_IF(!pdev)) in init_hc_port()
3399 if(CHIP_IS_E1(pdev)) in init_hc_port()
3401 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0); in init_hc_port()
3402 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0); in init_hc_port()
3405 ECORE_INIT_PORT(pdev, HC); in init_hc_port()
3408 static void init_hc_func(lm_device_t *pdev) in init_hc_func() argument
3410 const u8_t func = FUNC_ID(pdev); in init_hc_func()
3412 if(ERR_IF(!pdev)) in init_hc_func()
3417 if(CHIP_IS_E1H(pdev)) in init_hc_func()
3419 REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_12 + 4*func,0x0); in init_hc_func()
3420 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0); in init_hc_func()
3421 REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0); in init_hc_func()
3424 ECORE_INIT_FUNC(pdev, HC); in init_hc_func()
3427 static void init_igu_common( lm_device_t *pdev ) in init_igu_common() argument
3430 ECORE_INIT_COMN(pdev, IGU); in init_igu_common()
3434 REG_WR(pdev, IGU_REG_COMMAND_DEBUG, 1); // 1 - FIFO collects eight last incoming command in init_igu_common()
3439 REG_WR(pdev, IGU_REG_ERROR_HANDLING_FILTER, val); in init_igu_common()
3444 static void init_igu_func(lm_device_t *pdev) in init_igu_func() argument
3453 if(ERR_IF(!pdev)) in init_igu_func()
3458 if (INTR_BLK_TYPE(pdev) == INTR_BLK_IGU) in init_igu_func()
3461 REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_12 + 4*FUNC_ID(pdev),0x0); in init_igu_func()
3462 REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, 0); in init_igu_func()
3463 REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, 0); in init_igu_func()
3465 ECORE_INIT_FUNC(pdev, IGU); in init_igu_func()
3468 val=REG_RD(pdev, IGU_REG_PF_CONFIGURATION); in init_igu_func()
3470 REG_WR(pdev, IGU_REG_PF_CONFIGURATION, val); in init_igu_func()
3485 for (sb_id = 0; sb_id < LM_IGU_SB_CNT(pdev); sb_id++) in init_igu_func()
3487 …prod_idx = (IGU_BASE_NDSB(pdev) + sb_id)*num_segs; /* bc-assumption consecutive pfs, norm-no assum… in init_igu_func()
3490 REG_WR(pdev, IGU_REG_PROD_CONS_MEMORY + (prod_idx + i)*4, 0); in init_igu_func()
3493 lm_int_ack_sb_enable(pdev, sb_id); in init_igu_func()
3496 lm_int_igu_sb_cleanup(pdev, IGU_BASE_NDSB(pdev) + sb_id); in init_igu_func()
3500 if (CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_4) in init_igu_func()
3502 dsb_idx = FUNC_ID(pdev); in init_igu_func()
3506 dsb_idx = VNIC_ID(pdev); in init_igu_func()
3508 … num_segs = (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC)? IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; in init_igu_func()
3509 …base_prod = (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_BC) ? (IGU_BC_BASE_DSB_PROD + dsb_idx) : (IGU_NO… in init_igu_func()
3512 REG_WR(pdev, IGU_REG_PROD_CONS_MEMORY + (base_prod + i*MAX_VNIC_NUM)*4, 0); in init_igu_func()
3515 lm_int_ack_def_sb_enable(pdev); in init_igu_func()
3518 lm_int_igu_sb_cleanup(pdev, IGU_DSB_ID(pdev)); in init_igu_func()
3521 igu_func_id = (CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_4)? FUNC_ID(pdev) : VNIC_ID(pdev); in init_igu_func()
3524 REG_WR(pdev, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + igu_func_id*4, 0); in init_igu_func()
3525 REG_WR(pdev, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + (igu_func_id + MAX_VNIC_NUM)*4, 0); in init_igu_func()
3528 REG_WR(pdev, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in init_igu_func()
3529 REG_WR(pdev, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in init_igu_func()
3530 REG_WR(pdev, IGU_REG_SB_MASK_LSB, 0); in init_igu_func()
3531 REG_WR(pdev, IGU_REG_SB_MASK_MSB, 0); in init_igu_func()
3532 REG_WR(pdev, IGU_REG_PBA_STATUS_LSB, 0); in init_igu_func()
3533 REG_WR(pdev, IGU_REG_PBA_STATUS_MSB, 0); in init_igu_func()
3539 static void init_nig_common(lm_device_t *pdev) in init_nig_common() argument
3541 ECORE_INIT_COMN( pdev, NIG); in init_nig_common()
3543 …if (CHIP_IS_E2(pdev) || CHIP_IS_E1H(pdev)) /* E3 supports this per port - and is therefore done in… in init_nig_common()
3545 REG_WR(pdev,NIG_REG_LLH_MF_MODE, IS_MULTI_VNIC(pdev) ? 1 : 0); in init_nig_common()
3549 if (CHIP_IS_E1H(pdev)) in init_nig_common()
3551 REG_WR(pdev,NIG_REG_LLH_E1HOV_MODE, IS_MF_SD_MODE(pdev) ? 1 : 0); in init_nig_common()
3556 static void init_nig_port(lm_device_t *pdev) in init_nig_port() argument
3558 ECORE_INIT_PORT( pdev, NIG); in init_nig_port()
3560 if (!CHIP_IS_E3(pdev)) in init_nig_port()
3562 … REG_WR(pdev,(PORT_ID(pdev) ? NIG_REG_XGXS_SERDES1_MODE_SEL : NIG_REG_XGXS_SERDES0_MODE_SEL),1); in init_nig_port()
3565 if (!CHIP_IS_E1x(pdev)) in init_nig_port()
3568 if (CHIP_IS_E3(pdev)) in init_nig_port()
3570 …REG_WR(pdev,(PORT_ID(pdev)? NIG_REG_LLH1_MF_MODE: NIG_REG_LLH_MF_MODE), IS_MULTI_VNIC(pdev) ? 1 :… in init_nig_port()
3574 if (!CHIP_IS_E1(pdev)) in init_nig_port()
3579 … u32_t mask_mf_reg = PORT_ID(pdev) ? NIG_REG_LLH1_BRB1_DRV_MASK_MF : NIG_REG_LLH0_BRB1_DRV_MASK_MF; in init_nig_port()
3580 …u32_t val = IS_MF_SD_MODE(pdev) ? NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_OUTER_VLAN : NI… in init_nig_port()
3584 REG_WR(pdev, mask_mf_reg, val); in init_nig_port()
3586 if (!CHIP_IS_E1x(pdev)) in init_nig_port()
3588 if (IS_MF_SD_MODE(pdev)) in init_nig_port()
3590 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_CLS_TYPE : NIG_REG_LLH0_CLS_TYPE), 1); in init_nig_port()
3594 REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_CLS_TYPE : NIG_REG_LLH0_CLS_TYPE), 2); in init_nig_port()
3600 void init_nig_func(lm_device_t *pdev) in init_nig_func() argument
3602 const u8_t mf = pdev->params.multi_vnics_mode; in init_nig_func()
3603 const u8_t port = PORT_ID(pdev); in init_nig_func()
3606 ECORE_INIT_FUNC(pdev, NIG); in init_nig_func()
3612 … if (IS_SD_UFP_MODE(pdev) && GET_FLAGS(pdev->params.mf_proto_support_flags, LM_PROTO_SUPPORT_FCOE)) in init_nig_func()
3614 REG_WR(pdev, offset , 0); in init_nig_func()
3618 REG_WR(pdev, offset , 1); in init_nig_func()
3622 REG_WR(pdev, offset , pdev->params.ovlan); in init_nig_func()
3626 static void init_pxpcs_common(lm_device_t *pdev) in init_pxpcs_common() argument
3628 if(ERR_IF(!pdev)) in init_pxpcs_common()
3634 REG_WR(pdev,0x2814,0xffffffff); in init_pxpcs_common()
3635 REG_WR(pdev,0x3820,0xffffffff); in init_pxpcs_common()
3637 if (!CHIP_IS_E1x(pdev)) in init_pxpcs_common()
3639 …REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_CONTROL_5, (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | PXPCS_TL_CONT… in init_pxpcs_common()
3640 REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in init_pxpcs_common()
3642 REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in init_pxpcs_common()
3647 static void init_pxpcs_func(lm_device_t *pdev) in init_pxpcs_func() argument
3649 if(ERR_IF(!pdev)) in init_pxpcs_func()
3654 REG_WR(pdev,0x2114,0xffffffff); in init_pxpcs_func()
3655 REG_WR(pdev,0x2120,0xffffffff); in init_pxpcs_func()
3658 static void init_pglue_b_port(lm_device_t *pdev) in init_pglue_b_port() argument
3660 ECORE_INIT_PORT(pdev, PGLUE_B); in init_pglue_b_port()
3664 if (!CHIP_IS_E1x(pdev)) in init_pglue_b_port()
3666 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in init_pglue_b_port()
3670 static void init_pglue_b_func(lm_device_t *pdev) in init_pglue_b_func() argument
3672 ECORE_INIT_FUNC(pdev, PGLUE_B); in init_pglue_b_func()
3674 if (!CHIP_IS_E1x(pdev)) in init_pglue_b_func()
3680 REG_WR(pdev,PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, FUNC_ID(pdev)); in init_pglue_b_func()
3685 static void init_cfc_func(lm_device_t *pdev) in init_cfc_func() argument
3687 ECORE_INIT_FUNC(pdev, CFC); in init_cfc_func()
3688 if (!CHIP_IS_E1x(pdev)) in init_cfc_func()
3690 REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,1); in init_cfc_func()
3695 static void init_aeu_common(lm_device_t * pdev) in init_aeu_common() argument
3697 ECORE_INIT_COMN(pdev, MISC_AEU); in init_aeu_common()
3700 lm_er_config_close_the_g8(pdev); in init_aeu_common()
3703 #define init_tcm_common( pdev) ECORE_INIT_COMN(pdev, TCM); argument
3704 #define init_ccm_common( pdev) ECORE_INIT_COMN(pdev, CCM); argument
3705 #define init_ucm_common( pdev) ECORE_INIT_COMN(pdev, UCM); argument
3706 #define init_xcm_common( pdev) ECORE_INIT_COMN(pdev, XCM) argument
3707 #define init_tsdm_common(pdev) ECORE_INIT_COMN(pdev, TSDM) argument
3708 #define init_csdm_common(pdev) ECORE_INIT_COMN(pdev, CSDM) argument
3709 #define init_usdm_common(pdev) ECORE_INIT_COMN(pdev, USDM) argument
3710 #define init_xsdm_common(pdev) ECORE_INIT_COMN(pdev, XSDM) argument
3711 #define init_tm_common( pdev) ECORE_INIT_COMN(pdev, TM) argument
3712 #define init_upb_common( pdev) ECORE_INIT_COMN(pdev, UPB) argument
3713 #define init_xpb_common( pdev) ECORE_INIT_COMN(pdev, XPB) argument
3714 #define init_hc_common( pdev) ECORE_INIT_COMN(pdev, HC) argument
3715 #define init_dbg_common(pdev) ECORE_INIT_COMN(pdev, DBG) argument
3717 #define init_pxp_port(pdev) ECORE_INIT_PORT(pdev, PXP) argument
3718 #define init_pxp2_port(pdev) ECORE_INIT_PORT(pdev, PXP2) argument
3719 #define init_atc_port(pdev) ECORE_INIT_PORT(pdev, ATC) argument
3720 #define init_tcm_port( pdev) ECORE_INIT_PORT(pdev, TCM) argument
3721 #define init_ucm_port( pdev) ECORE_INIT_PORT(pdev, UCM) argument
3722 #define init_ccm_port( pdev) ECORE_INIT_PORT(pdev, CCM) argument
3723 #define init_misc_port( pdev) ECORE_INIT_PORT(pdev, MISC) argument
3724 #define init_xcm_port( pdev) ECORE_INIT_PORT(pdev, XCM) argument
3725 #define init_dq_port(pdev) ECORE_INIT_PORT(pdev, DORQ) argument
3726 #define init_tsdm_port( pdev) ECORE_INIT_PORT(pdev, TSDM) argument
3727 #define init_csdm_port( pdev) ECORE_INIT_PORT(pdev, CSDM) argument
3728 #define init_usdm_port( pdev) ECORE_INIT_PORT(pdev, USDM) argument
3729 #define init_xsdm_port( pdev) ECORE_INIT_PORT(pdev, XSDM) argument
3730 #define init_upb_port(pdev) ECORE_INIT_PORT(pdev, UPB) argument
3731 #define init_xpb_port(pdev) ECORE_INIT_PORT(pdev, XPB) argument
3732 #define init_src_port(pdev) ECORE_INIT_PORT(pdev, SRC) argument
3733 #define init_cdu_port(pdev) ECORE_INIT_PORT(pdev, CDU) argument
3734 #define init_cfc_port(pdev) ECORE_INIT_PORT(pdev, CFC) argument
3736 #define init_igu_port( pdev) ECORE_INIT_PORT(pdev, IGU) argument
3737 #define init_dbg_port(pdev) ECORE_INIT_PORT(pdev, DBG) argument
3738 #define init_dmae_port(pdev) ECORE_INIT_PORT(pdev, DMAE) argument
3740 #define init_misc_func(pdev) ECORE_INIT_FUNC(pdev, MISC) argument
3741 #define init_pxp_func(pdev) ECORE_INIT_FUNC(pdev, PXP) argument
3742 #define init_atc_func(pdev) ECORE_INIT_FUNC(pdev, ATC) argument
3743 #define init_tcm_func(pdev) ECORE_INIT_FUNC(pdev, TCM) argument
3744 #define init_ucm_func(pdev) ECORE_INIT_FUNC(pdev, UCM) argument
3745 #define init_ccm_func(pdev) ECORE_INIT_FUNC(pdev, CCM) argument
3746 #define init_xcm_func(pdev) ECORE_INIT_FUNC(pdev, XCM) argument
3747 #define init_tm_func(pdev) ECORE_INIT_FUNC(pdev, TM) argument
3748 #define init_brb_func(pdev) ECORE_INIT_FUNC(pdev, BRB1) argument
3749 #define init_tsdm_func(pdev) ECORE_INIT_FUNC(pdev, TSDM) argument
3750 #define init_csdm_func(pdev) ECORE_INIT_FUNC(pdev, CSDM) argument
3751 #define init_usdm_func(pdev) ECORE_INIT_FUNC(pdev, USDM) argument
3752 #define init_xsdm_func(pdev) ECORE_INIT_FUNC(pdev, XSDM) argument
3753 #define init_upb_func(pdev) ECORE_INIT_FUNC(pdev, UPB) argument
3754 #define init_xpb_func(pdev) ECORE_INIT_FUNC(pdev, XPB) argument
3755 #define init_cdu_func(pdev) ECORE_INIT_FUNC(pdev, CDU) argument
3756 #define init_aeu_func(pdev) ECORE_INIT_FUNC(pdev, MISC_AEU) argument
3757 #define init_dbg_func(pdev) ECORE_INIT_FUNC(pdev, DBG) argument
3758 #define init_dmae_func(pdev) ECORE_INIT_FUNC(pdev, DMAE) argument
3761 static void init_nig_pkt(struct _lm_device_t *pdev) in init_nig_pkt() argument
3772 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB, wb_write[0]); in init_nig_pkt()
3773 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+4,wb_write[1]); in init_nig_pkt()
3775 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+8,wb_write[2]); in init_nig_pkt()
3782 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB, wb_write[0]); in init_nig_pkt()
3783 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+4,wb_write[1]); in init_nig_pkt()
3785 REG_WR_IND(pdev,NIG_REG_DEBUG_PACKET_LB+8,wb_write[2]); in init_nig_pkt()
3788 static void prs_brb_mem_setup (struct _lm_device_t *pdev) in prs_brb_mem_setup() argument
3798 DbgBreakIf(!pdev->vars.clk_factor); in prs_brb_mem_setup()
3800 DbgMessage(pdev, WARN, "mem_wrk start part1\n"); in prs_brb_mem_setup()
3803 REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x0); in prs_brb_mem_setup()
3804 REG_WR(pdev,TCM_REG_PRS_IFEN,0x0); in prs_brb_mem_setup()
3805 REG_WR(pdev,CFC_REG_DEBUG0,0x1); in prs_brb_mem_setup()
3806 REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x0); in prs_brb_mem_setup()
3809 REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x0); in prs_brb_mem_setup()
3812 init_nig_pkt(pdev); in prs_brb_mem_setup()
3819 val=REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET); in prs_brb_mem_setup()
3820 trash=REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET+4); in prs_brb_mem_setup()
3826 mm_wait(pdev,10 * pdev->vars.clk_factor); in prs_brb_mem_setup()
3831 DbgMessage(pdev, FATAL, "mem_wrk: part1 NIG timeout val = 0x%x\n",val); in prs_brb_mem_setup()
3839 val=REG_RD(pdev,PRS_REG_NUM_OF_PACKETS); in prs_brb_mem_setup()
3845 mm_wait(pdev,10 * pdev->vars.clk_factor); in prs_brb_mem_setup()
3850 DbgMessage(pdev, FATAL, "mem_wrk: part1 PRS timeout val = 0x%x\n",val); in prs_brb_mem_setup()
3856 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x3); in prs_brb_mem_setup()
3857 mm_wait(pdev,50); in prs_brb_mem_setup()
3858 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x3); in prs_brb_mem_setup()
3859 mm_wait(pdev,50); in prs_brb_mem_setup()
3860 init_brb1_common( pdev ); in prs_brb_mem_setup()
3861 init_prs_common(pdev); in prs_brb_mem_setup()
3863 DbgMessage(pdev, WARN, "mem_wrk start part2\n"); in prs_brb_mem_setup()
3867 REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x0); in prs_brb_mem_setup()
3868 REG_WR(pdev,TCM_REG_PRS_IFEN,0x0); in prs_brb_mem_setup()
3869 REG_WR(pdev,CFC_REG_DEBUG0,0x1); in prs_brb_mem_setup()
3870 REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x0); in prs_brb_mem_setup()
3873 REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x0); in prs_brb_mem_setup()
3878 init_nig_pkt(pdev); in prs_brb_mem_setup()
3885 val=REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET); in prs_brb_mem_setup()
3886 trash=REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET+4); in prs_brb_mem_setup()
3892 mm_wait(pdev,10 * pdev->vars.clk_factor ); in prs_brb_mem_setup()
3897 DbgMessage(pdev, FATAL, "mem_wrk: part2 NIG timeout val = 0x%x\n",val); in prs_brb_mem_setup()
3902 val=REG_RD(pdev,PRS_REG_NUM_OF_PACKETS); in prs_brb_mem_setup()
3906 DbgMessage(pdev, FATAL, "mem_wrk: part2 PRS wait for 2 timeout val = 0x%x\n",val); in prs_brb_mem_setup()
3911 REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x1); in prs_brb_mem_setup()
3914 mm_wait(pdev,100 * pdev->vars.clk_factor); in prs_brb_mem_setup()
3916 val=REG_RD(pdev,PRS_REG_NUM_OF_PACKETS); in prs_brb_mem_setup()
3920 DbgMessage(pdev, FATAL, "mem_wrk: part2 PRS wait for 3 timeout val = 0x%x\n",val); in prs_brb_mem_setup()
3927 trash=REG_RD(pdev,NIG_REG_INGRESS_EOP_LB_FIFO); in prs_brb_mem_setup()
3929 val=REG_RD(pdev,NIG_REG_INGRESS_EOP_LB_EMPTY); in prs_brb_mem_setup()
3933 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x03); in prs_brb_mem_setup()
3934 mm_wait(pdev,50); in prs_brb_mem_setup()
3935 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x03); in prs_brb_mem_setup()
3936 mm_wait(pdev,50); in prs_brb_mem_setup()
3937 init_brb1_common( pdev ); in prs_brb_mem_setup()
3938 init_prs_common(pdev); in prs_brb_mem_setup()
3942 REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x7fffffff); in prs_brb_mem_setup()
3943 REG_WR(pdev,TCM_REG_PRS_IFEN,0x1); in prs_brb_mem_setup()
3944 REG_WR(pdev,CFC_REG_DEBUG0,0x0); in prs_brb_mem_setup()
3945 REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x1); in prs_brb_mem_setup()
3947 DbgMessage(pdev, WARN, "mem_wrk: Finish start part2\n"); in prs_brb_mem_setup()
3951 static void lm_init_intmem_common(struct _lm_device_t *pdev) in lm_init_intmem_common() argument
3955 LM_INTMEM_WRITE16(pdev, XSTORM_COMMON_IP_ID_MASK_OFFSET, 0x8000, BAR_XSTRORM_INTMEM); in lm_init_intmem_common()
3957 …LM_INTMEM_WRITE16(pdev, USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET, (u16_t)pdev->params.l2_dynamic_hc_min_… in lm_init_intmem_common()
3960 if (!CHIP_IS_E1x(pdev)) in lm_init_intmem_common()
3963 if (INTR_BLK_MODE(pdev) == INTR_BLK_MODE_NORM) in lm_init_intmem_common()
3965 LM_INTMEM_WRITE8(pdev, CSTORM_IGU_MODE_OFFSET, HC_IGU_NBC_MODE, BAR_CSTRORM_INTMEM); in lm_init_intmem_common()
3969 LM_INTMEM_WRITE8(pdev, CSTORM_IGU_MODE_OFFSET, HC_IGU_BC_MODE, BAR_CSTRORM_INTMEM); in lm_init_intmem_common()
3975 static void lm_init_intmem_port(struct _lm_device_t *pdev) in lm_init_intmem_port() argument
3980 if (GET_FLAGS( pdev->params.test_mode, TEST_MODE_NO_MCP)) in lm_init_intmem_port()
3984 …DbgMessage(pdev, WARN, "writing reg: %p\n", SHMEM_ABSOLUTE_LICENSE_ADDRESS + (PORT_ID(pdev) * 0x1c… in lm_init_intmem_port()
3985 LM_SHMEM_WRITE(pdev, SHMEM_ABSOLUTE_LICENSE_ADDRESS + (PORT_ID(pdev) * 0x1c), 0xffff); in lm_init_intmem_port()
3988 DbgBreakIf(!pdev->vars.clk_factor); in lm_init_intmem_port()
3989 if(CHIP_IS_E1H(pdev)) in lm_init_intmem_port()
3992 LM_FOREACH_FUNC_IN_PORT(pdev, func) in lm_init_intmem_port()
3995 …LM_INTMEM_WRITE32(pdev,TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + OFFSETOF(struct tstorm_eth_mac_filt… in lm_init_intmem_port()
3996 …LM_INTMEM_WRITE32(pdev,TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + OFFSETOF(struct tstorm_eth_mac_filt… in lm_init_intmem_port()
3997 …LM_INTMEM_WRITE32(pdev,TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + OFFSETOF(struct tstorm_eth_mac_filt… in lm_init_intmem_port()
3998 …LM_INTMEM_WRITE32(pdev,TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + OFFSETOF(struct tstorm_eth_mac_filt… in lm_init_intmem_port()
3999 …LM_INTMEM_WRITE32(pdev,TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + OFFSETOF(struct tstorm_eth_mac_filt… in lm_init_intmem_port()
4003 if (IS_MULTI_VNIC(pdev)) in lm_init_intmem_port()
4006 lm_cmng_init(pdev,10000); in lm_init_intmem_port()
4010 if (IS_MF_SI_MODE(pdev) && pdev->params.npar_vm_switching_enable) in lm_init_intmem_port()
4013 … LM_INTMEM_WRITE32(pdev,XSTORM_TCP_TX_SWITCHING_EN_OFFSET(PORT_ID(pdev)), 1, BAR_XSTRORM_INTMEM); in lm_init_intmem_port()
4017 … if (!CHIP_IS_E1x(pdev)) //no Tx switching in E1, and the internal RAM offset for it is invalid. in lm_init_intmem_port()
4019 … LM_INTMEM_WRITE32(pdev,XSTORM_TCP_TX_SWITCHING_EN_OFFSET(PORT_ID(pdev)), 0, BAR_XSTRORM_INTMEM); in lm_init_intmem_port()
4024 static void lm_init_intmem_eq(struct _lm_device_t * pdev) in lm_init_intmem_eq() argument
4027 u32_t addr = CSTORM_EVENT_RING_DATA_OFFSET(FUNC_ID(pdev)); in lm_init_intmem_eq()
4030 eq_data.base_addr.hi = lm_bd_chain_phys_addr(&pdev->eq_info.eq_chain.bd_chain, 0).as_u32.high; in lm_init_intmem_eq()
4031 eq_data.base_addr.lo = lm_bd_chain_phys_addr(&pdev->eq_info.eq_chain.bd_chain, 0).as_u32.low; in lm_init_intmem_eq()
4032 eq_data.producer = lm_bd_chain_prod_idx(&pdev->eq_info.eq_chain.bd_chain); in lm_init_intmem_eq()
4038 …LM_INTMEM_WRITE32(pdev, addr + (sizeof(u32_t) * index), *((u32 *)&eq_data + index), BAR_CSTRORM_IN… in lm_init_intmem_eq()
4042 static void lm_init_intmem_function(struct _lm_device_t *pdev) in lm_init_intmem_function() argument
4044 u8_t const func = FUNC_ID(pdev); in lm_init_intmem_function()
4047 …REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PAGE_BASE_OFFSET(func)),pdev->sq_info.sq_chain.bd_c… in lm_init_intmem_function()
4048 …REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PAGE_BASE_OFFSET(func)) + 4,pdev->sq_info.sq_chain.… in lm_init_intmem_function()
4049 …REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PROD_OFFSET(func)),pdev->sq_info.sq_chain.prod_idx); in lm_init_intmem_function()
4052 lm_init_intmem_eq(pdev); in lm_init_intmem_function()
4056 if(CHIP_IS_E1(pdev)) in lm_init_intmem_function()
4060 DbgBreakIf(lm_bd_chain_phys_addr(&pdev->eq_info.eq_chain.bd_chain, 0).as_u64 == 0); in lm_init_intmem_function()
4061 …LM_INTMEM_WRITE32(pdev,USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),lm_bd_chain_phys_addr(&pdev->eq_… in lm_init_intmem_function()
4062 …LM_INTMEM_WRITE32(pdev,USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func)+4,lm_bd_chain_phys_addr(&pdev->e… in lm_init_intmem_function()
4066 ASSERT_STATIC( 3 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[0].threshold) ) ; in lm_init_intmem_function()
4069 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func), pdev->vars.int_coal.eth_dynamic_hc_c… in lm_init_intmem_function()
4070 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+4, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4071 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+8, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4074 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+12, (16 - (u8_t)pdev->params.l4_hc_sca… in lm_init_intmem_function()
4077 LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+13, 0, BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4078 LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+14, 0, BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4079 LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+15, 0, BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4081 …ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout0… in lm_init_intmem_function()
4082 …ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout1… in lm_init_intmem_function()
4083 …ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout2… in lm_init_intmem_function()
4084 …ASSERT_STATIC( 4 == ARRSIZE(pdev->vars.int_coal.eth_dynamic_hc_cfg.sm_config[SM_RX_ID].hc_timeout3… in lm_init_intmem_function()
4087 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+16, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4088 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+17, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4089 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+18, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4090 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+19, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4093 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+20, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4094 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+21, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4095 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+22, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4096 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+23, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4099 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+24, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4100 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+25, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4101 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+26, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4102 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+27, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4105 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+28, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4106 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+29, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4107 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+30, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4108 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+31, pdev->vars.int_coal.eth_dynamic_hc… in lm_init_intmem_function()
4111 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET, pdev->vars.int_coal.et… in lm_init_intmem_function()
4112 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+4, pdev->vars.int_coal.… in lm_init_intmem_function()
4113 …LM_INTMEM_WRITE32(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+8, pdev->vars.int_coal.… in lm_init_intmem_function()
4117 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+12, 0, BAR_CSTRORM_INTME… in lm_init_intmem_function()
4118 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+13, 0, BAR_CSTRORM_INTME… in lm_init_intmem_function()
4119 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+14, 0, BAR_CSTRORM_INTME… in lm_init_intmem_function()
4120 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+15, 0, BAR_CSTRORM_INTME… in lm_init_intmem_function()
4123 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+16, pdev->vars.int_coal.… in lm_init_intmem_function()
4124 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+17, pdev->vars.int_coal.… in lm_init_intmem_function()
4125 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+18, pdev->vars.int_coal.… in lm_init_intmem_function()
4126 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+19, pdev->vars.int_coal.… in lm_init_intmem_function()
4129 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+20, pdev->vars.int_coal.… in lm_init_intmem_function()
4130 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+21, pdev->vars.int_coal.… in lm_init_intmem_function()
4131 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+22, pdev->vars.int_coal.… in lm_init_intmem_function()
4132 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+23, pdev->vars.int_coal.… in lm_init_intmem_function()
4135 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+24, pdev->vars.int_coal.… in lm_init_intmem_function()
4136 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+25, pdev->vars.int_coal.… in lm_init_intmem_function()
4137 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+26, pdev->vars.int_coal.… in lm_init_intmem_function()
4138 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+27, pdev->vars.int_coal.… in lm_init_intmem_function()
4141 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+28, pdev->vars.int_coal.… in lm_init_intmem_function()
4142 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+29, pdev->vars.int_coal.… in lm_init_intmem_function()
4143 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+30, pdev->vars.int_coal.… in lm_init_intmem_function()
4144 …LM_INTMEM_WRITE8(pdev,CSTORM_DYNAMIC_HC_CONFIG_OFFSET(func)+TX_DHC_OFFSET+31, pdev->vars.int_coal.… in lm_init_intmem_function()
4147 if (pdev->params.disable_patent_using) in lm_init_intmem_function()
4149 DbgMessage(pdev, WARN, "Patent is disabled\n"); in lm_init_intmem_function()
4150 LM_INTMEM_WRITE8(pdev, TSTORM_TCP_GLOBAL_PARAMS_OFFSET, 0, BAR_TSTRORM_INTMEM); in lm_init_intmem_function()
4155 if (pdev->params.record_sp & XSTORM_RECORD_SLOW_PATH) in lm_init_intmem_function()
4157 … LM_INTMEM_WRITE8(pdev, XSTORM_RECORD_SLOW_PATH_OFFSET(FUNC_ID(pdev)), 1, BAR_XSTRORM_INTMEM); in lm_init_intmem_function()
4160 if (pdev->params.record_sp & CSTORM_RECORD_SLOW_PATH) in lm_init_intmem_function()
4162 … LM_INTMEM_WRITE8(pdev, CSTORM_RECORD_SLOW_PATH_OFFSET(FUNC_ID(pdev)), 1, BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4165 if (pdev->params.record_sp & TSTORM_RECORD_SLOW_PATH) in lm_init_intmem_function()
4167 … LM_INTMEM_WRITE8(pdev, TSTORM_RECORD_SLOW_PATH_OFFSET(FUNC_ID(pdev)), 1, BAR_TSTRORM_INTMEM); in lm_init_intmem_function()
4170 if (pdev->params.record_sp & USTORM_RECORD_SLOW_PATH) in lm_init_intmem_function()
4172 … LM_INTMEM_WRITE8(pdev, USTORM_RECORD_SLOW_PATH_OFFSET(FUNC_ID(pdev)), 1, BAR_USTRORM_INTMEM); in lm_init_intmem_function()
4176 … LM_INTMEM_WRITE8(pdev, XSTORM_VF_TO_PF_OFFSET(FUNC_ID(pdev)), FUNC_ID(pdev), BAR_XSTRORM_INTMEM); in lm_init_intmem_function()
4177 … LM_INTMEM_WRITE8(pdev, CSTORM_VF_TO_PF_OFFSET(FUNC_ID(pdev)), FUNC_ID(pdev), BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4178 … LM_INTMEM_WRITE8(pdev, TSTORM_VF_TO_PF_OFFSET(FUNC_ID(pdev)), FUNC_ID(pdev), BAR_TSTRORM_INTMEM); in lm_init_intmem_function()
4179 … LM_INTMEM_WRITE8(pdev, USTORM_VF_TO_PF_OFFSET(FUNC_ID(pdev)), FUNC_ID(pdev), BAR_USTRORM_INTMEM); in lm_init_intmem_function()
4181 LM_INTMEM_WRITE8(pdev, XSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 1, BAR_XSTRORM_INTMEM); in lm_init_intmem_function()
4182 LM_INTMEM_WRITE8(pdev, CSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 1, BAR_CSTRORM_INTMEM); in lm_init_intmem_function()
4183 LM_INTMEM_WRITE8(pdev, TSTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 1, BAR_TSTRORM_INTMEM); in lm_init_intmem_function()
4184 LM_INTMEM_WRITE8(pdev, USTORM_FUNC_EN_OFFSET(FUNC_ID(pdev)), 1, BAR_USTRORM_INTMEM); in lm_init_intmem_function()
4187 static void init_common_part(struct _lm_device_t *pdev) in init_common_part() argument
4193 const u32_t wait_ms = 200*pdev->vars.clk_factor ; in init_common_part()
4196 const u8_t port = PORT_ID(pdev); in init_common_part()
4198 DbgMessage(pdev, INFORMi, "init_common_part\n"); in init_common_part()
4202 lm_reset_clear_inprogress(pdev); in init_common_part()
4204 DbgBreakIf( !pdev->vars.clk_factor ); in init_common_part()
4206 init_misc_common( pdev ); in init_common_part()
4207 init_pxp_common ( pdev ); in init_common_part()
4208 init_pxp2_common( pdev ); in init_common_part()
4209 init_pglue_b_common(pdev); in init_common_part()
4210 init_atc_common ( pdev ); in init_common_part()
4211 init_dmae_common( pdev ); in init_common_part()
4212 init_tcm_common ( pdev ); in init_common_part()
4213 init_ucm_common ( pdev ); in init_common_part()
4214 init_ccm_common ( pdev ); in init_common_part()
4215 init_xcm_common ( pdev ); in init_common_part()
4216 init_qm_common ( pdev ); in init_common_part()
4217 init_tm_common ( pdev ); in init_common_part()
4218 init_dq_common ( pdev ); in init_common_part()
4219 init_brb1_common( pdev ); in init_common_part()
4220 init_prs_common( pdev); in init_common_part()
4221 init_tsdm_common( pdev ); in init_common_part()
4222 init_csdm_common( pdev ); in init_common_part()
4223 init_usdm_common( pdev ); in init_common_part()
4224 init_xsdm_common( pdev ); in init_common_part()
4226 init_semi_common(pdev); in init_common_part()
4229 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x80000000); in init_common_part()
4230 REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x80000000); in init_common_part()
4232 init_upb_common( pdev ); in init_common_part()
4233 init_xpb_common( pdev ); in init_common_part()
4234 init_pbf_common( pdev ); in init_common_part()
4236 init_src_common(pdev); in init_common_part()
4237 init_cdu_common(pdev); in init_common_part()
4238 init_cfc_common(pdev); in init_common_part()
4239 init_hc_common(pdev); in init_common_part()
4241 if (!CHIP_IS_E1x(pdev) && GET_FLAGS( pdev->params.test_mode, TEST_MODE_NO_MCP)) in init_common_part()
4244 REG_WR(pdev,IGU_REG_RESET_MEMORIES,0x36); in init_common_part()
4246 init_igu_common(pdev); in init_common_part()
4247 init_aeu_common(pdev); in init_common_part()
4248 init_pxpcs_common(pdev); in init_common_part()
4249 init_dbg_common(pdev); in init_common_part()
4250 init_nig_common(pdev); in init_common_part()
4254 REG_WAIT_VERIFY_VAL(pdev, CFC_REG_LL_INIT_DONE,1,wait_ms ); in init_common_part()
4256 REG_WAIT_VERIFY_VAL(pdev, CFC_REG_AC_INIT_DONE,1,wait_ms); in init_common_part()
4258 REG_WAIT_VERIFY_VAL(pdev, CFC_REG_CAM_INIT_DONE,1,wait_ms); in init_common_part()
4260 REG_WR(pdev,CFC_REG_DEBUG0,0); in init_common_part()
4262 if (CHIP_IS_E1(pdev)) in init_common_part()
4265 val = REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET); in init_common_part()
4266 trash = REG_RD(pdev,NIG_REG_STAT2_BRB_OCTET+4); in init_common_part()
4271 prs_brb_mem_setup(pdev); in init_common_part()
4275 lm_setup_fan_failure_detection(pdev); in init_common_part()
4281 if ((pdev->vars.load_code == LM_LOADER_RESPONSE_LOAD_COMMON_CHIP) || in init_common_part()
4282 CHIP_IS_E1x(pdev)) in init_common_part()
4284 shmem_base[0] = pdev->hw_info.shmem_base; in init_common_part()
4285 shmem_base2[0] = pdev->hw_info.shmem_base2; in init_common_part()
4287 if (!CHIP_IS_E1x(pdev)) in init_common_part()
4289 LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem_base_addr), &shmem_base[1]); in init_common_part()
4290 LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem2_base_addr), &shmem_base2[1]); in init_common_part()
4294 if ( !LM_SHMEM2_HAS(pdev, lfa_host_addr[port]) ) in init_common_part()
4296 rc = elink_common_init_phy(pdev, shmem_base, shmem_base2, CHIP_ID(pdev), 0); in init_common_part()
4299 rc = elink_pre_init_phy(pdev, shmem_base[0], shmem_base2[0], CHIP_ID(pdev), port); in init_common_part()
4305 temp = REG_RD(pdev,PXP2_REG_PXP2_INT_STS_CLR_0); in init_common_part()
4308 if(pdev->hw_info.shmem_base2) in init_common_part()
4312 LM_SHMEM2_WRITE(pdev, temp, val ); in init_common_part()
4316 if (IS_MF_AFEX_MODE(pdev)) in init_common_part()
4318 DbgBreakIf(!pdev->hw_info.shmem_base2); in init_common_part()
4319 LM_SHMEM2_WRITE(pdev, OFFSETOF( shmem2_region_t, afex_driver_support), in init_common_part()
4323 if (LM_SHMEM2_HAS(pdev, drv_capabilities_flag)) in init_common_part()
4325 DbgBreakIf(!pdev->hw_info.shmem_base2); in init_common_part()
4327 …LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_capabilities_flag[FUNC_MAILBOX_ID(pdev)]), DRV… in init_common_part()
4331 enable_blocks_attention(pdev); in init_common_part()
4334 if (!CHIP_IS_E1x(pdev)) in init_common_part()
4336 DbgMessage(pdev, WARN, "Enabling parity errors\n"); in init_common_part()
4337 ecore_enable_blocks_parity(pdev); in init_common_part()
4342 void init_port_part(struct _lm_device_t *pdev) in init_port_part() argument
4345 const u8_t port = PORT_ID(pdev); in init_port_part()
4348 elink_phy_probe(&pdev->params.link); in init_port_part()
4350 REG_WR(pdev,(port ? NIG_REG_MASK_INTERRUPT_PORT1 : NIG_REG_MASK_INTERRUPT_PORT0), 0); in init_port_part()
4352 init_misc_port(pdev); in init_port_part()
4353 init_pxp_port(pdev); in init_port_part()
4354 init_pxp2_port(pdev); in init_port_part()
4355 init_pglue_b_port(pdev); in init_port_part()
4356 init_atc_port(pdev); in init_port_part()
4357 init_tcm_port( pdev); in init_port_part()
4358 init_ucm_port( pdev); in init_port_part()
4359 init_ccm_port( pdev); in init_port_part()
4360 init_xcm_port( pdev); in init_port_part()
4361 init_qm_port ( pdev); in init_port_part()
4362 init_tm_port ( pdev); in init_port_part()
4363 init_dq_port ( pdev); in init_port_part()
4364 init_brb_port( pdev); in init_port_part()
4365 init_prs_port( pdev); in init_port_part()
4366 init_tsdm_port( pdev); in init_port_part()
4367 init_csdm_port( pdev); in init_port_part()
4368 init_usdm_port( pdev); in init_port_part()
4369 init_xsdm_port( pdev); in init_port_part()
4371 init_semi_port(pdev); in init_port_part()
4372 init_upb_port(pdev); in init_port_part()
4373 init_xpb_port(pdev); in init_port_part()
4374 init_pbf_port( pdev ); in init_port_part()
4375 init_src_port(pdev); in init_port_part()
4376 init_cdu_port(pdev); in init_port_part()
4377 init_cfc_port(pdev); in init_port_part()
4378 init_hc_port( pdev); in init_port_part()
4379 init_igu_port( pdev); in init_port_part()
4380 init_aeu_port( pdev); in init_port_part()
4381 init_dbg_port(pdev); in init_port_part()
4383 init_nig_port( pdev); in init_port_part()
4384 init_dmae_port(pdev); in init_port_part()
4387 MM_ACQUIRE_PHY_LOCK(pdev); in init_port_part()
4388 lm_stats_init_port_part(pdev); in init_port_part()
4389 …elink_init_mod_abs_int(pdev, &pdev->vars.link, CHIP_ID(pdev), pdev->hw_info.shmem_base, pdev->hw_i… in init_port_part()
4390 MM_RELEASE_PHY_LOCK(pdev); in init_port_part()
4393 if (!GET_FLAGS( pdev->params.test_mode, TEST_MODE_NO_MCP)) in init_port_part()
4395 … LM_SHMEM_READ(pdev, OFFSETOF(shmem_region_t,dev_info.port_feature_config[port].config), &val ); in init_port_part()
4397 … LM_SHMEM_WRITE(pdev, OFFSETOF(shmem_region_t,dev_info.port_feature_config[port].config), val ); in init_port_part()
4400 lm_dcbx_config_drv_flags(pdev, lm_dcbx_drv_flags_reset_flags,0); in init_port_part()
4403 void init_function_part(struct _lm_device_t *pdev) in init_function_part() argument
4405 const u8_t func = FUNC_ID(pdev); in init_function_part()
4406 const u8_t func_mb_id = FUNC_MAILBOX_ID(pdev); in init_function_part()
4408 DbgMessage(pdev, INFORMi, "init_function_part, func=%d\n", func); in init_function_part()
4410 if (!CHIP_IS_E1x(pdev) && LM_SHMEM2_HAS(pdev, drv_capabilities_flag)) in init_function_part()
4413 …LM_SHMEM2_WRITE(pdev, OFFSETOF(shmem2_region_t, drv_capabilities_flag[func_mb_id]), DRV_FLAGS_CAPA… in init_function_part()
4416 init_pxp_func(pdev); in init_function_part()
4417 init_pxp2_func( pdev ); in init_function_part()
4418 init_pglue_b_func(pdev); in init_function_part()
4419 init_atc_func(pdev); in init_function_part()
4420 init_misc_func(pdev); in init_function_part()
4421 init_tcm_func(pdev); in init_function_part()
4422 init_ucm_func(pdev); in init_function_part()
4423 init_ccm_func(pdev); in init_function_part()
4424 init_xcm_func(pdev); in init_function_part()
4425 init_semi_func(pdev); in init_function_part()
4426 init_qm_func(pdev); in init_function_part()
4427 init_tm_func(pdev); in init_function_part()
4428 init_dq_func(pdev); in init_function_part()
4429 init_brb_func(pdev); in init_function_part()
4430 init_prs_func(pdev); in init_function_part()
4431 init_tsdm_func(pdev); in init_function_part()
4432 init_csdm_func(pdev); in init_function_part()
4433 init_usdm_func(pdev); in init_function_part()
4434 init_xsdm_func(pdev); in init_function_part()
4435 init_upb_func(pdev); in init_function_part()
4436 init_xpb_func(pdev); in init_function_part()
4438 init_pbf_func(pdev); in init_function_part()
4439 init_src_func(pdev); in init_function_part()
4440 init_cdu_func(pdev); in init_function_part()
4441 init_cfc_func(pdev); in init_function_part()
4442 init_hc_func(pdev); in init_function_part()
4443 init_igu_func(pdev); in init_function_part()
4444 init_aeu_func(pdev); in init_function_part()
4445 init_pxpcs_func(pdev); in init_function_part()
4446 init_dbg_func(pdev); in init_function_part()
4447 init_nig_func( pdev); in init_function_part()
4448 init_dmae_func(pdev); in init_function_part()
4452 elink_phy_probe(&pdev->params.link); in init_function_part()
4453 if (IS_PMF(pdev) && IS_MULTI_VNIC(pdev)) in init_function_part()
4455 DbgMessage(pdev, WARN, "init_function_part: Func %d is the PMF\n", func ); in init_function_part()
4458 MM_ACQUIRE_PHY_LOCK(pdev); in init_function_part()
4459 lm_stats_init_func_part(pdev); in init_function_part()
4460 MM_RELEASE_PHY_LOCK(pdev); in init_function_part()
4478 lm_chip_ready_for_init( struct _lm_device_t *pdev) in lm_chip_ready_for_init() argument
4480 lm_igu_info_t * igu_info = &pdev->hw_info.intr_blk_info.igu_info; in lm_chip_ready_for_init()
4481 const u8_t blk_type = INTR_BLK_TYPE(pdev); in lm_chip_ready_for_init()
4482 const u8_t blk_mode = INTR_BLK_MODE(pdev); in lm_chip_ready_for_init()
4496 lm_status_t lm_init_common_chip_part(struct _lm_device_t *pdev) in lm_init_common_chip_part() argument
4502 lm_fl_reset_clear_inprogress(pdev); in lm_init_common_chip_part()
4505 val = convert_to_bcd( pdev->product_version ); in lm_init_common_chip_part()
4506 lm_ncsi_drv_ver_to_scratchpad(pdev, val ); in lm_init_common_chip_part()
4518 lm_chip_init( struct _lm_device_t *pdev) in lm_chip_init() argument
4526 DbgMessage(pdev, INFORMi , "### lm_chip_init %x\n",CHIP_NUM(pdev)); in lm_chip_init()
4529 if (IS_VFDEV(pdev)) in lm_chip_init()
4531 return lm_vf_chip_init(pdev); in lm_chip_init()
4535 if (!lm_chip_ready_for_init(pdev)) in lm_chip_init()
4544 if (IS_PFDEV(pdev)) in lm_chip_init()
4546 lm_reset_device_if_undi_active(pdev); in lm_chip_init()
4550 lm_status = lm_mcp_cmd_init(pdev); in lm_chip_init()
4554 DbgMessage(pdev, FATAL, "lm_chip_init: mcp_cmd_init failed. lm_status=0x%x\n", lm_status); in lm_chip_init()
4559 INIT_MODE_FLAGS(pdev) = lm_init_get_modes_bitmap(pdev); in lm_chip_init()
4561 resp = lm_loader_lock(pdev, opcode ); in lm_chip_init()
4565 pdev->vars.load_code = resp; in lm_chip_init()
4568 lm_driver_pulse_always_alive(pdev); in lm_chip_init()
4572 if (IS_ASSIGNED_TO_VM_PFDEV(pdev)) in lm_chip_init()
4579 if (!lm_is_fw_version_valid(pdev)) in lm_chip_init()
4581 lm_loader_lock(pdev, LM_LOADER_OPCODE_UNLOAD_WOL_MCP); in lm_chip_init()
4582 lm_loader_unlock(pdev, LM_LOADER_OPCODE_UNLOAD_WOL_MCP, NULL ); in lm_chip_init()
4591 …lm_setup_read_mgmt_stats_ptr(pdev, FUNC_MAILBOX_ID(pdev), &pdev->vars.fw_port_stats_ptr, &pdev->va… in lm_chip_init()
4594 if (!IS_DRIVER_PULSE_ALWAYS_ALIVE(pdev)) in lm_chip_init()
4596 if(LM_STATUS_SUCCESS != lm_send_driver_pulse(pdev)) in lm_chip_init()
4598 lm_driver_pulse_always_alive(pdev); in lm_chip_init()
4604 lm_status = lm_get_pcicfg_mps_mrrs(pdev); in lm_chip_init()
4606 if (!IS_ASSIGNED_TO_VM_PFDEV(pdev)) in lm_chip_init()
4608 lm_pcie_state_restore_for_d0( pdev); in lm_chip_init()
4614 lm_status = lm_init_common_chip_part(pdev); in lm_chip_init()
4622 lm_fl_reset_clear_inprogress(pdev); in lm_chip_init()
4624 lm_reset_path( pdev, FALSE ); /* Give a chip-reset (path) before initializing driver*/ in lm_chip_init()
4625 init_common_part(pdev); in lm_chip_init()
4626 … if (IS_MULTI_VNIC(pdev) && CHIP_IS_E2E3(pdev) && CHIP_PORT_MODE(pdev) == LM_CHIP_PORT_MODE_2) in lm_chip_init()
4632 for (i = 0; i < VNICS_PER_PATH(pdev); i++) in lm_chip_init()
4634 REG_WR(pdev, start_reg + 4 * i, function_number + 2 * i); in lm_chip_init()
4638 lm_init_intmem_common(pdev); in lm_chip_init()
4643 mm_dbus_stop_if_started(pdev); in lm_chip_init()
4646 mm_dbus_start_if_enable(pdev); in lm_chip_init()
4651 if (lm_is_function_after_flr(pdev)) in lm_chip_init()
4653 if (IS_PFDEV(pdev)) in lm_chip_init()
4655 lm_status = lm_cleanup_after_flr(pdev); in lm_chip_init()
4664 lm_fl_reset_clear_inprogress(pdev); in lm_chip_init()
4669 pdev->vars.b_is_dmae_ready = TRUE; in lm_chip_init()
4672 pdev->vars.is_pmf = PMF_ORIGINAL; in lm_chip_init()
4674 init_port_part(pdev); in lm_chip_init()
4675 lm_init_intmem_port(pdev); in lm_chip_init()
4680 if (lm_is_function_after_flr(pdev)) in lm_chip_init()
4682 if (IS_PFDEV(pdev)) in lm_chip_init()
4684 lm_status = lm_cleanup_after_flr(pdev); in lm_chip_init()
4693 lm_fl_reset_clear_inprogress(pdev); in lm_chip_init()
4698 pdev->vars.b_is_dmae_ready = TRUE; in lm_chip_init()
4699 init_function_part(pdev); in lm_chip_init()
4700 init_status_blocks(pdev); in lm_chip_init()
4701 lm_init_intmem_function(pdev); in lm_chip_init()
4703 lm_tcp_init_chip_common(pdev); in lm_chip_init()
4708 DbgMessage(pdev, WARN, "wrong loader response\n"); in lm_chip_init()
4712 resp = lm_loader_unlock( pdev, opcode, NULL ) ; in lm_chip_init()
4716 DbgMessage(pdev, WARN, "wrong loader response\n"); in lm_chip_init()
4726 if (IS_MF_MODE_CAPABLE(pdev)) in lm_chip_init()
4728 lm_get_shmem_info(pdev); in lm_chip_init()