Lines Matching refs:pdev
31 static int ecore_gunzip(struct _lm_device_t *pdev, const u8 *zbuf, int len);
32 static void ecore_reg_wr_ind(struct _lm_device_t *pdev, u32 addr, u32 val);
33 static void ecore_write_dmae_phys_len(struct _lm_device_t *pdev,
37 static void ecore_init_str_wr(struct _lm_device_t *pdev, u32 addr, in ecore_init_str_wr() argument
43 REG_WR(pdev, addr + i*4, data[i]); in ecore_init_str_wr()
46 static void ecore_init_ind_wr(struct _lm_device_t *pdev, u32 addr, in ecore_init_ind_wr() argument
52 ecore_reg_wr_ind(pdev, addr + i*4, data[i]); in ecore_init_ind_wr()
55 static void ecore_write_big_buf(struct _lm_device_t *pdev, u32 addr, u32 len, in ecore_write_big_buf() argument
58 if (DMAE_READY(pdev)) in ecore_write_big_buf()
59 ecore_write_dmae_phys_len(pdev, GUNZIP_PHYS(pdev), addr, len); in ecore_write_big_buf()
62 else if (wb && CHIP_IS_E1(pdev)) in ecore_write_big_buf()
63 ecore_init_ind_wr(pdev, addr, GUNZIP_BUF(pdev), len); in ecore_write_big_buf()
67 ecore_init_str_wr(pdev, addr, GUNZIP_BUF(pdev), len); in ecore_write_big_buf()
70 static void ecore_init_fill(struct _lm_device_t *pdev, u32 addr, int fill, in ecore_init_fill() argument
77 mm_memset(GUNZIP_BUF(pdev), (u8)fill, buf_len); in ecore_init_fill()
82 ecore_write_big_buf(pdev, addr + i*4, cur_len, wb); in ecore_init_fill()
86 static void ecore_write_big_buf_wb(struct _lm_device_t *pdev, u32 addr, u32 len) in ecore_write_big_buf_wb() argument
88 if (DMAE_READY(pdev)) in ecore_write_big_buf_wb()
89 ecore_write_dmae_phys_len(pdev, GUNZIP_PHYS(pdev), addr, len); in ecore_write_big_buf_wb()
92 else if (CHIP_IS_E1(pdev)) in ecore_write_big_buf_wb()
93 ecore_init_ind_wr(pdev, addr, GUNZIP_BUF(pdev), len); in ecore_write_big_buf_wb()
97 ecore_init_str_wr(pdev, addr, GUNZIP_BUF(pdev), len); in ecore_write_big_buf_wb()
100 static void ecore_init_wr_64(struct _lm_device_t *pdev, u32 addr, in ecore_init_wr_64() argument
113 u64 *pdata = ((u64 *)(GUNZIP_BUF(pdev))) + i; in ecore_init_wr_64()
121 ecore_write_big_buf_wb(pdev, addr + i*4, cur_len); in ecore_init_wr_64()
139 static const u8 *ecore_sel_blob(struct _lm_device_t *pdev, u32 addr, in ecore_sel_blob() argument
143 data = INIT_TSEM_INT_TABLE_DATA(pdev); in ecore_sel_blob()
146 data = INIT_CSEM_INT_TABLE_DATA(pdev); in ecore_sel_blob()
149 data = INIT_USEM_INT_TABLE_DATA(pdev); in ecore_sel_blob()
152 data = INIT_XSEM_INT_TABLE_DATA(pdev); in ecore_sel_blob()
155 data = INIT_TSEM_PRAM_DATA(pdev); in ecore_sel_blob()
158 data = INIT_CSEM_PRAM_DATA(pdev); in ecore_sel_blob()
161 data = INIT_USEM_PRAM_DATA(pdev); in ecore_sel_blob()
164 data = INIT_XSEM_PRAM_DATA(pdev); in ecore_sel_blob()
169 static void ecore_init_wr_wb(struct _lm_device_t *pdev, u32 addr, in ecore_init_wr_wb() argument
172 if (DMAE_READY(pdev)) in ecore_init_wr_wb()
173 VIRT_WR_DMAE_LEN(pdev, data, addr, len, 0); in ecore_init_wr_wb()
176 else if (CHIP_IS_E1(pdev)) in ecore_init_wr_wb()
177 ecore_init_ind_wr(pdev, addr, data, len); in ecore_init_wr_wb()
181 ecore_init_str_wr(pdev, addr, data, len); in ecore_init_wr_wb()
185 static void ecore_init_fw(struct _lm_device_t *pdev, u32 addr, u32 len) in ecore_init_fw() argument
189 data = ecore_sel_blob(pdev, addr, (const u8 *)data); in ecore_init_fw()
191 if (DMAE_READY(pdev)) in ecore_init_fw()
192 VIRT_WR_DMAE_LEN(pdev, data, addr, len, 1); in ecore_init_fw()
195 else if (CHIP_IS_E1(pdev)) in ecore_init_fw()
196 ecore_init_ind_wr(pdev, addr, (const u32 *)data, len); in ecore_init_fw()
200 ecore_init_str_wr(pdev, addr, (const u32 *)data, len); in ecore_init_fw()
206 static void ecore_wr_64(struct _lm_device_t *pdev, u32 reg, u32 val_lo, in ecore_wr_64() argument
213 REG_WR_DMAE_LEN(pdev, reg, wb_write, 2); in ecore_wr_64()
217 static void ecore_init_wr_zp(struct _lm_device_t *pdev, u32 addr, u32 len, in ecore_init_wr_zp() argument
224 data = ecore_sel_blob(pdev, addr, data) + blob_off*4; in ecore_init_wr_zp()
226 rc = ecore_gunzip(pdev, data, len); in ecore_init_wr_zp()
231 len = GUNZIP_OUTLEN(pdev); in ecore_init_wr_zp()
233 ((u32 *)GUNZIP_BUF(pdev))[i] = FORCE32 in ecore_init_wr_zp()
234 mm_cpu_to_le32(((u32 *)GUNZIP_BUF(pdev))[i]); in ecore_init_wr_zp()
236 ecore_write_big_buf_wb(pdev, addr, len); in ecore_init_wr_zp()
239 static void ecore_init_block(struct _lm_device_t *pdev, u32 block, u32 stage) in ecore_init_block() argument
242 INIT_OPS_OFFSETS(pdev)[BLOCK_OPS_IDX(block, stage, in ecore_init_block()
245 INIT_OPS_OFFSETS(pdev)[BLOCK_OPS_IDX(block, stage, in ecore_init_block()
255 data_base = INIT_DATA(pdev); in ecore_init_block()
259 op = (const union init_op *)&(INIT_OPS(pdev)[op_idx]); in ecore_init_block()
272 REG_RD(pdev, addr); in ecore_init_block()
275 REG_WR(pdev, addr, op->write.val); in ecore_init_block()
278 ecore_init_str_wr(pdev, addr, data, len); in ecore_init_block()
281 ecore_init_wr_wb(pdev, addr, data, len); in ecore_init_block()
285 ecore_init_fw(pdev, addr, len); in ecore_init_block()
289 ecore_init_fill(pdev, addr, 0, op->zero.len, 0); in ecore_init_block()
292 ecore_init_fill(pdev, addr, 0, op->zero.len, 1); in ecore_init_block()
295 ecore_init_wr_zp(pdev, addr, len, in ecore_init_block()
299 ecore_init_wr_64(pdev, addr, data, len); in ecore_init_block()
305 if ((INIT_MODE_FLAGS(pdev) & in ecore_init_block()
314 if ((INIT_MODE_FLAGS(pdev) & in ecore_init_block()
497 static void ecore_init_pxp_arb(struct _lm_device_t *pdev, int r_order, in ecore_init_pxp_arb() argument
503 DbgMessage(pdev, WARNi, "read order of %d order adjusted to %d\n", in ecore_init_pxp_arb()
508 DbgMessage(pdev, WARNi, "write order of %d order adjusted to %d\n", in ecore_init_pxp_arb()
512 if (CHIP_REV_IS_FPGA(pdev)) { in ecore_init_pxp_arb()
513 DbgMessage(pdev, WARNi, "write order adjusted to 1 for FPGA\n"); in ecore_init_pxp_arb()
516 DbgMessage(pdev, INFORMi, "read order %d write order %d\n", r_order, w_order); in ecore_init_pxp_arb()
519 REG_WR(pdev, read_arb_addr[i].l, read_arb_data[i][r_order].l); in ecore_init_pxp_arb()
520 REG_WR(pdev, read_arb_addr[i].add, in ecore_init_pxp_arb()
522 REG_WR(pdev, read_arb_addr[i].ubound, in ecore_init_pxp_arb()
530 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
533 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
536 REG_WR(pdev, write_arb_addr[i].ubound, in ecore_init_pxp_arb()
540 val = REG_RD(pdev, write_arb_addr[i].l); in ecore_init_pxp_arb()
541 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
544 val = REG_RD(pdev, write_arb_addr[i].add); in ecore_init_pxp_arb()
545 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
548 val = REG_RD(pdev, write_arb_addr[i].ubound); in ecore_init_pxp_arb()
549 REG_WR(pdev, write_arb_addr[i].ubound, in ecore_init_pxp_arb()
557 REG_WR(pdev, PXP2_REG_PSWRQ_BW_RD, val); in ecore_init_pxp_arb()
562 REG_WR(pdev, PXP2_REG_PSWRQ_BW_WR, val); in ecore_init_pxp_arb()
564 REG_WR(pdev, PXP2_REG_RQ_WR_MBS0, w_order); in ecore_init_pxp_arb()
565 REG_WR(pdev, PXP2_REG_RQ_WR_MBS1, w_order); in ecore_init_pxp_arb()
566 REG_WR(pdev, PXP2_REG_RQ_RD_MBS0, r_order); in ecore_init_pxp_arb()
567 REG_WR(pdev, PXP2_REG_RQ_RD_MBS1, r_order); in ecore_init_pxp_arb()
569 if ((CHIP_IS_E1(pdev) || CHIP_IS_E1H(pdev)) && (r_order == MAX_RD_ORD)) in ecore_init_pxp_arb()
570 REG_WR(pdev, PXP2_REG_RQ_PDR_LIMIT, 0xe00); in ecore_init_pxp_arb()
572 if (CHIP_IS_E3(pdev)) in ecore_init_pxp_arb()
573 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); in ecore_init_pxp_arb()
574 else if (CHIP_IS_E2(pdev)) in ecore_init_pxp_arb()
575 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); in ecore_init_pxp_arb()
577 REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); in ecore_init_pxp_arb()
579 if (!CHIP_IS_E1(pdev)) { in ecore_init_pxp_arb()
586 if (!CHIP_IS_E1H(pdev)) { in ecore_init_pxp_arb()
589 REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, val); in ecore_init_pxp_arb()
592 REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, 2); in ecore_init_pxp_arb()
595 REG_WR(pdev, PXP2_REG_WR_HC_MPS, val); in ecore_init_pxp_arb()
596 REG_WR(pdev, PXP2_REG_WR_USDM_MPS, val); in ecore_init_pxp_arb()
597 REG_WR(pdev, PXP2_REG_WR_CSDM_MPS, val); in ecore_init_pxp_arb()
598 REG_WR(pdev, PXP2_REG_WR_TSDM_MPS, val); in ecore_init_pxp_arb()
599 REG_WR(pdev, PXP2_REG_WR_XSDM_MPS, val); in ecore_init_pxp_arb()
600 REG_WR(pdev, PXP2_REG_WR_QM_MPS, val); in ecore_init_pxp_arb()
601 REG_WR(pdev, PXP2_REG_WR_TM_MPS, val); in ecore_init_pxp_arb()
602 REG_WR(pdev, PXP2_REG_WR_SRC_MPS, val); in ecore_init_pxp_arb()
603 REG_WR(pdev, PXP2_REG_WR_DBG_MPS, val); in ecore_init_pxp_arb()
604 REG_WR(pdev, PXP2_REG_WR_CDU_MPS, val); in ecore_init_pxp_arb()
609 val = REG_RD(pdev, PCIE_REG_PCIER_TL_HDR_FC_ST); in ecore_init_pxp_arb()
612 REG_WR(pdev, PXP2_REG_PGL_TAGS_LIMIT, 0x20); in ecore_init_pxp_arb()
641 static int ecore_ilt_line_mem_op(struct _lm_device_t *pdev, in ecore_ilt_line_mem_op() argument
656 static int ecore_ilt_client_mem_op(struct _lm_device_t *pdev, int cli_num, in ecore_ilt_client_mem_op() argument
660 struct ecore_ilt *ilt = PDEV_ILT(pdev); in ecore_ilt_client_mem_op()
670 rc = ecore_ilt_line_mem_op(pdev, &ilt->lines[i], in ecore_ilt_client_mem_op()
676 static int ecore_ilt_mem_op_cnic(struct _lm_device_t *pdev, u8 memop) in ecore_ilt_mem_op_cnic() argument
680 if (CONFIGURE_NIC_MODE(pdev)) in ecore_ilt_mem_op_cnic()
681 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_SRC, memop); in ecore_ilt_mem_op_cnic()
683 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_TM, memop); in ecore_ilt_mem_op_cnic()
688 static int ecore_ilt_mem_op(struct _lm_device_t *pdev, u8 memop) in ecore_ilt_mem_op() argument
690 int rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_CDU, memop); in ecore_ilt_mem_op()
692 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_QM, memop); in ecore_ilt_mem_op()
693 if (!rc && CNIC_SUPPORT(pdev) && !CONFIGURE_NIC_MODE(pdev)) in ecore_ilt_mem_op()
694 rc = ecore_ilt_client_mem_op(pdev, ILT_CLIENT_SRC, memop); in ecore_ilt_mem_op()
699 static void ecore_ilt_line_wr(struct _lm_device_t *pdev, int abs_idx, in ecore_ilt_line_wr() argument
704 if (CHIP_IS_E1(pdev)) in ecore_ilt_line_wr()
709 ecore_wr_64(pdev, reg, ILT_ADDR1(page_mapping.as_u64), ILT_ADDR2(page_mapping.as_u64)); in ecore_ilt_line_wr()
712 static void ecore_ilt_line_init_op(struct _lm_device_t *pdev, in ecore_ilt_line_init_op() argument
723 ecore_ilt_line_wr(pdev, abs_idx, ilt->lines[idx].page_mapping); in ecore_ilt_line_init_op()
727 ecore_ilt_line_wr(pdev, abs_idx, null_mapping); in ecore_ilt_line_init_op()
732 static void ecore_ilt_boundry_init_op(struct _lm_device_t *pdev, in ecore_ilt_boundry_init_op() argument
743 if (CHIP_IS_E1(pdev)) { in ecore_ilt_boundry_init_op()
758 REG_WR(pdev, start_reg + PDEV_FUNC(pdev)*4, in ecore_ilt_boundry_init_op()
780 REG_WR(pdev, start_reg, (ilt_start + ilt_cli->start)); in ecore_ilt_boundry_init_op()
781 REG_WR(pdev, end_reg, (ilt_start + ilt_cli->end)); in ecore_ilt_boundry_init_op()
785 static void ecore_ilt_client_init_op_ilt(struct _lm_device_t *pdev, in ecore_ilt_client_init_op_ilt() argument
796 ecore_ilt_line_init_op(pdev, ilt, i, initop); in ecore_ilt_client_init_op_ilt()
799 ecore_ilt_boundry_init_op(pdev, ilt_cli, ilt->start_line, initop); in ecore_ilt_client_init_op_ilt()
802 static void ecore_ilt_client_init_op(struct _lm_device_t *pdev, in ecore_ilt_client_init_op() argument
805 struct ecore_ilt *ilt = PDEV_ILT(pdev); in ecore_ilt_client_init_op()
807 ecore_ilt_client_init_op_ilt(pdev, ilt, ilt_cli, initop); in ecore_ilt_client_init_op()
810 static void ecore_ilt_client_id_init_op(struct _lm_device_t *pdev, in ecore_ilt_client_id_init_op() argument
813 struct ecore_ilt *ilt = PDEV_ILT(pdev); in ecore_ilt_client_id_init_op()
816 ecore_ilt_client_init_op(pdev, ilt_cli, initop); in ecore_ilt_client_id_init_op()
819 static void ecore_ilt_init_op_cnic(struct _lm_device_t *pdev, u8 initop) in ecore_ilt_init_op_cnic() argument
821 if (CONFIGURE_NIC_MODE(pdev)) in ecore_ilt_init_op_cnic()
822 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_SRC, initop); in ecore_ilt_init_op_cnic()
823 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_TM, initop); in ecore_ilt_init_op_cnic()
826 static void ecore_ilt_init_op(struct _lm_device_t *pdev, u8 initop) in ecore_ilt_init_op() argument
828 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_CDU, initop); in ecore_ilt_init_op()
829 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_QM, initop); in ecore_ilt_init_op()
830 if (CNIC_SUPPORT(pdev) && !CONFIGURE_NIC_MODE(pdev)) in ecore_ilt_init_op()
831 ecore_ilt_client_id_init_op(pdev, ILT_CLIENT_SRC, initop); in ecore_ilt_init_op()
834 static void ecore_ilt_init_client_psz(struct _lm_device_t *pdev, int cli_num, in ecore_ilt_init_client_psz() argument
837 struct ecore_ilt *ilt = PDEV_ILT(pdev); in ecore_ilt_init_client_psz()
847 REG_WR(pdev, psz_reg, ILOG2(ilt_cli->page_size >> 12)); in ecore_ilt_init_client_psz()
858 static void ecore_ilt_init_page_size(struct _lm_device_t *pdev, u8 initop) in ecore_ilt_init_page_size() argument
860 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_CDU, in ecore_ilt_init_page_size()
862 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_QM, in ecore_ilt_init_page_size()
864 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_SRC, in ecore_ilt_init_page_size()
866 ecore_ilt_init_client_psz(pdev, ILT_CLIENT_TM, in ecore_ilt_init_page_size()
878 static void ecore_qm_init_cid_count(struct _lm_device_t *pdev, int qm_cid_count, in ecore_qm_init_cid_count() argument
881 int port = PDEV_PORT(pdev); in ecore_qm_init_cid_count()
888 REG_WR(pdev, QM_REG_CONNNUM_0 + port*4, in ecore_qm_init_cid_count()
897 static void ecore_qm_set_ptr_table(struct _lm_device_t *pdev, int qm_cid_count, in ecore_qm_set_ptr_table() argument
903 REG_WR(pdev, base_reg + i*4, in ecore_qm_set_ptr_table()
905 ecore_init_wr_wb(pdev, reg + i*8, in ecore_qm_set_ptr_table()
911 static void ecore_qm_init_ptr_table(struct _lm_device_t *pdev, int qm_cid_count, in ecore_qm_init_ptr_table() argument
921 ecore_qm_set_ptr_table(pdev, qm_cid_count, in ecore_qm_init_ptr_table()
923 if (CHIP_IS_E1H(pdev)) in ecore_qm_init_ptr_table()
924 ecore_qm_set_ptr_table(pdev, qm_cid_count, in ecore_qm_init_ptr_table()
939 static void ecore_src_init_t2(struct _lm_device_t *pdev, struct src_ent *t2, in ecore_src_init_t2() argument
943 int port = PDEV_PORT(pdev); in ecore_src_init_t2()
951 REG_WR(pdev, SRC_REG_COUNTFREE0 + port*4, src_cid_count); in ecore_src_init_t2()
953 ecore_wr_64(pdev, SRC_REG_FIRSTFREE0 + port*16, in ecore_src_init_t2()
956 ecore_wr_64(pdev, SRC_REG_LASTFREE0 + port*16, in ecore_src_init_t2()