Lines Matching refs:pdev
26 lm_device_t *pdev, in lm_set_mac_addr() argument
40 REG_WR(pdev, emac.emac_mac_match[addr_idx*2], val); in lm_set_mac_addr()
44 REG_WR(pdev, emac.emac_mac_match[addr_idx*2+1], val); in lm_set_mac_addr()
63 lm_device_t *pdev, in lm_reg_rd_ind() argument
69 mm_acquire_ind_reg_lock(pdev); in lm_reg_rd_ind()
71 REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset); in lm_reg_rd_ind()
72 REG_RD(pdev, pci_config.pcicfg_reg_window, ret); in lm_reg_rd_ind()
74 mm_release_ind_reg_lock(pdev); in lm_reg_rd_ind()
91 lm_device_t *pdev, in lm_reg_wr_ind() argument
97 mm_acquire_ind_reg_lock(pdev); in lm_reg_wr_ind()
99 REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset); in lm_reg_wr_ind()
100 REG_WR(pdev, pci_config.pcicfg_reg_window, val); in lm_reg_wr_ind()
102 mm_release_ind_reg_lock(pdev); in lm_reg_wr_ind()
114 lm_device_t *pdev, in lm_ctx_wr() argument
126 if(CHIP_NUM(pdev) == CHIP_NUM_5709) in lm_ctx_wr()
128 if (CHIP_REV(pdev) == CHIP_REV_IKOS) in lm_ctx_wr()
137 REG_WR(pdev, context.ctx_ctx_data, val); in lm_ctx_wr()
138 REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_WRITE_REQ); in lm_ctx_wr()
142 REG_RD(pdev, context.ctx_ctx_ctrl, &val); in lm_ctx_wr()
149 mm_wait(pdev, 10); in lm_ctx_wr()
156 REG_WR(pdev, context.ctx_data_adr, offset); in lm_ctx_wr()
157 REG_WR(pdev, context.ctx_data, val); in lm_ctx_wr()
170 lm_device_t *pdev, in lm_ctx_rd() argument
182 if(CHIP_NUM(pdev) == CHIP_NUM_5709) in lm_ctx_rd()
184 if(CHIP_REV(pdev) == CHIP_REV_IKOS) in lm_ctx_rd()
193 REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_READ_REQ); in lm_ctx_rd()
197 REG_RD(pdev, context.ctx_ctx_ctrl, &val); in lm_ctx_rd()
204 mm_wait(pdev, 5); in lm_ctx_rd()
209 REG_RD(pdev, context.ctx_ctx_data, &val); in lm_ctx_rd()
213 REG_WR(pdev, context.ctx_data_adr, offset); in lm_ctx_rd()
214 REG_RD(pdev, context.ctx_data, &val); in lm_ctx_rd()
229 lm_device_t *pdev) in lm_disable_int() argument
234 switch(CHIP_NUM(pdev)) in lm_disable_int()
238 REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); in lm_disable_int()
240 REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); in lm_disable_int()
247 REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); in lm_disable_int()
266 lm_device_t *pdev) in lm_enable_int() argument
270 switch(CHIP_NUM(pdev)) in lm_enable_int()
274 REG_RD(pdev, pci_config.pcicfg_int_ack_cmd, &val); in lm_enable_int()
276 REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val); in lm_enable_int()
280 REG_RD(pdev, hc.hc_config, &val); in lm_enable_int()
282 REG_WR(pdev, hc.hc_config, val); in lm_enable_int()
300 lm_device_t *pdev, in lm_reg_rd_blk() argument
313 REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); in lm_reg_rd_blk()
322 REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); in lm_reg_rd_blk()
325 REG_RD_OFFSET(pdev, GRC_WINDOW_BASE + grc_win_offset, buf_ptr); in lm_reg_rd_blk()
332 REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff); in lm_reg_rd_blk()
344 lm_device_t *pdev, in lm_reg_rd_blk_ind() argument
351 mm_acquire_ind_reg_lock(pdev); in lm_reg_rd_blk_ind()
355 REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset); in lm_reg_rd_blk_ind()
356 REG_RD(pdev, pci_config.pcicfg_reg_window, buf_ptr); in lm_reg_rd_blk_ind()
363 mm_release_ind_reg_lock(pdev); in lm_reg_rd_blk_ind()
375 lm_device_t *pdev, in lm_reg_wr_blk() argument
386 if (CHIP_NUM(pdev) == CHIP_NUM_5709) in lm_reg_wr_blk()
398 REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); in lm_reg_wr_blk()
407 REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); in lm_reg_wr_blk()
410 REG_WR_OFFSET(pdev, GRC_WINDOW_BASE + grc_win_offset, *data_ptr); in lm_reg_wr_blk()
417 REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff); in lm_reg_wr_blk()
429 lm_device_t *pdev, in lm_reg_wr_blk_ind() argument
436 mm_acquire_ind_reg_lock(pdev); in lm_reg_wr_blk_ind()
440 REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset); in lm_reg_wr_blk_ind()
441 REG_WR(pdev, pci_config.pcicfg_reg_window, *data_ptr); in lm_reg_wr_blk_ind()
448 mm_release_ind_reg_lock(pdev); in lm_reg_wr_blk_ind()
460 lm_device_t *pdev, in lm_submit_fw_cmd() argument
465 if(pdev->vars.fw_timed_out) in lm_submit_fw_cmd()
467 DbgMessage(pdev, WARN, "fw timed out.\n"); in lm_submit_fw_cmd()
475 pdev, in lm_submit_fw_cmd()
476 pdev->hw_info.shmem_base + OFFSETOF(shmem_region_t, drv_fw_mb.fw_mb), in lm_submit_fw_cmd()
478 if((val & FW_MSG_ACK) != (pdev->vars.fw_wr_seq & DRV_MSG_SEQ)) in lm_submit_fw_cmd()
480 DbgMessage(pdev, WARN, "command pending.\n"); in lm_submit_fw_cmd()
485 pdev->vars.fw_wr_seq++; in lm_submit_fw_cmd()
487 drv_msg |= (pdev->vars.fw_wr_seq & DRV_MSG_SEQ); in lm_submit_fw_cmd()
490 pdev, in lm_submit_fw_cmd()
491 pdev->hw_info.shmem_base + in lm_submit_fw_cmd()
507 lm_device_t *pdev) in lm_last_fw_cmd_status() argument
511 if(pdev->vars.fw_timed_out) in lm_last_fw_cmd_status()
513 DbgMessage(pdev, WARN, "fw timed out.\n"); in lm_last_fw_cmd_status()
519 pdev, in lm_last_fw_cmd_status()
520 pdev->hw_info.shmem_base + in lm_last_fw_cmd_status()
523 if((val & FW_MSG_ACK) != (pdev->vars.fw_wr_seq & DRV_MSG_SEQ)) in lm_last_fw_cmd_status()
545 lm_device_t *pdev, in lm_mb_get_cid_addr() argument
550 DbgBreakIf(pdev->params.bin_mq_mode && CHIP_NUM(pdev) != CHIP_NUM_5709); in lm_mb_get_cid_addr()
552 if(cid < 256 || pdev->params.bin_mq_mode == FALSE) in lm_mb_get_cid_addr()
558 DbgBreakIf(cid < pdev->hw_info.first_l4_l5_bin); in lm_mb_get_cid_addr()
561 ((((cid - pdev->hw_info.first_l4_l5_bin) / in lm_mb_get_cid_addr()
562 pdev->hw_info.bin_size) + 256) << MB_KERNEL_CTX_SHIFT); in lm_mb_get_cid_addr()
565 DbgBreakIf(mq_offset > pdev->hw_info.bar_size); in lm_mb_get_cid_addr()
579 lm_device_t *pdev, in lm_mb_get_bypass_addr() argument
584 DbgBreakIf(pdev->params.bin_mq_mode && CHIP_NUM(pdev) != CHIP_NUM_5709); in lm_mb_get_bypass_addr()
586 if(cid < 256 || pdev->params.bin_mq_mode == FALSE) in lm_mb_get_bypass_addr()
594 DbgBreakIf(cid < pdev->hw_info.first_l4_l5_bin); in lm_mb_get_bypass_addr()
598 (((cid - pdev->hw_info.first_l4_l5_bin) / in lm_mb_get_bypass_addr()
599 pdev->hw_info.bin_size) + 256) * LM_PAGE_SIZE; in lm_mb_get_bypass_addr()
602 DbgBreakIf(mq_offset > pdev->hw_info.bar_size); in lm_mb_get_bypass_addr()