Lines Matching refs:outb
120 outb(src & 0xff, eth_asic_base + WD_GP2);
121 outb(src >> 8, eth_asic_base + WD_GP2);
123 outb(D8390_COMMAND_RD2 |
125 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
126 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
127 outb(src, eth_nic_base + D8390_P0_RSAR0);
128 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
129 outb(D8390_COMMAND_RD0 |
133 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
134 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
135 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
157 outb(t503_output, eth_asic_base + _3COM_CR);
170 outb(dst & 0xff, eth_asic_base + WD_GP2); in eth_pio_write()
171 outb(dst >> 8, eth_asic_base + WD_GP2); in eth_pio_write()
173 outb(D8390_COMMAND_RD2 | in eth_pio_write()
175 outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); in eth_pio_write()
176 outb(cnt, eth_nic_base + D8390_P0_RBCR0); in eth_pio_write()
177 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1); in eth_pio_write()
178 outb(dst, eth_nic_base + D8390_P0_RSAR0); in eth_pio_write()
179 outb(dst>>8, eth_nic_base + D8390_P0_RSAR1); in eth_pio_write()
180 outb(D8390_COMMAND_RD1 | in eth_pio_write()
184 outb(dst & 0xff, eth_asic_base + _3COM_DALSB); in eth_pio_write()
185 outb(dst >> 8, eth_asic_base + _3COM_DAMSB); in eth_pio_write()
187 outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR); in eth_pio_write()
206 outb(*(src++), eth_asic_base + ASIC_PIO); in eth_pio_write()
210 outb(t503_output, eth_asic_base + _3COM_CR); in eth_pio_write()
243 outb(4, eth_nic_base+D8390_P0_RCR); in enable_multicast()
244 outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND); in enable_multicast()
247 outb(mcfilter[i], eth_nic_base + 8 + i); in enable_multicast()
251 outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND); in enable_multicast()
252 outb(4 | 0x08, eth_nic_base+D8390_P0_RCR); in enable_multicast()
265 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); in ns8390_reset()
268 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | in ns8390_reset()
271 outb(0x49, eth_nic_base+D8390_P0_DCR); in ns8390_reset()
273 outb(0x48, eth_nic_base+D8390_P0_DCR); in ns8390_reset()
274 outb(0, eth_nic_base+D8390_P0_RBCR0); in ns8390_reset()
275 outb(0, eth_nic_base+D8390_P0_RBCR1); in ns8390_reset()
276 outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */ in ns8390_reset()
277 outb(2, eth_nic_base+D8390_P0_TCR); in ns8390_reset()
278 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR); in ns8390_reset()
279 outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART); in ns8390_reset()
283 outb(0x10, eth_asic_base + 0x06); /* disable interrupts, enable PIO */ in ns8390_reset()
284 outb(0x01, eth_nic_base + 0x09); /* enable ring read auto-wrap */ in ns8390_reset()
286 outb(0, eth_nic_base + 0x09); in ns8390_reset()
290 outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP); in ns8390_reset()
291 outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND); in ns8390_reset()
292 outb(0xFF, eth_nic_base+D8390_P0_ISR); in ns8390_reset()
293 outb(0, eth_nic_base+D8390_P0_IMR); in ns8390_reset()
296 outb(D8390_COMMAND_PS1 | in ns8390_reset()
300 outb(D8390_COMMAND_PS1 | in ns8390_reset()
303 outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i); in ns8390_reset()
305 outb(0xFF, eth_nic_base+D8390_P1_MAR0+i); in ns8390_reset()
306 outb(eth_rx_start, eth_nic_base+D8390_P1_CURR); in ns8390_reset()
309 outb(D8390_COMMAND_PS0 | in ns8390_reset()
313 outb(D8390_COMMAND_PS0 | in ns8390_reset()
315 outb(0xFF, eth_nic_base+D8390_P0_ISR); in ns8390_reset()
316 outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */ in ns8390_reset()
317 outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */ in ns8390_reset()
329 outb(t503_output, eth_asic_base + _3COM_CR); in ns8390_reset()
345 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND); in eth_rx_overrun()
348 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | in eth_rx_overrun()
356 outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */ in eth_rx_overrun()
357 outb(0, eth_nic_base+D8390_P0_RBCR1); in eth_rx_overrun()
365 outb(2, eth_nic_base+D8390_P0_TCR); in eth_rx_overrun()
368 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND); in eth_rx_overrun()
371 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | in eth_rx_overrun()
379 outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR); in eth_rx_overrun()
382 outb(0, eth_nic_base+D8390_P0_TCR); in eth_rx_overrun()
413 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR); in ns8390_transmit()
419 outb(WD_MSR_MENB, eth_asic_base + WD_MSR); in ns8390_transmit()
431 outb(0, eth_asic_base + WD_MSR); in ns8390_transmit()
461 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR); in ns8390_transmit()
465 outb(D8390_COMMAND_PS0 | in ns8390_transmit()
469 outb(D8390_COMMAND_PS0 | in ns8390_transmit()
471 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR); in ns8390_transmit()
472 outb(s, eth_nic_base+D8390_P0_TBCR0); in ns8390_transmit()
473 outb(s>>8, eth_nic_base+D8390_P0_TBCR1); in ns8390_transmit()
476 outb(D8390_COMMAND_PS0 | in ns8390_transmit()
480 outb(D8390_COMMAND_PS0 | in ns8390_transmit()
508 outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND); in ns8390_poll()
510 outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND); in ns8390_poll()
518 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR); in ns8390_poll()
523 outb(WD_MSR_MENB, eth_asic_base + WD_MSR); in ns8390_poll()
566 outb(0, eth_asic_base + WD_MSR); in ns8390_poll()
571 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR); in ns8390_poll()
579 outb(next-1, eth_nic_base+D8390_P0_BOUND); in ns8390_poll()
684 outb(0x80, eth_asic_base + WD_MSR); /* Reset */ in eth_probe()
694 outb(0, eth_asic_base+WD_MSR); in eth_probe()
697 outb(WD_MSR_MENB, eth_asic_base+WD_MSR); in eth_probe()
698 outb((inb(eth_asic_base+0x04) | in eth_probe()
700 outb(((unsigned)(eth_bmem >> 13) & 0x0F) | in eth_probe()
703 outb((inb(eth_asic_base+0x04) & in eth_probe()
708 outb(((unsigned)(eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR); in eth_probe()
713 outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR); in eth_probe()
715 outb((eth_laar = in eth_probe()
812 outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR ); in eth_probe()
813 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR ); in eth_probe()
817 outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR); in eth_probe()
829 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR); in eth_probe()
834 outb(_3COM_GACFR_RSEL | in eth_probe()
837 outb(0xff, eth_asic_base + _3COM_VPTR2); in eth_probe()
838 outb(0xff, eth_asic_base + _3COM_VPTR1); in eth_probe()
839 outb(0x00, eth_asic_base + _3COM_VPTR0); in eth_probe()
855 outb(eth_tx_start, eth_asic_base + _3COM_PSTR); in eth_probe()
856 outb(eth_memsize, eth_asic_base + _3COM_PSPR); in eth_probe()
885 outb(c, eth_asic_base + NE_RESET); in eth_probe()
887 outb(D8390_COMMAND_STP | in eth_probe()
889 outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); in eth_probe()
890 outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); in eth_probe()
891 outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); in eth_probe()
892 outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); in eth_probe()
905 outb(D8390_DCR_WTS | in eth_probe()
907 outb(MEM_16384, eth_nic_base + D8390_P0_PSTART); in eth_probe()
908 outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP); in eth_probe()