Lines Matching refs:base
343 static inline void pci_push(u8 * base) in pci_push() argument
346 readl(base); in pci_push()
351 u8 *base = (u8 *) BASE; in reg_delay() local
353 pci_push(base); in reg_delay()
362 } while ((readl(base + offset) & mask) != target); in reg_delay()
395 u8 *base = (u8 *) BASE; in mii_rw() local
400 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); in mii_rw()
402 reg = readl(base + NvRegAdapterControl); in mii_rw()
406 base + NvRegAdapterControl); in mii_rw()
408 reg = readl(base + NvRegMIIControl); in mii_rw()
410 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); in mii_rw()
417 writel(value, base + NvRegMIIData); in mii_rw()
420 writel(reg, base + NvRegMIIControl); in mii_rw()
432 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { in mii_rw()
439 retval = readl(base + NvRegMIIData); in mii_rw()
444 reg = readl(base + NvRegAdapterControl); in mii_rw()
446 base + NvRegAdapterControl); in mii_rw()
453 u8 *base = (u8 *) BASE; in start_rx() local
457 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { in start_rx()
458 writel(0, base + NvRegReceiverControl); in start_rx()
459 pci_push(base); in start_rx()
461 writel(np->linkspeed, base + NvRegLinkSpeed); in start_rx()
462 pci_push(base); in start_rx()
463 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); in start_rx()
464 pci_push(base); in start_rx()
469 u8 *base = (u8 *) BASE; in stop_rx() local
472 writel(0, base + NvRegReceiverControl); in stop_rx()
478 writel(0, base + NvRegLinkSpeed); in stop_rx()
483 u8 *base = (u8 *) BASE; in start_tx() local
486 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); in start_tx()
487 pci_push(base); in start_tx()
492 u8 *base = (u8 *) BASE; in stop_tx() local
495 writel(0, base + NvRegTransmitterControl); in stop_tx()
501 writel(0, base + NvRegUnknownTransmitterReg); in stop_tx()
507 u8 *base = (u8 *) BASE; in txrx_reset() local
511 base + NvRegTxRxControl); in txrx_reset()
512 pci_push(base); in txrx_reset()
514 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl); in txrx_reset()
515 pci_push(base); in txrx_reset()
603 u8 *base = (u8 *) BASE; in set_multicast() local
625 writel(addr[0], base + NvRegMulticastAddrA); in set_multicast()
626 writel(addr[1], base + NvRegMulticastAddrB); in set_multicast()
627 writel(mask[0], base + NvRegMulticastMaskA); in set_multicast()
628 writel(mask[1], base + NvRegMulticastMaskB); in set_multicast()
629 writel(pff, base + NvRegPacketFilterFlags); in set_multicast()
638 u8 *base = (u8 *) BASE; in forcedeth_reset() local
645 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); in forcedeth_reset()
646 writel(0, base + NvRegMulticastAddrB); in forcedeth_reset()
647 writel(0, base + NvRegMulticastMaskA); in forcedeth_reset()
648 writel(0, base + NvRegMulticastMaskB); in forcedeth_reset()
649 writel(0, base + NvRegPacketFilterFlags); in forcedeth_reset()
650 writel(0, base + NvRegAdapterControl); in forcedeth_reset()
651 writel(0, base + NvRegLinkSpeed); in forcedeth_reset()
652 writel(0, base + NvRegUnknownTransmitterReg); in forcedeth_reset()
654 writel(0, base + NvRegUnknownSetupReg6); in forcedeth_reset()
670 writel(mac[0], base + NvRegMacAddrA); in forcedeth_reset()
671 writel(mac[1], base + NvRegMacAddrB); in forcedeth_reset()
677 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); in forcedeth_reset()
678 writel(0, base + NvRegTxRxControl); in forcedeth_reset()
679 pci_push(base); in forcedeth_reset()
680 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl); in forcedeth_reset()
686 writel(0, base + NvRegUnknownSetupReg4); in forcedeth_reset()
689 writel(NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, base + NvRegMIISpeed); in forcedeth_reset()
718 base + NvRegMisc1); in forcedeth_reset()
719 writel(readl(base + NvRegTransmitterStatus), in forcedeth_reset()
720 base + NvRegTransmitterStatus); in forcedeth_reset()
721 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); in forcedeth_reset()
722 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig); in forcedeth_reset()
724 writel(readl(base + NvRegReceiverStatus), in forcedeth_reset()
725 base + NvRegReceiverStatus); in forcedeth_reset()
730 base + NvRegRandomSeed); in forcedeth_reset()
731 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); in forcedeth_reset()
732 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); in forcedeth_reset()
733 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval); in forcedeth_reset()
734 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); in forcedeth_reset()
737 NVREG_ADAPTCTL_PHYVALID, base + NvRegAdapterControl); in forcedeth_reset()
738 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); in forcedeth_reset()
739 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); in forcedeth_reset()
743 base + NvRegRxRingPhysAddr); in forcedeth_reset()
745 base + NvRegTxRingPhysAddr); in forcedeth_reset()
750 base + NvRegRingSizes); in forcedeth_reset()
752 i = readl(base + NvRegPowerState); in forcedeth_reset()
755 base + NvRegPowerState); in forcedeth_reset()
757 pci_push(base); in forcedeth_reset()
759 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, in forcedeth_reset()
760 base + NvRegPowerState); in forcedeth_reset()
761 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); in forcedeth_reset()
763 writel(0, base + NvRegIrqMask); in forcedeth_reset()
764 pci_push(base); in forcedeth_reset()
765 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in forcedeth_reset()
766 pci_push(base); in forcedeth_reset()
767 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); in forcedeth_reset()
768 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); in forcedeth_reset()
769 pci_push(base); in forcedeth_reset()
773 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); in forcedeth_reset()
774 writel(0, base + NvRegMulticastAddrB); in forcedeth_reset()
775 writel(0, base + NvRegMulticastMaskA); in forcedeth_reset()
776 writel(0, base + NvRegMulticastMaskB); in forcedeth_reset()
778 base + NvRegPacketFilterFlags); in forcedeth_reset()
845 u8 *base = (u8 *) BASE; in forcedeth_transmit() local
869 writel(NVREG_TXRXCTL_KICK, base + NvRegTxRxControl); in forcedeth_transmit()
870 pci_push(base); in forcedeth_transmit()
890 u8 *base = (u8 *) BASE; in forcedeth_disable() local
896 writel(0, base + NvRegIrqMask); in forcedeth_disable()
897 pci_push(base); in forcedeth_disable()
903 writel(np->orig_mac[0], base + NvRegMacAddrA); in forcedeth_disable()
904 writel(np->orig_mac[1], base + NvRegMacAddrB); in forcedeth_disable()
933 u8 *base; in forcedeth_probe() local
960 base = (u8 *) BASE; in forcedeth_probe()
961 np->orig_mac[0] = readl(base + NvRegMacAddrA); in forcedeth_probe()
962 np->orig_mac[1] = readl(base + NvRegMacAddrB); in forcedeth_probe()