16461 Introduce sequence to clear Branch History Buffer (BHB)
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <

16461 Introduce sequence to clear Branch History Buffer (BHB)
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <Gordon.W.Ross@gmail.com>

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16407 Raphael DF revision detection is incorrect
16405 initial amdzen family 1ah and cpuid support
16406 zen topo should tolerate missing revision or ppin info
Reviewed by: Andy Fiddaman

16407 Raphael DF revision detection is incorrect
16405 initial amdzen family 1ah and cpuid support
16406 zen topo should tolerate missing revision or ppin info
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Luqman Aden <luqman@oxide.computer>
Approved by: Richard Lowe <richlowe@richlowe.net>

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16413 Post-barrier Return Stack Buffer (PBRSB) fixes can be detected in HW
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by:

16413 Post-barrier Return Stack Buffer (PBRSB) fixes can be detected in HW
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by: Gordon Ross <Gordon.W.Ross@gmail.com>

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16397 Re-enable VERW-using x86_md_clear() function on RFDS-afflicted Intel CPUs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Appr

16397 Re-enable VERW-using x86_md_clear() function on RFDS-afflicted Intel CPUs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Bill Sommerfeld <sommerfeld@hamachi.org>
Approved by: Richard Lowe <richlowe@richlowe.net>

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16139 unix: we should recognize qemu
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Reviewed by: Igor Kozhukhov <igor@dilos.org>
Reviewed by: Garrett D'Amore <garrett@damore.org>

16139 unix: we should recognize qemu
Reviewed by: Gordon Ross <gordon.w.ross@gmail.com>
Reviewed by: Igor Kozhukhov <igor@dilos.org>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Approved by: Robert Mustacchi <rm@fingolfin.org>

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16170 Flesh out AMD Zen4 microarchitecture (core) revisions.
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@mnx.io>

15951 want Zen specific CPU topology mapping
15952 want way of exposing AMD SoC topology to userland
15953 /dev/fm should support cache information
15954 snapshot new AMD CPUID topology l

15951 want Zen specific CPU topology mapping
15952 want way of exposing AMD SoC topology to userland
15953 /dev/fm should support cache information
15954 snapshot new AMD CPUID topology leaves
15955 want more convenient topo module API for setting properties
Reviewed by: Keith Wesolowski <wesolows@oxide.computer>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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15923 Add support for SP6 Socket Types
15924 Improve AMD Socket Management
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Marco van Wieringen <marco.van.wieringen@planets.

15923 Add support for SP6 Socket Types
15924 Improve AMD Socket Management
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Reviewed by: Marco van Wieringen <marco.van.wieringen@planets.elm.net>
Reviewed by: Keith M Wesolowski <wesolows@oxide.computer>
Approved by: Dan McDonald <danmcd@mnx.io>

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15846 Restructure CPU microcode update
15475 ucodeadm -l could be more ergonomic
15847 Remove vestigial bootadm support for microcode extraction
15848 Remove support for Xen DOM0 CPU micr

15846 Restructure CPU microcode update
15475 ucodeadm -l could be more ergonomic
15847 Remove vestigial bootadm support for microcode extraction
15848 Remove support for Xen DOM0 CPU microcode updates
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@mnx.io>

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15676 SVM feature detection broken in bhyve
15677 SVM should not blindly enable LBR-virt
15678 SVM should expose LBR MSRs
15693 vmm-data should allow specific MSR reads
Reviewed by: J

15676 SVM feature detection broken in bhyve
15677 SVM should not blindly enable LBR-virt
15678 SVM should expose LBR MSRs
15693 vmm-data should allow specific MSR reads
Reviewed by: Jordan Paige Hendricks <jordan@oxide.computer>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Dan McDonald <danmcd@mnx.io>

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15254 %ymm registers not restored after signal handler
15367 x86 getfpregs() summons corrupting %xmm ghosts
15333 want x86 /proc xregs support (libc_db, libproc, mdb, etc.)
15336 want lib

15254 %ymm registers not restored after signal handler
15367 x86 getfpregs() summons corrupting %xmm ghosts
15333 want x86 /proc xregs support (libc_db, libproc, mdb, etc.)
15336 want libc functions for extended ucontext_t
15334 want ps_lwphandle-specific reg routines
15328 FPU_CW_INIT mistreats reserved bit
15335 i86pc fpu_subr.c isn't really platform-specific
15332 setcontext(2) isn't actually noreturn
15331 need <sys/stdalign.h>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Rich Lowe <richlowe@richlowe.net>
Approved by: Joshua M. Clulow <josh@sysmgr.org>

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15521 Use Automatic IBRS when available
Reviewed by: Dan McDonald <danmcd@mnx.io>
Approved by: Richard Lowe <richlowe@richlowe.net>

15518 Update various AMD CPU revision and socket data
15519 Phoenix and Bergamo amdzen, zen_umc support
Reviewed by: Dan McDonald <danmcd@mnx.io>
Approved by: Patrick Mooney <pmooney@pfmo

15518 Update various AMD CPU revision and socket data
15519 Phoenix and Bergamo amdzen, zen_umc support
Reviewed by: Dan McDonald <danmcd@mnx.io>
Approved by: Patrick Mooney <pmooney@pfmooney.com>

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14821 Add additional AVX512 capabilities
14822 Need new word of hardware capabilities
14823 aux vector feature mapping should use x86_featureset
Reviewed by: Richard Lowe <richlowe@richlo

14821 Add additional AVX512 capabilities
14822 Need new word of hardware capabilities
14823 aux vector feature mapping should use x86_featureset
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Approved by: Dan McDonald <danmcd@mnx.io>

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14836 extend AMD chiprev mechanism to identify core revs
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Joshua M. Clulow <josh@sysmgr.org>

14834 cpuid code is and has always been isadep
14835 split cpuid pass1
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by:

14834 cpuid code is and has always been isadep
14835 split cpuid pass1
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Andy Fiddaman <illumos@fiddaman.net>
Approved by: Garrett D'Amore <garrett@damore.org>

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14838 Rename erratum 147 handling
14839 Untangle erratum 147 from lockstat
14840 Modernize lockstat probes
14865 mutex_tryenter:adaptive-acquire probe never fires
Reviewed by: Toomas

14838 Rename erratum 147 handling
14839 Untangle erratum 147 from lockstat
14840 Modernize lockstat probes
14865 mutex_tryenter:adaptive-acquire probe never fires
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: Dan McDonald <danmcd@mnx.io>
Reviewed by: Gerg&#337; Mih&#225;ly Doma <domag02@gmail.com>
Approved by: Robert Mustacchi <rm@fingolfin.org>

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14727 Want AMD Unified Memory Controller Driver
Reviewed by: Keith M Wesolowski <wesolows@oxide.computer>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: C Fraire <cfraire@

14727 Want AMD Unified Memory Controller Driver
Reviewed by: Keith M Wesolowski <wesolows@oxide.computer>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: C Fraire <cfraire@me.com>
Approved by: Garrett D'Amore <garrett@damore.org>

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13896 bhyve VM interfaces should be better fit
13981 bhyve emulation should set dirty bits
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Joshua M. Clulow <josh@sysmgr.org>

13896 bhyve VM interfaces should be better fit
13981 bhyve emulation should set dirty bits
Reviewed by: Dan Cross <cross@oxidecomputer.com>
Reviewed by: Joshua M. Clulow <josh@sysmgr.org>
Approved by: Dan McDonald <danmcd@joyent.com>

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13939 it's time the 32bit intel kernel was (x)86'd
Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Approved by: Garret D'Am

13939 it's time the 32bit intel kernel was (x)86'd
Reviewed by: Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Approved by: Garret D'Amore <garrett@damore.org>

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14013 Update Zen 3 cpuid_subr.c info
Reviewed by: Andy Fiddaman <andy@omnios.org>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Richard Lowe <richlowe@richlowe.net>

13704 add Ice Lake Xeon to PPIN list
13705 add recent Intel models to x86_archext.h
Reviewed by: Andrew Stormont <andyjstormont@gmail.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Ap

13704 add Ice Lake Xeon to PPIN list
13705 add recent Intel models to x86_archext.h
Reviewed by: Andrew Stormont <andyjstormont@gmail.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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13383 generalize check for serializing LFENCE
13384 tsc_read() should use lfence when prudent
13387 bhyve should expose lfence serialize in DE_CFG MSR
Reviewed by: Robert Mustacchi <rm@fi

13383 generalize check for serializing LFENCE
13384 tsc_read() should use lfence when prudent
13387 bhyve should expose lfence serialize in DE_CFG MSR
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@joyent.com>

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13440 ppin disablement path missing state transition
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Patrick Mooney <pmooney@p

13440 ppin disablement path missing state transition
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Patrick Mooney <pmooney@pfmooney.com>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

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13339 Add support for Hygon Dhyana Family 18h processor
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@joyent.com>