px_lib4v.h (0114761d) px_lib4v.h (b1593d50)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#ifndef _SYS_PX_LIB4V_H
27#define _SYS_PX_LIB4V_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/*
34 * Fasttrap numbers for VPCI hypervisor functions.
35 */
36
37#define HVIO_IOMMU_MAP 0xb0
38#define HVIO_IOMMU_DEMAP 0xb1
39#define HVIO_IOMMU_GETMAP 0xb2
40#define HVIO_IOMMU_GETBYPASS 0xb3
41
42#define HVIO_CONFIG_GET 0xb4
43#define HVIO_CONFIG_PUT 0xb5
44
45#define HVIO_PEEK 0xb6
46#define HVIO_POKE 0xb7
47
48#define HVIO_DMA_SYNC 0xb8
49
50#define HVIO_MSIQ_CONF 0xc0
51#define HVIO_MSIQ_INFO 0xc1
52#define HVIO_MSIQ_GETVALID 0xc2
53#define HVIO_MSIQ_SETVALID 0xc3
54#define HVIO_MSIQ_GETSTATE 0xc4
55#define HVIO_MSIQ_SETSTATE 0xc5
56#define HVIO_MSIQ_GETHEAD 0xc6
57#define HVIO_MSIQ_SETHEAD 0xc7
58#define HVIO_MSIQ_GETTAIL 0xc8
59
60#define HVIO_MSI_GETVALID 0xc9
61#define HVIO_MSI_SETVALID 0xca
62#define HVIO_MSI_GETMSIQ 0xcb
63#define HVIO_MSI_SETMSIQ 0xcc
64#define HVIO_MSI_GETSTATE 0xcd
65#define HVIO_MSI_SETSTATE 0xce
66
67#define HVIO_MSG_GETMSIQ 0xd0
68#define HVIO_MSG_SETMSIQ 0xd1
69#define HVIO_MSG_GETVALID 0xd2
70#define HVIO_MSG_SETVALID 0xd3
71
72#ifndef _ASM
73
74/*
75 * The device handle uniquely identifies a SUN4V device.
76 * It consists of the lower 28-bits of the hi-cell of the
77 * first entry of the SUN4V device's "reg" property as
78 * defined by the SUN4V Bus Binding to Open Firmware.
79 */
80#define DEVHDLE_MASK 0xFFFFFFF
81
82/* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */
83#define PX_RA_BDF_SHIFT 8
84
85#define PX_ADDR2PFN(addr, index, flags, i) \
86 ((flags & MMU_MAP_PFN) ? \
87 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \
88 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i))))
89
90/*
91 * VPCI API versioning.
92 *
93 * Currently PX nexus driver supports VPCI API version 1.1
94 */
95#define PX_VPCI_MAJOR_VER_1 0x1ull
96#define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1
97
98#define PX_VPCI_MINOR_VER_0 0x0ull
99#define PX_VPCI_MINOR_VER_1 0x1ull
23 * Use is subject to license terms.
24 */
25
26#ifndef _SYS_PX_LIB4V_H
27#define _SYS_PX_LIB4V_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/*
34 * Fasttrap numbers for VPCI hypervisor functions.
35 */
36
37#define HVIO_IOMMU_MAP 0xb0
38#define HVIO_IOMMU_DEMAP 0xb1
39#define HVIO_IOMMU_GETMAP 0xb2
40#define HVIO_IOMMU_GETBYPASS 0xb3
41
42#define HVIO_CONFIG_GET 0xb4
43#define HVIO_CONFIG_PUT 0xb5
44
45#define HVIO_PEEK 0xb6
46#define HVIO_POKE 0xb7
47
48#define HVIO_DMA_SYNC 0xb8
49
50#define HVIO_MSIQ_CONF 0xc0
51#define HVIO_MSIQ_INFO 0xc1
52#define HVIO_MSIQ_GETVALID 0xc2
53#define HVIO_MSIQ_SETVALID 0xc3
54#define HVIO_MSIQ_GETSTATE 0xc4
55#define HVIO_MSIQ_SETSTATE 0xc5
56#define HVIO_MSIQ_GETHEAD 0xc6
57#define HVIO_MSIQ_SETHEAD 0xc7
58#define HVIO_MSIQ_GETTAIL 0xc8
59
60#define HVIO_MSI_GETVALID 0xc9
61#define HVIO_MSI_SETVALID 0xca
62#define HVIO_MSI_GETMSIQ 0xcb
63#define HVIO_MSI_SETMSIQ 0xcc
64#define HVIO_MSI_GETSTATE 0xcd
65#define HVIO_MSI_SETSTATE 0xce
66
67#define HVIO_MSG_GETMSIQ 0xd0
68#define HVIO_MSG_SETMSIQ 0xd1
69#define HVIO_MSG_GETVALID 0xd2
70#define HVIO_MSG_SETVALID 0xd3
71
72#ifndef _ASM
73
74/*
75 * The device handle uniquely identifies a SUN4V device.
76 * It consists of the lower 28-bits of the hi-cell of the
77 * first entry of the SUN4V device's "reg" property as
78 * defined by the SUN4V Bus Binding to Open Firmware.
79 */
80#define DEVHDLE_MASK 0xFFFFFFF
81
82/* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */
83#define PX_RA_BDF_SHIFT 8
84
85#define PX_ADDR2PFN(addr, index, flags, i) \
86 ((flags & MMU_MAP_PFN) ? \
87 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \
88 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i))))
89
90/*
91 * VPCI API versioning.
92 *
93 * Currently PX nexus driver supports VPCI API version 1.1
94 */
95#define PX_VPCI_MAJOR_VER_1 0x1ull
96#define PX_VPCI_MAJOR_VER PX_VPCI_MAJOR_VER_1
97
98#define PX_VPCI_MINOR_VER_0 0x0ull
99#define PX_VPCI_MINOR_VER_1 0x1ull
100#define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_1
100#define PX_VPCI_MINOR_VER_2 0x2ull
101#define PX_VPCI_MINOR_VER PX_VPCI_MINOR_VER_2
101
102extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf,
103 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p);
104extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf,
105 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data);
106
107extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
108 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p,
109 pages_t *pages_mapped);
110extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
111 pages_t pages, pages_t *pages_demapped);
112extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
113 io_attributes_t *attr_p, r_addr_t *r_addr_p);
114extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
115 io_attributes_t attr, io_addr_t *io_addr_p);
116extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
117 size_t num_bytes, io_sync_direction_t io_sync_direction,
118 size_t *bytes_synched);
119
120/*
121 * MSIQ Functions:
122 */
123extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
124 r_addr_t ra, uint_t msiq_rec_cnt);
125extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
126 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p);
127extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
128 pci_msiq_valid_state_t *msiq_valid_state);
129extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
130 pci_msiq_valid_state_t msiq_valid_state);
131extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
132 pci_msiq_state_t *msiq_state);
133extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
134 pci_msiq_state_t msiq_state);
135extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
136 msiqhead_t *msiq_head);
137extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
138 msiqhead_t msiq_head);
139extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
140 msiqtail_t *msiq_tail);
141
142/*
143 * MSI Functions:
144 */
145extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
146 msiqid_t *msiq_id);
147extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
148 msiqid_t msiq_id, msi_type_t msitype);
149extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
150 pci_msi_valid_state_t *msi_valid_state);
151extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
152 pci_msi_valid_state_t msi_valid_state);
153extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
154 pci_msi_state_t *msi_state);
155extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
156 pci_msi_state_t msi_state);
157
158/*
159 * MSG Functions:
160 */
161extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
162 msiqid_t *msiq_id);
163extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
164 msiqid_t msiq_id);
165extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
166 pcie_msg_valid_state_t *msg_valid_state);
167extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
168 pcie_msg_valid_state_t msg_valid_state);
169
170typedef struct px_config_acc_pvt {
171 dev_info_t *dip;
172 uint32_t raddr;
173 uint32_t vaddr;
174} px_config_acc_pvt_t;
175
176/*
177 * Peek/poke functionality:
178 */
179
180extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size,
181 uint32_t *status, uint64_t *data_p);
182extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size,
183 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat);
184extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf,
185 int32_t *mps_cap);
186extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf,
187 int32_t mps);
188
189/*
190 * Priviledged physical access:
191 */
192extern uint64_t hv_ra2pa(uint64_t ra);
193extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2,
194 uint64_t arg3);
195extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr);
196
197#endif /* _ASM */
198
199#ifdef __cplusplus
200}
201#endif
202
203#endif /* _SYS_PX_LIB4V_H */
102
103extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf,
104 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p);
105extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf,
106 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data);
107
108extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
109 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p,
110 pages_t *pages_mapped);
111extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
112 pages_t pages, pages_t *pages_demapped);
113extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
114 io_attributes_t *attr_p, r_addr_t *r_addr_p);
115extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
116 io_attributes_t attr, io_addr_t *io_addr_p);
117extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
118 size_t num_bytes, io_sync_direction_t io_sync_direction,
119 size_t *bytes_synched);
120
121/*
122 * MSIQ Functions:
123 */
124extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
125 r_addr_t ra, uint_t msiq_rec_cnt);
126extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
127 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p);
128extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
129 pci_msiq_valid_state_t *msiq_valid_state);
130extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
131 pci_msiq_valid_state_t msiq_valid_state);
132extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
133 pci_msiq_state_t *msiq_state);
134extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
135 pci_msiq_state_t msiq_state);
136extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
137 msiqhead_t *msiq_head);
138extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
139 msiqhead_t msiq_head);
140extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
141 msiqtail_t *msiq_tail);
142
143/*
144 * MSI Functions:
145 */
146extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
147 msiqid_t *msiq_id);
148extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
149 msiqid_t msiq_id, msi_type_t msitype);
150extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
151 pci_msi_valid_state_t *msi_valid_state);
152extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
153 pci_msi_valid_state_t msi_valid_state);
154extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
155 pci_msi_state_t *msi_state);
156extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
157 pci_msi_state_t msi_state);
158
159/*
160 * MSG Functions:
161 */
162extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
163 msiqid_t *msiq_id);
164extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
165 msiqid_t msiq_id);
166extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
167 pcie_msg_valid_state_t *msg_valid_state);
168extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
169 pcie_msg_valid_state_t msg_valid_state);
170
171typedef struct px_config_acc_pvt {
172 dev_info_t *dip;
173 uint32_t raddr;
174 uint32_t vaddr;
175} px_config_acc_pvt_t;
176
177/*
178 * Peek/poke functionality:
179 */
180
181extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size,
182 uint32_t *status, uint64_t *data_p);
183extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size,
184 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat);
185extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf,
186 int32_t *mps_cap);
187extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf,
188 int32_t mps);
189
190/*
191 * Priviledged physical access:
192 */
193extern uint64_t hv_ra2pa(uint64_t ra);
194extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2,
195 uint64_t arg3);
196extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr);
197
198#endif /* _ASM */
199
200#ifdef __cplusplus
201}
202#endif
203
204#endif /* _SYS_PX_LIB4V_H */