101 102extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 103 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 104extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 105 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 106 107extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 108 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 109 pages_t *pages_mapped); 110extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 111 pages_t pages, pages_t *pages_demapped); 112extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 113 io_attributes_t *attr_p, r_addr_t *r_addr_p); 114extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 115 io_attributes_t attr, io_addr_t *io_addr_p); 116extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 117 size_t num_bytes, io_sync_direction_t io_sync_direction, 118 size_t *bytes_synched); 119 120/* 121 * MSIQ Functions: 122 */ 123extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 124 r_addr_t ra, uint_t msiq_rec_cnt); 125extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 126 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 127extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 128 pci_msiq_valid_state_t *msiq_valid_state); 129extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 130 pci_msiq_valid_state_t msiq_valid_state); 131extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 132 pci_msiq_state_t *msiq_state); 133extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 134 pci_msiq_state_t msiq_state); 135extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 136 msiqhead_t *msiq_head); 137extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 138 msiqhead_t msiq_head); 139extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 140 msiqtail_t *msiq_tail); 141 142/* 143 * MSI Functions: 144 */ 145extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 146 msiqid_t *msiq_id); 147extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 148 msiqid_t msiq_id, msi_type_t msitype); 149extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 150 pci_msi_valid_state_t *msi_valid_state); 151extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 152 pci_msi_valid_state_t msi_valid_state); 153extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 154 pci_msi_state_t *msi_state); 155extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 156 pci_msi_state_t msi_state); 157 158/* 159 * MSG Functions: 160 */ 161extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 162 msiqid_t *msiq_id); 163extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 164 msiqid_t msiq_id); 165extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 166 pcie_msg_valid_state_t *msg_valid_state); 167extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 168 pcie_msg_valid_state_t msg_valid_state); 169 170typedef struct px_config_acc_pvt { 171 dev_info_t *dip; 172 uint32_t raddr; 173 uint32_t vaddr; 174} px_config_acc_pvt_t; 175 176/* 177 * Peek/poke functionality: 178 */ 179 180extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 181 uint32_t *status, uint64_t *data_p); 182extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 183 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 184extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, 185 int32_t *mps_cap); 186extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, 187 int32_t mps); 188 189/* 190 * Priviledged physical access: 191 */ 192extern uint64_t hv_ra2pa(uint64_t ra); 193extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 194 uint64_t arg3); 195extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 196 197#endif /* _ASM */ 198 199#ifdef __cplusplus 200} 201#endif 202 203#endif /* _SYS_PX_LIB4V_H */
| 102 103extern uint64_t hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 104 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p); 105extern uint64_t hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 106 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data); 107 108extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 109 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 110 pages_t *pages_mapped); 111extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 112 pages_t pages, pages_t *pages_demapped); 113extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 114 io_attributes_t *attr_p, r_addr_t *r_addr_p); 115extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 116 io_attributes_t attr, io_addr_t *io_addr_p); 117extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 118 size_t num_bytes, io_sync_direction_t io_sync_direction, 119 size_t *bytes_synched); 120 121/* 122 * MSIQ Functions: 123 */ 124extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 125 r_addr_t ra, uint_t msiq_rec_cnt); 126extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 127 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 128extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 129 pci_msiq_valid_state_t *msiq_valid_state); 130extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 131 pci_msiq_valid_state_t msiq_valid_state); 132extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 133 pci_msiq_state_t *msiq_state); 134extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 135 pci_msiq_state_t msiq_state); 136extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 137 msiqhead_t *msiq_head); 138extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 139 msiqhead_t msiq_head); 140extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 141 msiqtail_t *msiq_tail); 142 143/* 144 * MSI Functions: 145 */ 146extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 147 msiqid_t *msiq_id); 148extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 149 msiqid_t msiq_id, msi_type_t msitype); 150extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 151 pci_msi_valid_state_t *msi_valid_state); 152extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 153 pci_msi_valid_state_t msi_valid_state); 154extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 155 pci_msi_state_t *msi_state); 156extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 157 pci_msi_state_t msi_state); 158 159/* 160 * MSG Functions: 161 */ 162extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 163 msiqid_t *msiq_id); 164extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 165 msiqid_t msiq_id); 166extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 167 pcie_msg_valid_state_t *msg_valid_state); 168extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 169 pcie_msg_valid_state_t msg_valid_state); 170 171typedef struct px_config_acc_pvt { 172 dev_info_t *dip; 173 uint32_t raddr; 174 uint32_t vaddr; 175} px_config_acc_pvt_t; 176 177/* 178 * Peek/poke functionality: 179 */ 180 181extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 182 uint32_t *status, uint64_t *data_p); 183extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 184 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 185extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, 186 int32_t *mps_cap); 187extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, 188 int32_t mps); 189 190/* 191 * Priviledged physical access: 192 */ 193extern uint64_t hv_ra2pa(uint64_t ra); 194extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 195 uint64_t arg3); 196extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 197 198#endif /* _ASM */ 199 200#ifdef __cplusplus 201} 202#endif 203 204#endif /* _SYS_PX_LIB4V_H */
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