| debugreg.h (b4203d75) | debugreg.h (9c3024a3) |
|---|---|
| 1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * --- 12 unchanged lines hidden (view full) --- 21 */ 22/* 23 * Copyright (c) 1999 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 27/* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 28/* All Rights Reserved */ | 1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * --- 12 unchanged lines hidden (view full) --- 21 */ 22/* 23 * Copyright (c) 1999 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 27/* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 28/* All Rights Reserved */ |
| 29/* 30 * Copyright (c) 2018, Joyent, Inc. All rights reserved. 31 */ |
|
| 29 30#ifndef _SYS_DEBUGREG_H 31#define _SYS_DEBUGREG_H 32 33#ifdef __cplusplus 34extern "C" { 35#endif 36 --- 15 unchanged lines hidden (view full) --- 52#define DR_STATUS 6 /* u.u_debugreg[DR_STATUS] */ 53#define DR_TRAP0 0x1 /* Trap from debug register #0 */ 54#define DR_TRAP1 0x2 /* Trap from debug register #1 */ 55#define DR_TRAP2 0x4 /* Trap from debug register #2 */ 56#define DR_TRAP3 0x8 /* Trap from debug register #3 */ 57#define DR_ICEALSO 0x2000 /* Flag bit reserved for in-circuit-emulator */ 58#define DR_SINGLESTEP 0x4000 /* Trap resulting from the single-step flag */ 59#define DR_TASKSWITCH 0x8000 /* Trap resulting from a task-switch */ | 32 33#ifndef _SYS_DEBUGREG_H 34#define _SYS_DEBUGREG_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 --- 15 unchanged lines hidden (view full) --- 55#define DR_STATUS 6 /* u.u_debugreg[DR_STATUS] */ 56#define DR_TRAP0 0x1 /* Trap from debug register #0 */ 57#define DR_TRAP1 0x2 /* Trap from debug register #1 */ 58#define DR_TRAP2 0x4 /* Trap from debug register #2 */ 59#define DR_TRAP3 0x8 /* Trap from debug register #3 */ 60#define DR_ICEALSO 0x2000 /* Flag bit reserved for in-circuit-emulator */ 61#define DR_SINGLESTEP 0x4000 /* Trap resulting from the single-step flag */ 62#define DR_TASKSWITCH 0x8000 /* Trap resulting from a task-switch */ |
| 63#define DR_IN_RTM 0x10000 /* Trap inside an RTM region */ |
|
| 60 61/* 62 * dr7 controls the rest of the debug registers. 63 * use shifts and masks because arrays of fields tend to get aligned. 64 * For example, 65 * dr7 & DR_LOCAL_ENABLE_MASK 66 * dr7 >> (DR_LOCAL_ENABLE_SHIFT + r# * DR_ENABLE_SIZE) & 0x1 67 * dr7 >> (DR_CONTROL_SHIFT + r# * DR_CONTROL_SIZE) & DR_RW_MASK 68 * Note that the GLOBAL bits below and always turned off by the kernel. 69 */ 70#define DR_CONTROL 7 /* u.u_debugreg[DR_CONTROL] */ 71#define DR_LOCAL_ENABLE_MASK 0x55 /* Enable all 4 regs for ldt addrs */ 72#define DR_GLOBAL_ENABLE_MASK 0xAA /* Enable all 4 regs for gdt addrs */ 73#define DR_CONTROL_RESERVED 0xFC00 /* Bits reserved by Intel */ 74#define DR_LOCAL_SLOWDOWN 0x100 /* Slow the pipeline for ldt addrs */ 75#define DR_GLOBAL_SLOWDOWN 0x200 /* Slow the pipeline for gdt addrs */ | 64 65/* 66 * dr7 controls the rest of the debug registers. 67 * use shifts and masks because arrays of fields tend to get aligned. 68 * For example, 69 * dr7 & DR_LOCAL_ENABLE_MASK 70 * dr7 >> (DR_LOCAL_ENABLE_SHIFT + r# * DR_ENABLE_SIZE) & 0x1 71 * dr7 >> (DR_CONTROL_SHIFT + r# * DR_CONTROL_SIZE) & DR_RW_MASK 72 * Note that the GLOBAL bits below and always turned off by the kernel. 73 */ 74#define DR_CONTROL 7 /* u.u_debugreg[DR_CONTROL] */ 75#define DR_LOCAL_ENABLE_MASK 0x55 /* Enable all 4 regs for ldt addrs */ 76#define DR_GLOBAL_ENABLE_MASK 0xAA /* Enable all 4 regs for gdt addrs */ 77#define DR_CONTROL_RESERVED 0xFC00 /* Bits reserved by Intel */ 78#define DR_LOCAL_SLOWDOWN 0x100 /* Slow the pipeline for ldt addrs */ 79#define DR_GLOBAL_SLOWDOWN 0x200 /* Slow the pipeline for gdt addrs */ |
| 80#define DR_RTM 0x800 /* Restricted Transactional Memory */ 81#define DR_GENERAL_DETECT 0x2000 /* General Detect Enable */ |
|
| 76 77#define DR_LOCAL_ENABLE_SHIFT 0 /* Additional shift: local enable */ 78#define DR_GLOBAL_ENABLE_SHIFT 1 /* Additional shift: global enable */ 79#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ 80 81#define DR_TRAPS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3) 82#define DR_ENABLE0 0x03 /* Local or Global enable of trap 0 */ 83#define DR_ENABLE1 0x0C /* Local or Global enable of trap 1 */ --- 6 unchanged lines hidden (view full) --- 90#define DR_RW_EXECUTE 0x0 /* Settings for the read/write mask */ 91#define DR_RW_WRITE 0x1 92#define DR_RW_IO_RW 0x2 /* I/O space on Pentium and beyond */ 93#define DR_RW_READ 0x3 94#define DR_LEN_MASK 0xC /* Two bits specify data length */ 95#define DR_LEN_1 0x0 /* Settings for data length */ 96#define DR_LEN_2 0x4 97#define DR_LEN_4 0xC | 82 83#define DR_LOCAL_ENABLE_SHIFT 0 /* Additional shift: local enable */ 84#define DR_GLOBAL_ENABLE_SHIFT 1 /* Additional shift: global enable */ 85#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */ 86 87#define DR_TRAPS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3) 88#define DR_ENABLE0 0x03 /* Local or Global enable of trap 0 */ 89#define DR_ENABLE1 0x0C /* Local or Global enable of trap 1 */ --- 6 unchanged lines hidden (view full) --- 96#define DR_RW_EXECUTE 0x0 /* Settings for the read/write mask */ 97#define DR_RW_WRITE 0x1 98#define DR_RW_IO_RW 0x2 /* I/O space on Pentium and beyond */ 99#define DR_RW_READ 0x3 100#define DR_LEN_MASK 0xC /* Two bits specify data length */ 101#define DR_LEN_1 0x0 /* Settings for data length */ 102#define DR_LEN_2 0x4 103#define DR_LEN_4 0xC |
| 104#define DR_LEN_8 0x8 |
|
| 98 99#ifdef __cplusplus 100} 101#endif 102 103#endif /* _SYS_DEBUGREG_H */ | 105 106#ifdef __cplusplus 107} 108#endif 109 110#endif /* _SYS_DEBUGREG_H */ |