emlxs_mbox.h (a9800beb) emlxs_mbox.h (8f23e9fa)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2010 Emulex. All rights reserved.
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef _EMLXS_MBOX_H
28#define _EMLXS_MBOX_H
29
30#ifdef __cplusplus
31extern "C" {

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101#define MBX_CONFIG_HBQ 0x7C /* SLI3 */
102#define MBX_LOAD_AREA 0x81
103#define MBX_RUN_BIU_DIAG64 0x84
104#define MBX_GET_DEBUG 0x86
105#define MBX_CONFIG_PORT 0x88
106#define MBX_READ_SPARM64 0x8D
107#define MBX_READ_RPI64 0x8F
108#define MBX_CONFIG_MSI 0x90
24 * Use is subject to license terms.
25 */
26
27#ifndef _EMLXS_MBOX_H
28#define _EMLXS_MBOX_H
29
30#ifdef __cplusplus
31extern "C" {

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101#define MBX_CONFIG_HBQ 0x7C /* SLI3 */
102#define MBX_LOAD_AREA 0x81
103#define MBX_RUN_BIU_DIAG64 0x84
104#define MBX_GET_DEBUG 0x86
105#define MBX_CONFIG_PORT 0x88
106#define MBX_READ_SPARM64 0x8D
107#define MBX_READ_RPI64 0x8F
108#define MBX_CONFIG_MSI 0x90
109#define MBX_REG_LOGIN64 0x93 /* SLI2/3 */
110#define MBX_REG_RPI 0x93 /* SLI4 */
111#define MBX_READ_LA64 0x95
112#define MBX_REG_VPI 0x96 /* NPIV */
113#define MBX_UNREG_VPI 0x97 /* NPIV */
109#define MBX_REG_LOGIN64 0x93 /* SLI2/3 */
110#define MBX_REG_RPI 0x93 /* SLI4 */
111#define MBX_READ_LA64 0x95 /* SLI2/3 */
112#define MBX_READ_TOPOLOGY 0x95 /* SLI4 */
113#define MBX_REG_VPI 0x96 /* NPIV */
114#define MBX_UNREG_VPI 0x97 /* NPIV */
114#define MBX_FLASH_WR_ULA 0x98
115#define MBX_SET_DEBUG 0x99
116#define MBX_SLI_CONFIG 0x9B
117#define MBX_LOAD_EXP_ROM 0x9C
118#define MBX_REQUEST_FEATURES 0x9D
119#define MBX_RESUME_RPI 0x9E
120#define MBX_REG_VFI 0x9F
121#define MBX_REG_FCFI 0xA0

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144#define MBXERR_RPI_REGISTERED 0xB
145#define MBXERR_RPI_FULL 0xC
146#define MBXERR_NO_RESOURCES 0xD
147#define MBXERR_BAD_RCV_LENGTH 0xE
148#define MBXERR_DMA_ERROR 0xF
149#define MBXERR_NOT_SUPPORTED 0x10
150#define MBXERR_UNSUPPORTED_FEATURE 0x11
151#define MBXERR_UNKNOWN_COMMAND 0x12
115#define MBX_FLASH_WR_ULA 0x98
116#define MBX_SET_DEBUG 0x99
117#define MBX_SLI_CONFIG 0x9B
118#define MBX_LOAD_EXP_ROM 0x9C
119#define MBX_REQUEST_FEATURES 0x9D
120#define MBX_RESUME_RPI 0x9E
121#define MBX_REG_VFI 0x9F
122#define MBX_REG_FCFI 0xA0

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145#define MBXERR_RPI_REGISTERED 0xB
146#define MBXERR_RPI_FULL 0xC
147#define MBXERR_NO_RESOURCES 0xD
148#define MBXERR_BAD_RCV_LENGTH 0xE
149#define MBXERR_DMA_ERROR 0xF
150#define MBXERR_NOT_SUPPORTED 0x10
151#define MBXERR_UNSUPPORTED_FEATURE 0x11
152#define MBXERR_UNKNOWN_COMMAND 0x12
153#define MBXERR_BAD_IP_BIT 0x13
154#define MBXERR_BAD_PCB_ALIGN 0x14
155#define MBXERR_BAD_HBQ_ID 0x15
156#define MBXERR_BAD_HBQ_STATE 0x16
157#define MBXERR_BAD_HBQ_MASK_NUM 0x17
158#define MBXERR_BAD_HBQ_MASK_SUBSET 0x18
159#define MBXERR_HBQ_CREATE_FAIL 0x19
160#define MBXERR_HBQ_EXISTING 0x1A
161#define MBXERR_HBQ_RSPRING_FULL 0x1B
162#define MBXERR_HBQ_DUP_MASK 0x1C
163#define MBXERR_HBQ_INVAL_GET_PTR 0x1D
164#define MBXERR_BAD_HBQ_SIZE 0x1E
165#define MBXERR_BAD_HBQ_ORDER 0x1F
166#define MBXERR_INVALID_ID 0x20
152
167
168#define MBXERR_INVALID_VFI 0x30
169
170#define MBXERR_FLASH_WRITE_FAILED 0x100
171
172#define MBXERR_INVALID_LINKSPEED 0x500
173
174#define MBXERR_BAD_REDIRECT 0x900
175#define MBXERR_RING_ALREADY_CONFIG 0x901
176
177#define MBXERR_RING_INACTIVE 0xA00
178
179#define MBXERR_RPI_INACTIVE 0xF00
180
181#define MBXERR_NO_ACTIVE_XRI 0x1100
182#define MBXERR_XRI_NOT_ACTIVE 0x1101
183
184#define MBXERR_RPI_INUSE 0x1400
185
186#define MBXERR_NO_LINK_ATTENTION 0x1500
187
188#define MBXERR_INVALID_SLI_MODE 0x8800
189#define MBXERR_INVALID_HOST_PTR 0x8801
190#define MBXERR_CANT_CFG_SLI_MODE 0x8802
191#define MBXERR_BAD_OVERLAY 0x8803
192#define MBXERR_INVALID_FEAT_REQ 0x8804
193
194#define MBXERR_CONFIG_CANT_COMPLETE 0x88FF
195
196#define MBXERR_DID_ALREADY_REGISTERED 0x9600
197#define MBXERR_DID_INCONSISTENT 0x9601
198#define MBXERR_VPI_TOO_LARGE 0x9603
199
200#define MBXERR_STILL_ASSOCIATED 0x9700
201
202#define MBXERR_INVALID_VF_STATE 0x9F00
203#define MBXERR_VFI_ALREADY_REGISTERED 0x9F02
204#define MBXERR_VFI_TOO_LARGE 0x9F03
205
206#define MBXERR_LOAD_FW_FAILED 0xFFFE
207#define MBXERR_FIND_FW_FAILED 0xFFFF
208
153/* Driver special codes */
154#define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */
155#define MBX_NONEMBED_ERROR 0xF9
156#define MBX_OVERTEMP_ERROR 0xFA
157#define MBX_HARDWARE_ERROR 0xFB
158#define MBX_DRVR_ERROR 0xFC
159#define MBX_BUSY 0xFD
160#define MBX_TIMEOUT 0xFE

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696 uint32_t altov;
697 uint32_t lmt;
698
699#define LMT_1GB_CAPABLE 0x0004
700#define LMT_2GB_CAPABLE 0x0008
701#define LMT_4GB_CAPABLE 0x0040
702#define LMT_8GB_CAPABLE 0x0080
703#define LMT_10GB_CAPABLE 0x0100
209/* Driver special codes */
210#define MBX_DRIVER_RESERVED 0xF9 /* Set to lowest drv status */
211#define MBX_NONEMBED_ERROR 0xF9
212#define MBX_OVERTEMP_ERROR 0xFA
213#define MBX_HARDWARE_ERROR 0xFB
214#define MBX_DRVR_ERROR 0xFC
215#define MBX_BUSY 0xFD
216#define MBX_TIMEOUT 0xFE

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752 uint32_t altov;
753 uint32_t lmt;
754
755#define LMT_1GB_CAPABLE 0x0004
756#define LMT_2GB_CAPABLE 0x0008
757#define LMT_4GB_CAPABLE 0x0040
758#define LMT_8GB_CAPABLE 0x0080
759#define LMT_10GB_CAPABLE 0x0100
760#define LMT_16GB_CAPABLE 0x0200
704/* E2E supported on adapters >= 8GB */
705#define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
706
707 uint32_t rsvd2;
708 uint32_t rsvd3;
709 uint32_t max_xri;
710 uint32_t max_iocb;
711 uint32_t max_rpi;

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720} READ_CONFIG_VAR;
721
722
723/* Structure for MB Command READ_CONFIG(0x11) */
724/* Good for SLI4 only */
725
726typedef struct
727{
761/* E2E supported on adapters >= 8GB */
762#define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
763
764 uint32_t rsvd2;
765 uint32_t rsvd3;
766 uint32_t max_xri;
767 uint32_t max_iocb;
768 uint32_t max_rpi;

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777} READ_CONFIG_VAR;
778
779
780/* Structure for MB Command READ_CONFIG(0x11) */
781/* Good for SLI4 only */
782
783typedef struct
784{
728 uint32_t rsvd1; /* Word 1 */
729#ifdef EMLXS_BIG_ENDIAN
785#ifdef EMLXS_BIG_ENDIAN
730 uint32_t topology:8;
731 uint32_t rsvd2:24; /* Word 2 */
786 uint32_t extents:1; /* Word 1 */
787 uint32_t rsvd1:31;
788
789 uint32_t topology:8; /* Word 2 */
790 uint32_t rsvd2:15;
791 uint32_t ldv:1;
792 uint32_t link_type:2;
793 uint32_t link_number:6;
732#endif
733#ifdef EMLXS_LITTLE_ENDIAN
794#endif
795#ifdef EMLXS_LITTLE_ENDIAN
734 uint32_t rsvd2:24; /* Word 2 */
796 uint32_t rsvd1:31; /* Word 1 */
797 uint32_t extents:1;
798
799 uint32_t link_number:6; /* Word 2 */
800 uint32_t link_type:2;
801 uint32_t ldv:1;
802 uint32_t rsvd2:15;
735 uint32_t topology:8;
736#endif
737 uint32_t rsvd3; /* Word 3 */
738 uint32_t edtov; /* Word 4 */
739 uint32_t rsvd4; /* Word 5 */
740 uint32_t ratov; /* Word 6 */
741 uint32_t rsvd5; /* Word 7 */
742 uint32_t rsvd6; /* Word 8 */

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777 uint16_t VPICount; /* Word 14 */
778
779 uint16_t VFIBase; /* Word 15 */
780 uint16_t VFICount; /* Word 15 */
781
782 uint16_t rsvd10; /* Word 16 */
783 uint16_t FCFICount; /* Word 16 */
784
803 uint32_t topology:8;
804#endif
805 uint32_t rsvd3; /* Word 3 */
806 uint32_t edtov; /* Word 4 */
807 uint32_t rsvd4; /* Word 5 */
808 uint32_t ratov; /* Word 6 */
809 uint32_t rsvd5; /* Word 7 */
810 uint32_t rsvd6; /* Word 8 */

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845 uint16_t VPICount; /* Word 14 */
846
847 uint16_t VFIBase; /* Word 15 */
848 uint16_t VFICount; /* Word 15 */
849
850 uint16_t rsvd10; /* Word 16 */
851 uint16_t FCFICount; /* Word 16 */
852
785 uint16_t EQCount; /* Word 17 */
786 uint16_t RQCount; /* Word 17 */
853 uint16_t RQCount; /* Word 17 */
854 uint16_t EQCount; /* Word 17 */
787
855
788 uint16_t CQCount; /* Word 18 */
789 uint16_t WQCount; /* Word 18 */
856 uint16_t WQCount; /* Word 18 */
857 uint16_t CQCount; /* Word 18 */
790#endif
791
792} READ_CONFIG4_VAR;
793
794/* Structure for MB Command READ_RCONFIG (12) */
795
796typedef struct
797{

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1169/* Good for SLI2/3 and SLI4 */
1170
1171typedef struct
1172{
1173#ifdef EMLXS_BIG_ENDIAN
1174 uint16_t rsvd1;
1175 uint16_t rpi;
1176 uint32_t CI:1;
858#endif
859
860} READ_CONFIG4_VAR;
861
862/* Structure for MB Command READ_RCONFIG (12) */
863
864typedef struct
865{

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1237/* Good for SLI2/3 and SLI4 */
1238
1239typedef struct
1240{
1241#ifdef EMLXS_BIG_ENDIAN
1242 uint16_t rsvd1;
1243 uint16_t rpi;
1244 uint32_t CI:1;
1177 uint32_t rsvd2:7;
1245 uint32_t rsvd2:1;
1246 uint32_t TERP:1;
1247 uint32_t rsvd3:4;
1248 uint32_t update:1;
1178 uint32_t did:24;
1179#endif
1180#ifdef EMLXS_LITTLE_ENDIAN
1181 uint16_t rpi;
1182 uint16_t rsvd1;
1183 uint32_t did:24;
1249 uint32_t did:24;
1250#endif
1251#ifdef EMLXS_LITTLE_ENDIAN
1252 uint16_t rpi;
1253 uint16_t rsvd1;
1254 uint32_t did:24;
1184 uint32_t rsvd2:7;
1255 uint32_t update:1;
1256 uint32_t rsvd3:4;
1257 uint32_t TERP:1;
1258 uint32_t rsvd2:1;
1185 uint32_t CI:1;
1186#endif
1187 union
1188 {
1189 ULP_BDE sp;
1190 ULP_BDE64 sp64;
1191 } un;
1192

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1418 uint32_t tc:1;
1419 uint32_t mm:1;
1420 uint32_t fa:1;
1421 uint32_t rsvd2:19;
1422#endif
1423#define AT_RESERVED 0x00 /* Reserved - attType */
1424#define AT_LINK_UP 0x01 /* Link is up */
1425#define AT_LINK_DOWN 0x02 /* Link is down */
1259 uint32_t CI:1;
1260#endif
1261 union
1262 {
1263 ULP_BDE sp;
1264 ULP_BDE64 sp64;
1265 } un;
1266

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1492 uint32_t tc:1;
1493 uint32_t mm:1;
1494 uint32_t fa:1;
1495 uint32_t rsvd2:19;
1496#endif
1497#define AT_RESERVED 0x00 /* Reserved - attType */
1498#define AT_LINK_UP 0x01 /* Link is up */
1499#define AT_LINK_DOWN 0x02 /* Link is down */
1500#define AT_NO_HARD_ALPA 0x03 /* SLI4 */
1501
1426#ifdef EMLXS_BIG_ENDIAN
1427 uint8_t granted_AL_PA;
1428 uint8_t lipAlPs;
1429 uint8_t lipType;
1430 uint8_t topology;
1431#endif
1432#ifdef EMLXS_LITTLE_ENDIAN
1433 uint8_t topology;

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1485 uint32_t Urx:2;
1486 uint32_t Utx:2;
1487 uint32_t UnlPort:4;
1488 uint32_t UlnkSpeed:8;
1489 uint32_t Ursvd2:14;
1490 uint32_t Utf:1;
1491 uint32_t Ulu:1;
1492#endif
1502#ifdef EMLXS_BIG_ENDIAN
1503 uint8_t granted_AL_PA;
1504 uint8_t lipAlPs;
1505 uint8_t lipType;
1506 uint8_t topology;
1507#endif
1508#ifdef EMLXS_LITTLE_ENDIAN
1509 uint8_t topology;

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1561 uint32_t Urx:2;
1562 uint32_t Utx:2;
1563 uint32_t UnlPort:4;
1564 uint32_t UlnkSpeed:8;
1565 uint32_t Ursvd2:14;
1566 uint32_t Utf:1;
1567 uint32_t Ulu:1;
1568#endif
1493
1494#define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1495#define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1496#define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1497#define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1498#define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1569#define LA_1GHZ_LINK 0x04 /* lnkSpeed */
1570#define LA_2GHZ_LINK 0x08 /* lnkSpeed */
1571#define LA_4GHZ_LINK 0x10 /* lnkSpeed */
1572#define LA_8GHZ_LINK 0x20 /* lnkSpeed */
1573#define LA_10GHZ_LINK 0x40 /* lnkSpeed */
1574#define LA_16GHZ_LINK 0x80 /* lnkSpeed */
1499} READ_LA_VAR;
1500
1501
1502/* Structure for MB Command CLEAR_LA (22) */
1503
1504typedef struct
1505{
1506 uint32_t eventTag; /* Event tag */

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1942} UNREG_VPI_VAR4;
1943
1944/* Structure for MB Command REG_VFI(0x9F) */
1945/* Good for SLI4 only */
1946
1947typedef struct
1948{
1949#ifdef EMLXS_BIG_ENDIAN
1575} READ_LA_VAR;
1576
1577
1578/* Structure for MB Command CLEAR_LA (22) */
1579
1580typedef struct
1581{
1582 uint32_t eventTag; /* Event tag */

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2018} UNREG_VPI_VAR4;
2019
2020/* Structure for MB Command REG_VFI(0x9F) */
2021/* Good for SLI4 only */
2022
2023typedef struct
2024{
2025#ifdef EMLXS_BIG_ENDIAN
1950 uint32_t rsvd1:3;
1951 uint32_t vp:1;
1952 uint32_t rsvd2:12;
2026 uint16_t rsvd1:2;
2027 uint16_t upd:1;
2028 uint16_t vp:1;
2029 uint16_t rsvd2:12;
1953 uint16_t vfi;
1954
1955 uint16_t vpi;
1956 uint16_t fcfi;
1957
1958 uint32_t portname[2]; /* N_PORT name */
1959
1960 ULP_BDE64 bde;
1961
1962/* CHANGE with next firmware drop */
1963 uint32_t edtov;
1964 uint32_t ratov;
1965
1966 uint32_t rsvd5:8;
1967 uint32_t sid:24;
1968#endif
1969#ifdef EMLXS_LITTLE_ENDIAN
1970 uint16_t vfi;
2030 uint16_t vfi;
2031
2032 uint16_t vpi;
2033 uint16_t fcfi;
2034
2035 uint32_t portname[2]; /* N_PORT name */
2036
2037 ULP_BDE64 bde;
2038
2039/* CHANGE with next firmware drop */
2040 uint32_t edtov;
2041 uint32_t ratov;
2042
2043 uint32_t rsvd5:8;
2044 uint32_t sid:24;
2045#endif
2046#ifdef EMLXS_LITTLE_ENDIAN
2047 uint16_t vfi;
1971 uint32_t rsvd2:12;
1972 uint32_t vp:1;
1973 uint32_t rsvd1:3;
2048 uint16_t rsvd2:12;
2049 uint16_t vp:1;
2050 uint16_t upd:1;
2051 uint16_t rsvd1:2;
1974
1975 uint16_t fcfi;
1976 uint16_t vpi;
1977
1978 uint32_t portname[2]; /* N_PORT name */
1979
1980 ULP_BDE64 bde;
1981

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2171 uint32_t chbs:1; /* Cofigure Host Backing store */
2172 uint32_t csah:1; /* Configure Synchronous Abort */
2173 /* Handling */
2174 uint32_t ccrp:1; /* Config Command Ring Polling */
2175 uint32_t cmv:1; /* Configure Max VPIs */
2176 uint32_t rsvd1:24;
2177#endif
2178#ifdef EMLXS_BIG_ENDIAN
2052
2053 uint16_t fcfi;
2054 uint16_t vpi;
2055
2056 uint32_t portname[2]; /* N_PORT name */
2057
2058 ULP_BDE64 bde;
2059

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2249 uint32_t chbs:1; /* Cofigure Host Backing store */
2250 uint32_t csah:1; /* Configure Synchronous Abort */
2251 /* Handling */
2252 uint32_t ccrp:1; /* Config Command Ring Polling */
2253 uint32_t cmv:1; /* Configure Max VPIs */
2254 uint32_t rsvd1:24;
2255#endif
2256#ifdef EMLXS_BIG_ENDIAN
2179 uint32_t rsvd2:24;
2257 uint32_t rsvd2:19; /* Reserved */
2258 uint32_t gdss:1; /* Configure Data Security SLI */
2259 uint32_t rsvd3:3; /* Reserved */
2260 uint32_t gbg:1; /* Grant BlockGuard */
2180 uint32_t gmv:1; /* Grant Max VPIs */
2181 uint32_t gcrp:1; /* Grant Command Ring Polling */
2182 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2183 uint32_t ghbs:1; /* Grant Host Backing Store */
2184 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2185 uint32_t gerbm:1; /* Grant ERBM Request */
2186 uint32_t gmx:1; /* Grant Max XRIs */
2187 uint32_t gmr:1; /* Grant Max RPIs */
2188#endif
2189#ifdef EMLXS_LITTLE_ENDIAN
2190 uint32_t gmr:1; /* Grant Max RPIs */
2191 uint32_t gmx:1; /* Grant Max XRIs */
2192 uint32_t gerbm:1; /* Grant ERBM Request */
2193 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2194 uint32_t ghbs:1; /* Grant Host Backing Store */
2195 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2196 uint32_t gcrp:1; /* Grant Command Ring Polling */
2197 uint32_t gmv:1; /* Grant Max VPIs */
2261 uint32_t gmv:1; /* Grant Max VPIs */
2262 uint32_t gcrp:1; /* Grant Command Ring Polling */
2263 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2264 uint32_t ghbs:1; /* Grant Host Backing Store */
2265 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2266 uint32_t gerbm:1; /* Grant ERBM Request */
2267 uint32_t gmx:1; /* Grant Max XRIs */
2268 uint32_t gmr:1; /* Grant Max RPIs */
2269#endif
2270#ifdef EMLXS_LITTLE_ENDIAN
2271 uint32_t gmr:1; /* Grant Max RPIs */
2272 uint32_t gmx:1; /* Grant Max XRIs */
2273 uint32_t gerbm:1; /* Grant ERBM Request */
2274 uint32_t ginb:1; /* Grant Interrupt Notification Block */
2275 uint32_t ghbs:1; /* Grant Host Backing Store */
2276 uint32_t gsah:1; /* Grant Synchronous Abort Handling */
2277 uint32_t gcrp:1; /* Grant Command Ring Polling */
2278 uint32_t gmv:1; /* Grant Max VPIs */
2198 uint32_t rsvd2:24;
2279 uint32_t gbg:1; /* Grant BlockGuard */
2280 uint32_t rsvd3:3; /* Reserved */
2281 uint32_t gdss:1; /* Configure Data Security SLI */
2282 uint32_t rsvd2:19; /* Reserved */
2199#endif
2200
2201#ifdef EMLXS_BIG_ENDIAN
2202 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2203 uint32_t max_xri:16; /* Max XRIs Port should configure */
2204#endif
2205#ifdef EMLXS_LITTLE_ENDIAN
2206 uint32_t max_xri:16; /* Max XRIs Port should configure */
2207 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2208#endif
2209
2210#ifdef EMLXS_BIG_ENDIAN
2211 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2283#endif
2284
2285#ifdef EMLXS_BIG_ENDIAN
2286 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2287 uint32_t max_xri:16; /* Max XRIs Port should configure */
2288#endif
2289#ifdef EMLXS_LITTLE_ENDIAN
2290 uint32_t max_xri:16; /* Max XRIs Port should configure */
2291 uint32_t max_rpi:16; /* Max RPIs Port should configure */
2292#endif
2293
2294#ifdef EMLXS_BIG_ENDIAN
2295 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2212 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */
2296 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2213#endif
2214#ifdef EMLXS_LITTLE_ENDIAN
2297#endif
2298#ifdef EMLXS_LITTLE_ENDIAN
2215 uint32_t rsvd3:16; /* Max HBQs Host expect to configure */
2299 uint32_t rsvd4:16; /* Max HBQs Host expect to configure */
2216 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2217#endif
2218
2300 uint32_t max_hbq:16; /* Max HBQs Host expect to configure */
2301#endif
2302
2219 uint32_t rsvd4; /* Reserved */
2303 uint32_t rsvd5; /* Reserved */
2220
2221#ifdef EMLXS_BIG_ENDIAN
2304
2305#ifdef EMLXS_BIG_ENDIAN
2222 uint32_t rsvd5:16; /* Reserved */
2306 uint32_t rsvd6:16; /* Reserved */
2223 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2224#endif
2225#ifdef EMLXS_LITTLE_ENDIAN
2226 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2307 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2308#endif
2309#ifdef EMLXS_LITTLE_ENDIAN
2310 uint32_t vpi_max:16; /* Max number of virt N-Ports */
2227 uint32_t rsvd5:16; /* Reserved */
2311 uint32_t rsvd6:16; /* Reserved */
2228#endif
2229} CONFIG_PORT_VAR;
2230
2231/* Structure for MB Command REQUEST_FEATURES (0x9D) */
2232/* Good for SLI4 only */
2233
2234typedef struct
2235{

--- 6 unchanged lines hidden (view full) ---

2242 uint32_t rsvd1:31;
2243#endif
2244
2245 uint32_t featuresRequested;
2246 uint32_t featuresEnabled;
2247
2248} REQUEST_FEATURES_VAR;
2249
2312#endif
2313} CONFIG_PORT_VAR;
2314
2315/* Structure for MB Command REQUEST_FEATURES (0x9D) */
2316/* Good for SLI4 only */
2317
2318typedef struct
2319{

--- 6 unchanged lines hidden (view full) ---

2326 uint32_t rsvd1:31;
2327#endif
2328
2329 uint32_t featuresRequested;
2330 uint32_t featuresEnabled;
2331
2332} REQUEST_FEATURES_VAR;
2333
2250#define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001
2251#define SLI4_FEATURE_NPIV 0x0002
2252#define SLI4_FEATURE_DIF 0x0004
2253#define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008
2254#define SLI4_FEATURE_FCP_INITIATOR 0x0010
2255#define SLI4_FEATURE_FCP_TARGET 0x0020
2256#define SLI4_FEATURE_FCP_COMBO 0x0040
2257#define SLI4_FEATURE_INHIBIT_FIP 0x0080
2334#define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001
2335#define SLI4_FEATURE_NPIV 0x0002
2336#define SLI4_FEATURE_DIF 0x0004
2337#define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008
2338#define SLI4_FEATURE_FCP_INITIATOR 0x0010
2339#define SLI4_FEATURE_FCP_TARGET 0x0020
2340#define SLI4_FEATURE_FCP_COMBO 0x0040
2341#define SLI4_FEATURE_RSVD1 0x0080
2342#define SLI4_FEATURE_RQD 0x0100
2343#define SLI4_FEATURE_INHIBIT_AUTO_ABTS_R 0x0200
2344#define SLI4_FEATURE_HIGH_LOGIN_MODE 0x0400
2345#define SLI4_FEATURE_PERF_HINT 0x0800
2258
2259
2260/* SLI-2 Port Control Block */
2261
2262/* SLIM POINTER */
2263#define SLIMOFF 0x30 /* WORD */
2264
2265typedef struct _SLI2_RDSC

--- 240 unchanged lines hidden (view full) ---

2506
2507typedef struct mbox_req_hdr
2508{
2509#ifdef EMLXS_BIG_ENDIAN
2510 uint32_t domain:8; /* word 6 */
2511 uint32_t port:8;
2512 uint32_t subsystem:8;
2513 uint32_t opcode:8;
2346
2347
2348/* SLI-2 Port Control Block */
2349
2350/* SLIM POINTER */
2351#define SLIMOFF 0x30 /* WORD */
2352
2353typedef struct _SLI2_RDSC

--- 240 unchanged lines hidden (view full) ---

2594
2595typedef struct mbox_req_hdr
2596{
2597#ifdef EMLXS_BIG_ENDIAN
2598 uint32_t domain:8; /* word 6 */
2599 uint32_t port:8;
2600 uint32_t subsystem:8;
2601 uint32_t opcode:8;
2602
2603 uint32_t timeout; /* word 7 */
2604
2605 uint32_t req_length; /* word 8 */
2606
2607 uint32_t reserved1:24; /* word 9 */
2608 uint32_t version:8; /* word 9 */
2514#endif
2515#ifdef EMLXS_LITTLE_ENDIAN
2516 uint32_t opcode:8;
2517 uint32_t subsystem:8;
2518 uint32_t port:8;
2519 uint32_t domain:8; /* word 6 */
2609#endif
2610#ifdef EMLXS_LITTLE_ENDIAN
2611 uint32_t opcode:8;
2612 uint32_t subsystem:8;
2613 uint32_t port:8;
2614 uint32_t domain:8; /* word 6 */
2520#endif
2615
2521 uint32_t timeout; /* word 7 */
2616 uint32_t timeout; /* word 7 */
2617
2522 uint32_t req_length; /* word 8 */
2618 uint32_t req_length; /* word 8 */
2523 uint32_t reserved1; /* word 9 */
2619
2620 uint32_t version:8; /* word 9 */
2621 uint32_t reserved1:24; /* word 9 */
2622#endif
2623
2524} mbox_req_hdr_t;
2525
2624} mbox_req_hdr_t;
2625
2626
2627typedef struct mbox_req_hdr2
2628{
2629#ifdef EMLXS_BIG_ENDIAN
2630 uint32_t vf_number:16; /* word 6 */
2631 uint32_t subsystem:8;
2632 uint32_t opcode:8;
2633
2634 uint32_t timeout; /* word 7 */
2635
2636 uint32_t req_length; /* word 8 */
2637
2638 uint32_t vh_number:6; /* word 9 */
2639 uint32_t pf_number:10;
2640 uint32_t reserved1:8;
2641 uint32_t version:8;
2642#endif
2643#ifdef EMLXS_LITTLE_ENDIAN
2644 uint32_t opcode:8;
2645 uint32_t subsystem:8;
2646 uint32_t vf_number:16; /* word 6 */
2647
2648 uint32_t timeout; /* word 7 */
2649
2650 uint32_t req_length; /* word 8 */
2651
2652 uint32_t version:8;
2653 uint32_t reserved1:8;
2654 uint32_t pf_number:10;
2655 uint32_t vh_number:6; /* word 9 */
2656#endif
2657
2658} mbox_req_hdr2_t;
2659
2526typedef struct mbox_rsp_hdr
2527{
2528#ifdef EMLXS_BIG_ENDIAN
2529 uint32_t domain:8; /* word 6 */
2530 uint32_t reserved1:8;
2531 uint32_t subsystem:8;
2532 uint32_t opcode:8;
2533

--- 17 unchanged lines hidden (view full) ---

2551
2552#define MBX_RSP_STATUS_SUCCESS 0x00
2553#define MBX_RSP_STATUS_FAILED 0x01
2554#define MBX_RSP_STATUS_ILLEGAL_REQ 0x02
2555#define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03
2556#define MBX_RSP_STATUS_FCF_IN_USE 0x3A
2557#define MBX_RSP_STATUS_NO_FCF 0x43
2558
2660typedef struct mbox_rsp_hdr
2661{
2662#ifdef EMLXS_BIG_ENDIAN
2663 uint32_t domain:8; /* word 6 */
2664 uint32_t reserved1:8;
2665 uint32_t subsystem:8;
2666 uint32_t opcode:8;
2667

--- 17 unchanged lines hidden (view full) ---

2685
2686#define MBX_RSP_STATUS_SUCCESS 0x00
2687#define MBX_RSP_STATUS_FAILED 0x01
2688#define MBX_RSP_STATUS_ILLEGAL_REQ 0x02
2689#define MBX_RSP_STATUS_ILLEGAL_FIELD 0x03
2690#define MBX_RSP_STATUS_FCF_IN_USE 0x3A
2691#define MBX_RSP_STATUS_NO_FCF 0x43
2692
2693#define MGMT_ADDI_STATUS_INCOMPATIBLE 0xA2
2694
2559typedef struct be_req_hdr
2560{
2561#ifdef EMLXS_BIG_ENDIAN
2562 uint32_t special:8; /* word 1 */
2563 uint32_t reserved2:16; /* word 1 */
2564 uint32_t sge_cnt:5; /* word 1 */
2565 uint32_t reserved1:2; /* word 1 */
2566 uint32_t embedded:1; /* word 1 */

--- 7 unchanged lines hidden (view full) ---

2574#endif
2575 uint32_t payload_length; /* word 2 */
2576 uint32_t tag_low; /* word 3 */
2577 uint32_t tag_hi; /* word 4 */
2578 uint32_t reserved3; /* word 5 */
2579 union
2580 {
2581 mbox_req_hdr_t hdr_req;
2695typedef struct be_req_hdr
2696{
2697#ifdef EMLXS_BIG_ENDIAN
2698 uint32_t special:8; /* word 1 */
2699 uint32_t reserved2:16; /* word 1 */
2700 uint32_t sge_cnt:5; /* word 1 */
2701 uint32_t reserved1:2; /* word 1 */
2702 uint32_t embedded:1; /* word 1 */

--- 7 unchanged lines hidden (view full) ---

2710#endif
2711 uint32_t payload_length; /* word 2 */
2712 uint32_t tag_low; /* word 3 */
2713 uint32_t tag_hi; /* word 4 */
2714 uint32_t reserved3; /* word 5 */
2715 union
2716 {
2717 mbox_req_hdr_t hdr_req;
2718 mbox_req_hdr2_t hdr_req2;
2582 mbox_rsp_hdr_t hdr_rsp;
2583 } un_hdr;
2584} be_req_hdr_t;
2585
2586#define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2587
2588/* SLI_CONFIG Mailbox commands */
2589

--- 5 unchanged lines hidden (view full) ---

2595#define COMMON_OPCODE_WRITE_FLASHROM 0x07
2596#define COMMON_OPCODE_CQ_CREATE 0x0C
2597#define COMMON_OPCODE_EQ_CREATE 0x0D
2598#define COMMON_OPCODE_MQ_CREATE 0x15
2599#define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2600#define COMMON_OPCODE_NOP 0x21
2601#define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2602#define COMMON_OPCODE_RESET 0x3D
2719 mbox_rsp_hdr_t hdr_rsp;
2720 } un_hdr;
2721} be_req_hdr_t;
2722
2723#define EMLXS_MAX_NONEMBED_SIZE (1024 * 64)
2724
2725/* SLI_CONFIG Mailbox commands */
2726

--- 5 unchanged lines hidden (view full) ---

2732#define COMMON_OPCODE_WRITE_FLASHROM 0x07
2733#define COMMON_OPCODE_CQ_CREATE 0x0C
2734#define COMMON_OPCODE_EQ_CREATE 0x0D
2735#define COMMON_OPCODE_MQ_CREATE 0x15
2736#define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
2737#define COMMON_OPCODE_NOP 0x21
2738#define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
2739#define COMMON_OPCODE_RESET 0x3D
2740#define COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1 0x3E
2741
2742#define COMMON_OPCODE_GET_BOOT_CFG 0x42
2743#define COMMON_OPCODE_SET_BOOT_CFG 0x43
2603#define COMMON_OPCODE_MANAGE_FAT 0x44
2744#define COMMON_OPCODE_MANAGE_FAT 0x44
2604#define COMMON_OPCODE_MCC_CREATE_EXT 0x5A
2745#define COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1 0x47
2746#define COMMON_OPCODE_GET_PORT_NAME 0x4D
2605
2747
2748#define COMMON_OPCODE_MQ_CREATE_EXT 0x5A
2749#define COMMON_OPCODE_GET_VPD_DATA 0x5B
2750#define COMMON_OPCODE_GET_PHY_DETAILS 0x66
2751#define COMMON_OPCODE_SEND_ACTIVATION 0x73
2752#define COMMON_OPCODE_RESET_LICENSES 0x74
2753#define COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB 0x79
2754
2755#define COMMON_OPCODE_GET_EXTENTS_INFO 0x9A
2756#define COMMON_OPCODE_GET_EXTENTS 0x9B
2757#define COMMON_OPCODE_ALLOC_EXTENTS 0x9C
2758#define COMMON_OPCODE_DEALLOC_EXTENTS 0x9D
2759
2760#define COMMON_OPCODE_GET_PROFILE_CAPS 0xA1
2761#define COMMON_OPCODE_GET_MR_PROFILE_CAPS 0xA2
2762#define COMMON_OPCODE_SET_MR_PROFILE_CAPS 0xA3
2763#define COMMON_OPCODE_GET_PROFILE_CFG 0xA4
2764#define COMMON_OPCODE_SET_PROFILE_CFG 0xA5
2765#define COMMON_OPCODE_GET_PROFILE_LIST 0xA6
2766#define COMMON_OPCODE_GET_ACTIVE_PROFILE 0xA7
2767#define COMMON_OPCODE_SET_ACTIVE_PROFILE 0xA8
2768#define COMMON_OPCODE_SET_FACTORY_PROFILE_CFG 0xA9
2769
2770#define COMMON_OPCODE_READ_OBJ 0xAB
2771#define COMMON_OPCODE_WRITE_OBJ 0xAC
2772#define COMMON_OPCODE_READ_OBJ_LIST 0xAD
2773#define COMMON_OPCODE_DELETE_OBJ 0xAE
2774#define COMMON_OPCODE_GET_SLI4_PARAMS 0xB5
2775
2606#define FCOE_OPCODE_WQ_CREATE 0x01
2607#define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2608#define FCOE_OPCODE_RQ_CREATE 0x05
2609#define FCOE_OPCODE_READ_FCF_TABLE 0x08
2610#define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2611#define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2612#define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2613#define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2776#define FCOE_OPCODE_WQ_CREATE 0x01
2777#define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
2778#define FCOE_OPCODE_RQ_CREATE 0x05
2779#define FCOE_OPCODE_READ_FCF_TABLE 0x08
2780#define FCOE_OPCODE_ADD_FCF_TABLE 0x09
2781#define FCOE_OPCODE_DELETE_FCF_TABLE 0x0A
2782#define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
2783#define FCOE_OPCODE_REDISCOVER_FCF_TABLE 0x10
2784#define FCOE_OPCODE_SET_FCLINK_SETTINGS 0x21
2614
2615#define DCBX_OPCODE_GET_DCBX_MODE 0x04
2616#define DCBX_OPCODE_SET_DCBX_MODE 0x05
2617
2618typedef struct
2619{
2620 struct
2621 {
2622 uint32_t opcode;
2623#define MGMT_FLASHROM_OPCODE_FLASH 1
2624#define MGMT_FLASHROM_OPCODE_SAVE 2
2625#define MGMT_FLASHROM_OPCODE_CLEAR 3
2626#define MGMT_FLASHROM_OPCODE_REPORT 4
2627#define MGMT_FLASHROM_OPCODE_INFO 5
2628#define MGMT_FLASHROM_OPCODE_CRC 6
2785
2786#define DCBX_OPCODE_GET_DCBX_MODE 0x04
2787#define DCBX_OPCODE_SET_DCBX_MODE 0x05
2788
2789typedef struct
2790{
2791 struct
2792 {
2793 uint32_t opcode;
2794#define MGMT_FLASHROM_OPCODE_FLASH 1
2795#define MGMT_FLASHROM_OPCODE_SAVE 2
2796#define MGMT_FLASHROM_OPCODE_CLEAR 3
2797#define MGMT_FLASHROM_OPCODE_REPORT 4
2798#define MGMT_FLASHROM_OPCODE_INFO 5
2799#define MGMT_FLASHROM_OPCODE_CRC 6
2800#define MGMT_FLASHROM_OPCODE_OFFSET_FLASH 7
2801#define MGMT_FLASHROM_OPCODE_OFFSET_SAVE 8
2802#define MGMT_PHY_FLASHROM_OPCODE_FLASH 9
2803#define MGMT_PHY_FLASHROM_OPCODE_SAVE 10
2629
2630 uint32_t optype;
2631#define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0
2632#define MGMT_FLASHROM_OPTYPE_REDBOOT 1
2633#define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2
2634#define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3
2635#define MGMT_FLASHROM_OPTYPE_CTRLS 4
2636#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5
2637#define MGMT_FLASHROM_OPTYPE_CFG_INI 6
2638#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7
2639#define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8
2640#define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9
2641#define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10
2642#define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11
2643#define MGMT_FLASHROM_OPTYPE_CTRLP 12
2644#define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13
2804
2805 uint32_t optype;
2806#define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0
2807#define MGMT_FLASHROM_OPTYPE_REDBOOT 1
2808#define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2
2809#define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3
2810#define MGMT_FLASHROM_OPTYPE_CTRLS 4
2811#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5
2812#define MGMT_FLASHROM_OPTYPE_CFG_INI 6
2813#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7
2814#define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8
2815#define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9
2816#define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10
2817#define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11
2818#define MGMT_FLASHROM_OPTYPE_CTRLP 12
2819#define MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE 13
2645#define MGMT_FLASHROM_OPTYPE_NCSI_8051 14
2820#define MGMT_FLASHROM_OPTYPE_CFG_NIC 14
2821#define MGMT_FLASHROM_OPTYPE_CFG_DCBX 15
2822#define MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS 16
2823#define MGMT_FLASHROM_OPTYPE_CFG_ALL 17
2824#define MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE 0xff /* Driver defined */
2646
2647 uint32_t data_buffer_size; /* Align to 4KB */
2648 uint32_t offset;
2649 uint32_t data_buffer; /* image starts here */
2650
2651 } params;
2652
2653} IOCTL_COMMON_FLASHROM;
2654
2655
2656typedef struct
2657{
2658 union
2659 {
2660 struct
2661 {
2825
2826 uint32_t data_buffer_size; /* Align to 4KB */
2827 uint32_t offset;
2828 uint32_t data_buffer; /* image starts here */
2829
2830 } params;
2831
2832} IOCTL_COMMON_FLASHROM;
2833
2834
2835typedef struct
2836{
2837 union
2838 {
2839 struct
2840 {
2841 uint32_t rsvd;
2842 } request;
2843
2844
2845 struct
2846 {
2847#ifdef EMLXS_BIG_ENDIAN
2848 uint16_t interface_type;
2849 uint16_t phy_type;
2850#endif
2851#ifdef EMLXS_LITTLE_ENDIAN
2852 uint16_t phy_type;
2853 uint16_t interface_type;
2854#endif
2855
2856/* phy_type */
2857#define PHY_XAUI 0x0
2858#define PHY_AEL_2020 0x1 /* eluris/Netlogic */
2859#define PHY_LSI_BRCM1 0x2 /* Peak pre-production board */
2860#define PHY_LSI_BRCM2 0x3 /* Peak production board */
2861#define PHY_SOLARFLARE 0x4 /* Dell recommended */
2862#define PHY_AMCC_QT2025 0x5 /* AMCC PHY */
2863#define PHY_AMCC_QT2225 0x6 /* AMCC PHY */
2864#define PHY_BRCM_5931 0x7 /* Broadcom Phy used by HP LOM */
2865#define PHY_BE3_INTERNAL_10GB 0x8 /* Internal 10GbPHY in BE3 */
2866#define PHY_BE3_INTERNAL_1GB 0x9 /* Internal 1Gb PHY in BE3 */
2867#define PHY_TN_2022 0xa /* Teranetics dual port 65nm PHY */
2868#define PHY_MARVELL_88E1340 0xb /* Marvel 1G PHY */
2869#define PHY_MARVELL_88E1322 0xc /* Marvel 1G PHY */
2870#define PHY_TN_8022 0xd /* Teranetics dual port 40nm PHY */
2871#define PHY_TYPE_NOT_SUPPORTED
2872
2873/* interface_type */
2874#define CX4_10GB_TYPE 0x0
2875#define XFP_10GB_TYPE 0x1
2876#define SFP_1GB_TYPE 0x2
2877#define SFP_PLUS_10GB_TYPE 0x3
2878#define KR_10GB_TYPE 0x4
2879#define KX4_10GB_TYPE 0x5
2880#define BASET_10GB_TYPE 0x6 /* 10G BaseT */
2881#define BASET_1000_TYPE 0x7 /* 1000 BaseT */
2882#define BASEX_1000_TYPE 0x8 /* 1000 BaseX */
2883#define SGMII_TYPE 0x9
2884#define INTERFACE_10GB_DISABLED 0xff /* Interface type not supported */
2885
2886 uint32_t misc_params;
2887 uint32_t rsvd[4];
2888 } response;
2889
2890 } params;
2891
2892} IOCTL_COMMON_GET_PHY_DETAILS;
2893
2894
2895typedef struct
2896{
2897 union
2898 {
2899 struct
2900 {
2901 uint32_t rsvd;
2902 } request;
2903
2904
2905 struct
2906 {
2907#ifdef EMLXS_BIG_ENDIAN
2908 uint8_t port3_name;
2909 uint8_t port2_name;
2910 uint8_t port1_name;
2911 uint8_t port0_name;
2912#endif
2913#ifdef EMLXS_LITTLE_ENDIAN
2914 uint8_t port0_name;
2915 uint8_t port1_name;
2916 uint8_t port2_name;
2917 uint8_t port3_name;
2918#endif
2919 } response;
2920
2921 } params;
2922
2923} IOCTL_COMMON_GET_PORT_NAME;
2924
2925
2926typedef struct
2927{
2928 union
2929 {
2930 struct
2931 {
2932#ifdef EMLXS_BIG_ENDIAN
2933 uint32_t rsvd:30;
2934 uint32_t pt:2;
2935#endif
2936#ifdef EMLXS_LITTLE_ENDIAN
2937 uint32_t pt:2;
2938 uint32_t rsvd:30;
2939#endif
2940#define PORT_TYPE_GIGE 0
2941#define PORT_TYPE_FC 1
2942 } request;
2943
2944
2945 struct
2946 {
2947#ifdef EMLXS_BIG_ENDIAN
2948 uint8_t port3_name;
2949 uint8_t port2_name;
2950 uint8_t port1_name;
2951 uint8_t port0_name;
2952#endif
2953#ifdef EMLXS_LITTLE_ENDIAN
2954 uint8_t port0_name;
2955 uint8_t port1_name;
2956 uint8_t port2_name;
2957 uint8_t port3_name;
2958#endif
2959 } response;
2960
2961 } params;
2962
2963} IOCTL_COMMON_GET_PORT_NAME_V1;
2964
2965
2966typedef struct
2967{
2968 union
2969 {
2970 struct
2971 {
2662 uint32_t fat_operation;
2663#define RETRIEVE_FAT 0
2664#define QUERY_FAT 1
2665#define CLEAR_FAT 2
2666
2667 uint32_t read_log_offset;
2668 uint32_t read_log_length;
2669 uint32_t data_buffer_size;

--- 9 unchanged lines hidden (view full) ---

2679 uint32_t data_buffer;
2680 } response;
2681
2682 } params;
2683
2684} IOCTL_COMMON_MANAGE_FAT;
2685
2686
2972 uint32_t fat_operation;
2973#define RETRIEVE_FAT 0
2974#define QUERY_FAT 1
2975#define CLEAR_FAT 2
2976
2977 uint32_t read_log_offset;
2978 uint32_t read_log_length;
2979 uint32_t data_buffer_size;

--- 9 unchanged lines hidden (view full) ---

2989 uint32_t data_buffer;
2990 } response;
2991
2992 } params;
2993
2994} IOCTL_COMMON_MANAGE_FAT;
2995
2996
2997typedef struct
2998{
2999 union
3000 {
3001 struct
3002 {
3003#ifdef EMLXS_BIG_ENDIAN
3004 uint32_t EOF:1; /* word 4 */
3005 uint32_t rsvd0:7;
3006 uint32_t desired_write_length:24;
3007#endif
3008#ifdef EMLXS_LITTLE_ENDIAN
3009 uint32_t desired_write_length:24;
3010 uint32_t rsvd0:7;
3011 uint32_t EOF:1; /* word 4 */
3012#endif
3013 uint32_t write_offset; /* word 5 */
3014 char object_name[(4 * 26)]; /* word 6 - 31 */
3015 uint32_t buffer_desc_count; /* word 32 */
3016
3017#ifdef EMLXS_BIG_ENDIAN
3018 uint32_t rsvd:8; /* word 33 */
3019 uint32_t buffer_length:24;
3020#endif
3021#ifdef EMLXS_LITTLE_ENDIAN
3022 uint32_t buffer_length:24;
3023 uint32_t rsvd:8; /* word 33 */
3024#endif
3025 uint32_t buffer_addrlo; /* word 34 */
3026 uint32_t buffer_addrhi; /* word 35 */
3027 } request;
3028
3029 struct
3030 {
3031 uint32_t actual_write_length;
3032
3033#ifdef EMLXS_BIG_ENDIAN
3034 uint32_t rsvd:24;
3035 uint32_t change_status:8;
3036#endif
3037#ifdef EMLXS_LITTLE_ENDIAN
3038 uint32_t change_status:8;
3039 uint32_t rsvd:24;
3040#endif
3041#define CS_NO_RESET 0
3042#define CS_REBOOT_RQD 1
3043#define CS_FW_RESET_RQD 2
3044#define CS_PROTO_RESET_RQD 3
3045 } response;
3046
3047 } params;
3048
3049} IOCTL_COMMON_WRITE_OBJECT;
3050
3051
3052typedef struct
3053{
3054 union
3055 {
3056 struct
3057 {
3058#ifdef EMLXS_BIG_ENDIAN
3059 uint32_t descriptor_offset:16; /* word 4 */
3060 uint32_t descriptor_count:16;
3061#endif
3062#ifdef EMLXS_LITTLE_ENDIAN
3063 uint32_t descriptor_count:16;
3064 uint32_t descriptor_offset:16; /* word 4 */
3065#endif
3066 uint32_t reserved; /* word 5 */
3067 char object_name[(4 * 26)]; /* word 6 - 31 */
3068 uint32_t buffer_desc_count; /* word 32 */
3069
3070#ifdef EMLXS_BIG_ENDIAN
3071 uint32_t rsvd:8; /* word 33 */
3072 uint32_t buffer_length:24;
3073#endif
3074#ifdef EMLXS_LITTLE_ENDIAN
3075 uint32_t buffer_length:24;
3076 uint32_t rsvd:8; /* word 33 */
3077#endif
3078 uint32_t buffer_addrlo; /* word 34 */
3079 uint32_t buffer_addrhi; /* word 35 */
3080 } request;
3081
3082 struct
3083 {
3084#ifdef EMLXS_BIG_ENDIAN
3085 uint32_t reserved:16;
3086 uint32_t actual_descriptor_count:16;
3087#endif
3088#ifdef EMLXS_LITTLE_ENDIAN
3089 uint32_t actual_descriptor_count:16;
3090 uint32_t reserved:16;
3091#endif
3092 } response;
3093
3094 } params;
3095
3096} IOCTL_COMMON_READ_OBJECT_LIST;
3097
3098
3099typedef struct
3100{
3101 union
3102 {
3103 struct
3104 {
3105#ifdef EMLXS_BIG_ENDIAN
3106 uint32_t reserved:16; /* word 4 */
3107 uint32_t boot_instance:8;
3108 uint32_t boot_status:8;
3109#endif
3110#ifdef EMLXS_LITTLE_ENDIAN
3111 uint32_t boot_status:8;
3112 uint32_t boot_instance:8;
3113 uint32_t reserved:16; /* word 4 */
3114#endif
3115 } request;
3116
3117 struct
3118 {
3119#ifdef EMLXS_BIG_ENDIAN
3120 uint32_t reserved:16; /* word 4 */
3121 uint32_t boot_instance:8;
3122 uint32_t boot_status:8;
3123#endif
3124#ifdef EMLXS_LITTLE_ENDIAN
3125 uint32_t boot_status:8;
3126 uint32_t boot_instance:8;
3127 uint32_t reserved:16; /* word 4 */
3128#endif
3129 } response;
3130
3131 } params;
3132
3133} IOCTL_COMMON_BOOT_CFG;
3134
3135
2687/* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
2688typedef struct _BE_FW_CFG
2689{
2690 uint32_t BEConfigNumber;
2691 uint32_t ASICRevision;
2692 uint32_t PhysicalPort;
2693 uint32_t FunctionMode;
2694 uint32_t ULPMode;

--- 28 unchanged lines hidden (view full) ---

2723 uint8_t fcf_mac_address_hi[4];
2724
2725 uint8_t mac_address_provider;
2726 uint8_t fcf_available;
2727 uint8_t fcf_mac_address_low[2];
2728
2729 uint8_t fabric_name_identifier[8];
2730
3136/* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3137typedef struct _BE_FW_CFG
3138{
3139 uint32_t BEConfigNumber;
3140 uint32_t ASICRevision;
3141 uint32_t PhysicalPort;
3142 uint32_t FunctionMode;
3143 uint32_t ULPMode;

--- 28 unchanged lines hidden (view full) ---

3172 uint8_t fcf_mac_address_hi[4];
3173
3174 uint8_t mac_address_provider;
3175 uint8_t fcf_available;
3176 uint8_t fcf_mac_address_low[2];
3177
3178 uint8_t fabric_name_identifier[8];
3179
2731 uint8_t fcf_valid;
3180 uint8_t fcf_sol:1;
3181 uint8_t rsvd0:5;
3182 uint8_t fcf_fc:1;
3183 uint8_t fcf_valid:1;
2732 uint8_t fc_map[3];
2733
2734 uint16_t fcf_state;
2735 uint16_t fcf_index;
2736#endif
2737#ifdef EMLXS_LITTLE_ENDIAN
2738 uint8_t fcf_mac_address_hi[4];
2739
2740 uint8_t fcf_mac_address_low[2];
2741 uint8_t fcf_available;
2742 uint8_t mac_address_provider;
2743
2744 uint8_t fabric_name_identifier[8];
2745
2746 uint8_t fc_map[3];
3184 uint8_t fc_map[3];
3185
3186 uint16_t fcf_state;
3187 uint16_t fcf_index;
3188#endif
3189#ifdef EMLXS_LITTLE_ENDIAN
3190 uint8_t fcf_mac_address_hi[4];
3191
3192 uint8_t fcf_mac_address_low[2];
3193 uint8_t fcf_available;
3194 uint8_t mac_address_provider;
3195
3196 uint8_t fabric_name_identifier[8];
3197
3198 uint8_t fc_map[3];
2747 uint8_t fcf_valid;
3199 uint8_t fcf_valid:1;
3200 uint8_t fcf_fc:1;
3201 uint8_t rsvd0:5;
3202 uint8_t fcf_sol:1;
2748
2749 uint16_t fcf_index;
2750 uint16_t fcf_state;
2751#endif
2752
2753 uint8_t vlan_bitmap[512];
2754 uint8_t switch_name_identifier[8];
2755

--- 147 unchanged lines hidden (view full) ---

2903
2904/* Context for EQ create */
2905typedef struct _EQ_CONTEXT
2906{
2907#ifdef EMLXS_BIG_ENDIAN
2908 uint32_t Size:1;
2909 uint32_t Rsvd2:1;
2910 uint32_t Valid:1;
3203
3204 uint16_t fcf_index;
3205 uint16_t fcf_state;
3206#endif
3207
3208 uint8_t vlan_bitmap[512];
3209 uint8_t switch_name_identifier[8];
3210

--- 147 unchanged lines hidden (view full) ---

3358
3359/* Context for EQ create */
3360typedef struct _EQ_CONTEXT
3361{
3362#ifdef EMLXS_BIG_ENDIAN
3363 uint32_t Size:1;
3364 uint32_t Rsvd2:1;
3365 uint32_t Valid:1;
2911 uint32_t EPIndex:13;
2912 uint32_t Rsvd1:3;
2913 uint32_t ConsumerIndex:13;
3366 uint32_t Rsvd1:29;
2914
2915 uint32_t Armed:1;
3367
3368 uint32_t Armed:1;
2916 uint32_t Stalled:1;
2917 uint32_t SolEvent:1;
3369 uint32_t Rsvd4:2;
2918 uint32_t Count:3;
3370 uint32_t Count:3;
2919 uint32_t ProtectionDomain:10;
2920 uint32_t Rsvd3:3;
2921 uint32_t ProduderIndex:13;
3371 uint32_t Rsvd3:26;
2922
3372
2923 uint32_t Rsvd7:4;
2924 uint32_t NoDelay:1;
2925 uint32_t Phase:2;
2926 uint32_t Rsvd6:2;
3373 uint32_t Rsvd6:9;
2927 uint32_t DelayMult:10;
3374 uint32_t DelayMult:10;
2928 uint32_t Rsvd5:1;
2929 uint32_t Func:8;
2930 uint32_t Rsvd4:4;
3375 uint32_t Rsvd5:13;
2931#endif
2932#ifdef EMLXS_LITTLE_ENDIAN
3376#endif
3377#ifdef EMLXS_LITTLE_ENDIAN
2933 uint32_t ConsumerIndex:13;
2934 uint32_t Rsvd1:3;
2935 uint32_t EPIndex:13;
3378 uint32_t Rsvd1:29;
2936 uint32_t Valid:1;
2937 uint32_t Rsvd2:1;
2938 uint32_t Size:1;
2939
3379 uint32_t Valid:1;
3380 uint32_t Rsvd2:1;
3381 uint32_t Size:1;
3382
2940 uint32_t ProduderIndex:13;
2941 uint32_t Rsvd3:3;
2942 uint32_t ProtectionDomain:10;
3383 uint32_t Rsvd3:26;
2943 uint32_t Count:3;
3384 uint32_t Count:3;
2944 uint32_t SolEvent:1;
2945 uint32_t Stalled:1;
3385 uint32_t Rsvd4:2;
2946 uint32_t Armed:1;
2947
3386 uint32_t Armed:1;
3387
2948 uint32_t Rsvd4:4;
2949 uint32_t Func:8;
2950 uint32_t Rsvd5:1;
3388 uint32_t Rsvd5:13;
2951 uint32_t DelayMult:10;
3389 uint32_t DelayMult:10;
2952 uint32_t Rsvd6:2;
2953 uint32_t Phase:2;
2954 uint32_t NoDelay:1;
2955 uint32_t Rsvd7:4;
3390 uint32_t Rsvd6:9;
2956#endif
2957
3391#endif
3392
2958 uint32_t Rsvd8;
3393 uint32_t Rsvd7;
2959
3394
2960}EQ_CONTEXT;
3395} EQ_CONTEXT;
2961
3396
3397
2962/* define for Count field */
2963#define EQ_ELEMENT_COUNT_1024 2
2964#define EQ_ELEMENT_COUNT_2048 3
2965#define EQ_ELEMENT_COUNT_4096 4
2966
2967/* define for Size field */
2968#define EQ_ELEMENT_SIZE_4 0
2969
2970/* define for DelayMullt - used for interrupt coalescing */
2971#define EQ_DELAY_MULT 64
2972
2973/* Context for CQ create */
2974typedef struct _CQ_CONTEXT
2975{
2976#ifdef EMLXS_BIG_ENDIAN
2977 uint32_t Eventable:1;
3398/* define for Count field */
3399#define EQ_ELEMENT_COUNT_1024 2
3400#define EQ_ELEMENT_COUNT_2048 3
3401#define EQ_ELEMENT_COUNT_4096 4
3402
3403/* define for Size field */
3404#define EQ_ELEMENT_SIZE_4 0
3405
3406/* define for DelayMullt - used for interrupt coalescing */
3407#define EQ_DELAY_MULT 64
3408
3409/* Context for CQ create */
3410typedef struct _CQ_CONTEXT
3411{
3412#ifdef EMLXS_BIG_ENDIAN
3413 uint32_t Eventable:1;
2978 uint32_t SolEvent:1;
3414 uint32_t Rsvd3:1;
2979 uint32_t Valid:1;
2980 uint32_t Count:2;
3415 uint32_t Valid:1;
3416 uint32_t Count:2;
2981 uint32_t Rsvd2:1;
2982 uint32_t EPIndex:11;
3417 uint32_t Rsvd2:12;
2983 uint32_t NoDelay:1;
2984 uint32_t CoalesceWM:2;
3418 uint32_t NoDelay:1;
3419 uint32_t CoalesceWM:2;
2985 uint32_t Rsvd1:1;
2986 uint32_t ConsumerIndex:11;
3420 uint32_t Rsvd1:12;
2987
2988 uint32_t Armed:1;
3421
3422 uint32_t Armed:1;
2989 uint32_t Stalled:1;
3423 uint32_t Rsvd5:1;
2990 uint32_t EQId:8;
3424 uint32_t EQId:8;
2991 uint32_t ProtectionDomain:10;
2992 uint32_t Rsvd3:1;
2993 uint32_t ProduderIndex:11;
3425 uint32_t Rsvd4:22;
2994
3426
2995 uint32_t Rsvd5:20;
2996 uint32_t Func:8;
2997 uint32_t Rsvd4:4;
3427 uint32_t Rsvd6;
2998#endif
2999#ifdef EMLXS_LITTLE_ENDIAN
3428#endif
3429#ifdef EMLXS_LITTLE_ENDIAN
3000 uint32_t ConsumerIndex:11;
3001 uint32_t Rsvd1:1;
3430 uint32_t Rsvd1:12;
3002 uint32_t CoalesceWM:2;
3003 uint32_t NoDelay:1;
3431 uint32_t CoalesceWM:2;
3432 uint32_t NoDelay:1;
3004 uint32_t EPIndex:11;
3005 uint32_t Rsvd2:1;
3433 uint32_t Rsvd2:12;
3006 uint32_t Count:2;
3007 uint32_t Valid:1;
3434 uint32_t Count:2;
3435 uint32_t Valid:1;
3008 uint32_t SolEvent:1;
3436 uint32_t Rsvd3:1;
3009 uint32_t Eventable:1;
3010
3437 uint32_t Eventable:1;
3438
3011 uint32_t ProduderIndex:11;
3012 uint32_t Rsvd3:1;
3013 uint32_t ProtectionDomain:10;
3439 uint32_t Rsvd4:22;
3014 uint32_t EQId:8;
3440 uint32_t EQId:8;
3015 uint32_t Stalled:1;
3441 uint32_t Rsvd5:1;
3016 uint32_t Armed:1;
3017
3442 uint32_t Armed:1;
3443
3018 uint32_t Rsvd4:4;
3019 uint32_t Func:8;
3020 uint32_t Rsvd5:20;
3444 uint32_t Rsvd6;
3021#endif
3022
3445#endif
3446
3023 uint32_t Rsvd6;
3447 uint32_t Rsvd7;
3024
3025} CQ_CONTEXT;
3026
3448
3449} CQ_CONTEXT;
3450
3451typedef struct _CQ_CONTEXT_V2
3452{
3453#ifdef EMLXS_BIG_ENDIAN
3454 uint32_t Eventable:1;
3455 uint32_t Rsvd3:1;
3456 uint32_t Valid:1;
3457 uint32_t CqeCnt:2;
3458 uint32_t CqeSize:2;
3459 uint32_t Rsvd2:9;
3460 uint32_t AutoValid:1;
3461 uint32_t NoDelay:1;
3462 uint32_t CoalesceWM:2;
3463 uint32_t Rsvd1:12;
3464
3465 uint32_t Armed:1;
3466 uint32_t Rsvd4:15;
3467 uint32_t EQId:16;
3468
3469 uint32_t Rsvd5:16;
3470 uint32_t Count1:16;
3471#endif
3472#ifdef EMLXS_LITTLE_ENDIAN
3473 uint32_t Rsvd1:12;
3474 uint32_t CoalesceWM:2;
3475 uint32_t NoDelay:1;
3476 uint32_t AutoValid:1;
3477 uint32_t Rsvd2:9;
3478 uint32_t CqeSize:2;
3479 uint32_t CqeCnt:2;
3480 uint32_t Valid:1;
3481 uint32_t Rsvd3:1;
3482 uint32_t Eventable:1;
3483
3484 uint32_t EQId:16;
3485 uint32_t Rsvd4:15;
3486 uint32_t Armed:1;
3487
3488 uint32_t Count1:16;
3489 uint32_t Rsvd5:16;
3490#endif
3491
3492 uint32_t Rsvd7;
3493
3494} CQ_CONTEXT_V2;
3495
3496/* CqeSize */
3497#define CQE_SIZE_16_BYTES 0
3498#define CQE_SIZE_32_BYTES 1
3499
3027/* define for Count field */
3028#define CQ_ELEMENT_COUNT_256 0
3029#define CQ_ELEMENT_COUNT_512 1
3030#define CQ_ELEMENT_COUNT_1024 2
3500/* define for Count field */
3501#define CQ_ELEMENT_COUNT_256 0
3502#define CQ_ELEMENT_COUNT_512 1
3503#define CQ_ELEMENT_COUNT_1024 2
3504#define CQ_ELEMENT_COUNT_SPECIFIED 3
3031
3032/* Context for MQ create */
3033typedef struct _MQ_CONTEXT
3034{
3035#ifdef EMLXS_BIG_ENDIAN
3036 uint32_t CQId:10;
3037 uint32_t Rsvd2:2;
3038 uint32_t Size:4;
3505
3506/* Context for MQ create */
3507typedef struct _MQ_CONTEXT
3508{
3509#ifdef EMLXS_BIG_ENDIAN
3510 uint32_t CQId:10;
3511 uint32_t Rsvd2:2;
3512 uint32_t Size:4;
3039 uint32_t Rsvd1:2;
3040 uint32_t ConsumerIndex:14;
3513 uint32_t Rsvd1:16;
3041
3042 uint32_t Valid:1;
3514
3515 uint32_t Valid:1;
3043 uint32_t ProtectionDomain:9;
3044 uint32_t FunctionNumber:8;
3045 uint32_t ProduderIndex:14;
3516 uint32_t Rsvd3:31;
3517
3518 uint32_t Rsvd4:21;
3519 uint32_t ACQId:10;
3520 uint32_t ACQV:1;
3046#endif
3047#ifdef EMLXS_LITTLE_ENDIAN
3521#endif
3522#ifdef EMLXS_LITTLE_ENDIAN
3048 uint32_t ConsumerIndex:14;
3049 uint32_t Rsvd1:2;
3523 uint32_t Rsvd1:16;
3050 uint32_t Size:4;
3051 uint32_t Rsvd2:2;
3052 uint32_t CQId:10;
3053
3524 uint32_t Size:4;
3525 uint32_t Rsvd2:2;
3526 uint32_t CQId:10;
3527
3054 uint32_t ProduderIndex:14;
3055 uint32_t FunctionNumber:8;
3056 uint32_t ProtectionDomain:9;
3528 uint32_t Rsvd3:31;
3057 uint32_t Valid:1;
3529 uint32_t Valid:1;
3530
3531 uint32_t ACQV:1;
3532 uint32_t ACQId:10;
3533 uint32_t Rsvd4:21;
3058#endif
3059
3534#endif
3535
3060 uint32_t Rsvd3;
3061 uint32_t Rsvd4;
3536 uint32_t Rsvd5;
3062
3063} MQ_CONTEXT;
3064
3537
3538} MQ_CONTEXT;
3539
3540
3541typedef struct _MQ_CONTEXT_V1
3542{
3543#ifdef EMLXS_BIG_ENDIAN
3544 uint32_t Rsvd2:12;
3545 uint32_t Size:4;
3546 uint32_t ACQId:16;
3547
3548 uint32_t Valid:1;
3549 uint32_t Rsvd3:31;
3550
3551 uint32_t Rsvd4:31;
3552 uint32_t ACQV:1;
3553#endif
3554#ifdef EMLXS_LITTLE_ENDIAN
3555 uint32_t ACQId:16;
3556 uint32_t Size:4;
3557 uint32_t Rsvd2:12;
3558
3559 uint32_t Rsvd3:31;
3560 uint32_t Valid:1;
3561
3562 uint32_t ACQV:1;
3563 uint32_t Rsvd4:31;
3564#endif
3565
3566 uint32_t Rsvd5;
3567
3568} MQ_CONTEXT_V1;
3569
3570
3065/* define for Size field */
3066#define MQ_ELEMENT_COUNT_16 0x05
3067
3068/* Context for RQ create */
3069typedef struct _RQ_CONTEXT
3070{
3071#ifdef EMLXS_BIG_ENDIAN
3571/* define for Size field */
3572#define MQ_ELEMENT_COUNT_16 0x05
3573
3574/* Context for RQ create */
3575typedef struct _RQ_CONTEXT
3576{
3577#ifdef EMLXS_BIG_ENDIAN
3072 uint32_t Rsvd2:8;
3073 uint32_t RQState:4;
3074 uint32_t RQSize:4;
3578 uint32_t Rsvd2:12;
3579 uint32_t RqeCnt:4;
3075 uint32_t Rsvd1:16;
3076
3077 uint32_t Rsvd3;
3078
3580 uint32_t Rsvd1:16;
3581
3582 uint32_t Rsvd3;
3583
3079 uint32_t Rsvd4:6;
3080 uint32_t CQIdRecv:10;
3584 uint32_t CQId:16;
3081 uint32_t BufferSize:16;
3082#endif
3083#ifdef EMLXS_LITTLE_ENDIAN
3084 uint32_t Rsvd1:16;
3585 uint32_t BufferSize:16;
3586#endif
3587#ifdef EMLXS_LITTLE_ENDIAN
3588 uint32_t Rsvd1:16;
3085 uint32_t RQSize:4;
3086 uint32_t RQState:4;
3087 uint32_t Rsvd2:8;
3589 uint32_t RqeCnt:4;
3590 uint32_t Rsvd2:12;
3088
3089 uint32_t Rsvd3;
3090
3091 uint32_t BufferSize:16;
3591
3592 uint32_t Rsvd3;
3593
3594 uint32_t BufferSize:16;
3092 uint32_t CQIdRecv:10;
3093 uint32_t Rsvd4:6;
3595 uint32_t CQId:16;
3094#endif
3095
3096 uint32_t Rsvd5;
3097
3098} RQ_CONTEXT;
3099
3596#endif
3597
3598 uint32_t Rsvd5;
3599
3600} RQ_CONTEXT;
3601
3602typedef struct _RQ_CONTEXT_V1
3603{
3604#ifdef EMLXS_BIG_ENDIAN
3605 uint32_t RqeCnt:16;
3606 uint32_t Rsvd1:4;
3607 uint32_t RqeSize:4;
3608 uint32_t PageSize:8;
3100
3609
3610 uint32_t Rsvd2;
3611
3612 uint32_t CQId:16;
3613 uint32_t Rsvd:16;
3614#endif
3615#ifdef EMLXS_LITTLE_ENDIAN
3616 uint32_t PageSize:8;
3617 uint32_t RqeSize:4;
3618 uint32_t Rsvd1:4;
3619 uint32_t RqeCnt:16;
3620
3621 uint32_t Rsvd2;
3622
3623 uint32_t Rsvd:16;
3624 uint32_t CQId:16;
3625#endif
3626
3627 uint32_t BufferSize;
3628
3629} RQ_CONTEXT_V1;
3630
3631/* RqeSize */
3632#define RQE_SIZE_8_BYTES 0x02
3633#define RQE_SIZE_16_BYTES 0x03
3634#define RQE_SIZE_32_BYTES 0x04
3635#define RQE_SIZE_64_BYTES 0x05
3636#define RQE_SIZE_128_BYTES 0x06
3637
3638/* RQ PageSize */
3639#define RQ_PAGE_SIZE_4K 0x01
3640#define RQ_PAGE_SIZE_8K 0x02
3641#define RQ_PAGE_SIZE_16K 0x04
3642#define RQ_PAGE_SIZE_32K 0x08
3643#define RQ_PAGE_SIZE_64K 0x10
3644
3645
3101/* IOCTL_COMMON_EQ_CREATE */
3102typedef struct
3103{
3104 union
3105 {
3106 struct
3107 {
3108#ifdef EMLXS_BIG_ENDIAN

--- 6 unchanged lines hidden (view full) ---

3115#endif
3116 EQ_CONTEXT EQContext;
3117 BE_PHYS_ADDR Pages[8];
3118 } request;
3119
3120 struct
3121 {
3122#ifdef EMLXS_BIG_ENDIAN
3646/* IOCTL_COMMON_EQ_CREATE */
3647typedef struct
3648{
3649 union
3650 {
3651 struct
3652 {
3653#ifdef EMLXS_BIG_ENDIAN

--- 6 unchanged lines hidden (view full) ---

3660#endif
3661 EQ_CONTEXT EQContext;
3662 BE_PHYS_ADDR Pages[8];
3663 } request;
3664
3665 struct
3666 {
3667#ifdef EMLXS_BIG_ENDIAN
3123 uint16_t Rsvd1;
3668 uint16_t MsiIndex; /* V1 only */
3124 uint16_t EQId;
3125#endif
3126#ifdef EMLXS_LITTLE_ENDIAN
3127 uint16_t EQId;
3669 uint16_t EQId;
3670#endif
3671#ifdef EMLXS_LITTLE_ENDIAN
3672 uint16_t EQId;
3128 uint16_t Rsvd1;
3673 uint16_t MsiIndex; /* V1 only */
3129#endif
3130 } response;
3131 } params;
3132
3133} IOCTL_COMMON_EQ_CREATE;
3134
3135
3674#endif
3675 } response;
3676 } params;
3677
3678} IOCTL_COMMON_EQ_CREATE;
3679
3680
3681typedef struct
3682{
3683#ifdef EMLXS_BIG_ENDIAN
3684 uint32_t Rsvd1:24; /* Word 0 */
3685 uint32_t ProtocolType:8;
3686
3687 uint32_t Rsvd3:3; /* Word 1 */
3688 uint32_t SliHint2:5;
3689 uint32_t SliHint1:8;
3690 uint32_t IfType:4;
3691 uint32_t SliFamily:4;
3692 uint32_t Revision:4;
3693 uint32_t Rsvd2:3;
3694 uint32_t FT:1;
3695
3696 uint32_t EqRsvd3:4; /* Word 2 */
3697 uint32_t EqeCntMethod:4;
3698 uint32_t EqPageSize:8;
3699 uint32_t EqRsvd2:4;
3700 uint32_t EqeSize:4;
3701 uint32_t EqRsvd1:4;
3702 uint32_t EqPageCnt:4;
3703
3704 uint32_t EqRsvd4:16; /* Word 3 */
3705 uint32_t EqeCntMask:16;
3706
3707 uint32_t CqRsvd3:4; /* Word 4 */
3708 uint32_t CqeCntMethod:4;
3709 uint32_t CqPageSize:8;
3710 uint32_t CQV:2;
3711 uint32_t CqRsvd2:2;
3712 uint32_t CqeSize:4;
3713 uint32_t CqRsvd1:4;
3714 uint32_t CqPageCnt:4;
3715
3716 uint32_t CqRsvd4:16; /* Word 5 */
3717 uint32_t CqeCntMask:16;
3718
3719 uint32_t MqRsvd2:4; /* Word 6 */
3720 uint32_t MqeCntMethod:4;
3721 uint32_t MqPageSize:8;
3722 uint32_t MQV:2;
3723 uint32_t MqRsvd1:10;
3724 uint32_t MqPageCnt:4;
3725
3726 uint32_t MqRsvd3:16; /* Word 7 */
3727 uint32_t MqeCntMask:16;
3728
3729 uint32_t WqRsvd3:4; /* Word 8 */
3730 uint32_t WqeCntMethod:4;
3731 uint32_t WqPageSize:8;
3732 uint32_t WQV:2;
3733 uint32_t WqeRsvd2:2;
3734 uint32_t WqeSize:4;
3735 uint32_t WqRsvd1:4;
3736 uint32_t WqPageCnt:4;
3737
3738 uint32_t WqRsvd4:16; /* Word 9 */
3739 uint32_t WqeCntMask:16;
3740
3741 uint32_t RqRsvd3:4; /* Word 10 */
3742 uint32_t RqeCntMethod:4;
3743 uint32_t RqPageSize:8;
3744 uint32_t RQV:2;
3745 uint32_t RqeRsvd2:2;
3746 uint32_t RqeSize:4;
3747 uint32_t RqRsvd1:4;
3748 uint32_t RqPageCnt:4;
3749
3750 uint32_t RqDbWin:4; /* Word 11 */
3751 uint32_t RqRsvd4:12;
3752 uint32_t RqeCntMask:16;
3753
3754 uint32_t Loopback:4; /* Word 12 */
3755 uint32_t Rsvd4:12;
3756 uint32_t PHWQ:1;
3757 uint32_t PHON:1;
3758 uint32_t PHOFF:1;
3759 uint32_t TRIR:1;
3760 uint32_t TRTY:1;
3761 uint32_t TCCA:1;
3762 uint32_t MWQE:1;
3763 uint32_t ASSI:1;
3764 uint32_t TERP:1;
3765 uint32_t TGT:1;
3766 uint32_t AREG:1;
3767 uint32_t FBRR:1;
3768 uint32_t SGLR:1;
3769 uint32_t HDRR:1;
3770 uint32_t EXT:1;
3771 uint32_t FCOE:1;
3772
3773 uint32_t SgeLength; /* Word 13 */
3774
3775 uint32_t SglRsvd2:8; /* Word 14 */
3776 uint32_t SglAlign:8;
3777 uint32_t SglPageSize:8;
3778 uint32_t SglRsvd1:4;
3779 uint32_t SglPageCnt:4;
3780
3781 uint32_t Rsvd5:16; /* Word 15 */
3782 uint32_t MinRqSize:16;
3783
3784 uint32_t MaxRqSize; /* Word 16 */
3785
3786 uint32_t RPIMax:16;
3787 uint32_t XRIMax:16; /* Word 17 */
3788
3789 uint32_t VFIMax:16;
3790 uint32_t VPIMax:16; /* Word 18 */
3791#endif
3792#ifdef EMLXS_LITTLE_ENDIAN
3793 uint32_t ProtocolType:8; /* Word 0 */
3794 uint32_t Rsvd1:24;
3795
3796 uint32_t FT:1; /* Word 1 */
3797 uint32_t Rsvd2:3;
3798 uint32_t Revision:4;
3799 uint32_t SliFamily:4;
3800 uint32_t IfType:4;
3801 uint32_t SliHint1:8;
3802 uint32_t SliHint2:5;
3803 uint32_t Rsvd3:3;
3804
3805 uint32_t EqPageCnt:4; /* Word 2 */
3806 uint32_t EqRsvd1:4;
3807 uint32_t EqeSize:4;
3808 uint32_t EqRsvd2:4;
3809 uint32_t EqPageSize:8;
3810 uint32_t EqeCntMethod:4;
3811 uint32_t EqRsvd3:4;
3812
3813 uint32_t EqeCntMask:16; /* Word 3 */
3814 uint32_t EqRsvd4:16;
3815
3816 uint32_t CqPageCnt:4; /* Word 4 */
3817 uint32_t CqRsvd1:4;
3818 uint32_t CqeSize:4;
3819 uint32_t CqRsvd2:2;
3820 uint32_t CQV:2;
3821 uint32_t CqPageSize:8;
3822 uint32_t CqeCntMethod:4;
3823 uint32_t CqRsvd3:4;
3824
3825 uint32_t CqeCntMask:16; /* Word 5 */
3826 uint32_t CqRsvd4:16;
3827
3828 uint32_t MqPageCnt:4; /* Word 6 */
3829 uint32_t MqRsvd1:10;
3830 uint32_t MQV:2;
3831 uint32_t MqPageSize:8;
3832 uint32_t MqeCntMethod:4;
3833 uint32_t MqRsvd2:4;
3834
3835 uint32_t MqeCntMask:16; /* Word 7 */
3836 uint32_t MqRsvd3:16;
3837
3838 uint32_t WqPageCnt:4; /* Word 8 */
3839 uint32_t WqRsvd1:4;
3840 uint32_t WqeSize:4;
3841 uint32_t WqeRsvd2:2;
3842 uint32_t WQV:2;
3843 uint32_t WqPageSize:8;
3844 uint32_t WqeCntMethod:4;
3845 uint32_t WqRsvd3:4;
3846
3847 uint32_t WqeCntMask:16; /* Word 9 */
3848 uint32_t WqRsvd4:16;
3849
3850 uint32_t RqPageCnt:4; /* Word 10 */
3851 uint32_t RqRsvd1:4;
3852 uint32_t RqeSize:4;
3853 uint32_t RqeRsvd2:2;
3854 uint32_t RQV:2;
3855 uint32_t RqPageSize:8;
3856 uint32_t RqeCntMethod:4;
3857 uint32_t RqRsvd3:4;
3858
3859 uint32_t RqeCntMask:16; /* Word 11 */
3860 uint32_t RqRsvd4:12;
3861 uint32_t RqDbWin:4;
3862
3863 uint32_t FCOE:1; /* Word 12 */
3864 uint32_t EXT:1;
3865 uint32_t HDRR:1;
3866 uint32_t SGLR:1;
3867 uint32_t FBRR:1;
3868 uint32_t AREG:1;
3869 uint32_t TGT:1;
3870 uint32_t TERP:1;
3871 uint32_t ASSI:1;
3872 uint32_t MWQE:1;
3873 uint32_t TCCA:1;
3874 uint32_t TRTY:1;
3875 uint32_t TRIR:1;
3876 uint32_t PHOFF:1;
3877 uint32_t PHON:1;
3878 uint32_t PHWQ:1;
3879 uint32_t Rsvd4:12;
3880 uint32_t Loopback:4;
3881
3882 uint32_t SgeLength; /* Word 13 */
3883
3884 uint32_t SglPageCnt:4; /* Word 14 */
3885 uint32_t SglRsvd1:4;
3886 uint32_t SglPageSize:8;
3887 uint32_t SglAlign:8;
3888 uint32_t SglRsvd2:8;
3889
3890 uint32_t MinRqSize:16; /* Word 15 */
3891 uint32_t Rsvd5:16;
3892
3893 uint32_t MaxRqSize; /* Word 16 */
3894
3895 uint32_t XRIMax:16; /* Word 17 */
3896 uint32_t RPIMax:16;
3897
3898 uint32_t VPIMax:16; /* Word 18 */
3899 uint32_t VFIMax:16;
3900#endif
3901
3902 uint32_t Rsvd6; /* Word 19 */
3903
3904} sli_params_t;
3905
3906/* SliFamily values */
3907#define SLI_FAMILY_BE2 0x0
3908#define SLI_FAMILY_BE3 0x1
3909#define SLI_FAMILY_LANCER_A 0xA
3910#define SLI_FAMILY_LANCER_B 0xB
3911
3912
3913
3914/* IOCTL_COMMON_SLI4_PARAMS */
3915typedef struct
3916{
3917 union
3918 {
3919 struct
3920 {
3921 uint32_t Rsvd1;
3922 } request;
3923
3924 struct
3925 {
3926 sli_params_t param;
3927 } response;
3928 } params;
3929
3930} IOCTL_COMMON_SLI4_PARAMS;
3931
3932
3933#define MAX_EXTENTS 16 /* 1 to 104 */
3934
3935/* IOCTL_COMMON_EXTENTS */
3936typedef struct
3937{
3938 union
3939 {
3940 struct
3941 {
3942#ifdef EMLXS_BIG_ENDIAN
3943 uint16_t RscCnt;
3944 uint16_t RscType;
3945#endif
3946#ifdef EMLXS_LITTLE_ENDIAN
3947 uint16_t RscType;
3948 uint16_t RscCnt;
3949#endif
3950 } request;
3951
3952 struct
3953 {
3954#ifdef EMLXS_BIG_ENDIAN
3955 uint16_t ExtentSize;
3956 uint16_t ExtentCnt;
3957#endif
3958#ifdef EMLXS_LITTLE_ENDIAN
3959 uint16_t ExtentCnt;
3960 uint16_t ExtentSize;
3961#endif
3962
3963 uint16_t RscId[MAX_EXTENTS];
3964
3965 } response;
3966 } params;
3967
3968} IOCTL_COMMON_EXTENTS;
3969
3970/* RscType */
3971#define RSC_TYPE_FCOE_VFI 0x20
3972#define RSC_TYPE_FCOE_VPI 0x21
3973#define RSC_TYPE_FCOE_RPI 0x22
3974#define RSC_TYPE_FCOE_XRI 0x23
3975
3976
3977
3136/* IOCTL_COMMON_CQ_CREATE */
3137typedef struct
3138{
3139 union
3140 {
3141 struct
3142 {
3143#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

3163 uint16_t Rsvd1;
3164#endif
3165 } response;
3166 } params;
3167
3168} IOCTL_COMMON_CQ_CREATE;
3169
3170
3978/* IOCTL_COMMON_CQ_CREATE */
3979typedef struct
3980{
3981 union
3982 {
3983 struct
3984 {
3985#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

4005 uint16_t Rsvd1;
4006#endif
4007 } response;
4008 } params;
4009
4010} IOCTL_COMMON_CQ_CREATE;
4011
4012
4013/* IOCTL_COMMON_CQ_CREATE_V2 */
4014typedef struct
4015{
4016 union
4017 {
4018 struct
4019 {
4020#ifdef EMLXS_BIG_ENDIAN
4021 uint8_t Rsvd1;
4022 uint8_t PageSize;
4023 uint16_t NumPages;
4024#endif
4025#ifdef EMLXS_LITTLE_ENDIAN
4026 uint16_t NumPages;
4027 uint8_t PageSize;
4028 uint8_t Rsvd1;
4029#endif
4030 CQ_CONTEXT_V2 CQContext;
4031 BE_PHYS_ADDR Pages[8];
4032 } request;
4033
4034 struct
4035 {
4036#ifdef EMLXS_BIG_ENDIAN
4037 uint16_t Rsvd1;
4038 uint16_t CQId;
4039#endif
4040#ifdef EMLXS_LITTLE_ENDIAN
4041 uint16_t CQId;
4042 uint16_t Rsvd1;
4043#endif
4044 } response;
4045 } params;
4046
4047} IOCTL_COMMON_CQ_CREATE_V2;
4048
4049#define CQ_PAGE_SIZE_4K 0x01
4050#define CQ_PAGE_SIZE_8K 0x02
4051#define CQ_PAGE_SIZE_16K 0x04
4052#define CQ_PAGE_SIZE_32K 0x08
4053#define CQ_PAGE_SIZE_64K 0x10
4054
4055
4056
3171/* IOCTL_COMMON_MQ_CREATE */
3172typedef struct
3173{
3174 union
3175 {
3176 struct
3177 {
3178#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

3198 uint16_t Rsvd1;
3199#endif
3200 } response;
3201 } params;
3202
3203} IOCTL_COMMON_MQ_CREATE;
3204
3205
4057/* IOCTL_COMMON_MQ_CREATE */
4058typedef struct
4059{
4060 union
4061 {
4062 struct
4063 {
4064#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

4084 uint16_t Rsvd1;
4085#endif
4086 } response;
4087 } params;
4088
4089} IOCTL_COMMON_MQ_CREATE;
4090
4091
3206/* IOCTL_COMMON_MCC_CREATE_EXT */
4092/* IOCTL_COMMON_MQ_CREATE_EXT */
3207typedef struct
3208{
3209 union
3210 {
3211 struct
3212 {
3213#ifdef EMLXS_BIG_ENDIAN
3214 uint16_t rsvd0;
3215 uint16_t num_pages;
3216#endif
3217#ifdef EMLXS_LITTLE_ENDIAN
3218 uint16_t num_pages;
3219 uint16_t rsvd0;
3220#endif
3221 uint32_t async_event_bitmap;
3222
4093typedef struct
4094{
4095 union
4096 {
4097 struct
4098 {
4099#ifdef EMLXS_BIG_ENDIAN
4100 uint16_t rsvd0;
4101 uint16_t num_pages;
4102#endif
4103#ifdef EMLXS_LITTLE_ENDIAN
4104 uint16_t num_pages;
4105 uint16_t rsvd0;
4106#endif
4107 uint32_t async_event_bitmap;
4108
3223#define ASYNC_LINK_EVENT 0x2
3224#define ASYNC_FCF_EVENT 0x4
3225#define ASYNC_GROUP5_EVENT 0x20
4109#define ASYNC_LINK_EVENT 0x00000002
4110#define ASYNC_FCF_EVENT 0x00000004
4111#define ASYNC_DCBX_EVENT 0x00000008
4112#define ASYNC_iSCSI_EVENT 0x00000010
4113#define ASYNC_GROUP5_EVENT 0x00000020
4114#define ASYNC_FC_EVENT 0x00010000
4115#define ASYNC_PORT_EVENT 0x00020000
4116#define ASYNC_VF_EVENT 0x00040000
4117#define ASYNC_MR_EVENT 0x00080000
3226
3227 MQ_CONTEXT context;
3228 BE_PHYS_ADDR pages[8];
3229 } request;
3230
3231 struct
3232 {
3233#ifdef EMLXS_BIG_ENDIAN
3234 uint16_t rsvd0;
4118
4119 MQ_CONTEXT context;
4120 BE_PHYS_ADDR pages[8];
4121 } request;
4122
4123 struct
4124 {
4125#ifdef EMLXS_BIG_ENDIAN
4126 uint16_t rsvd0;
3235 uint16_t id;
4127 uint16_t MQId;
3236#endif
3237#ifdef EMLXS_LITTLE_ENDIAN
4128#endif
4129#ifdef EMLXS_LITTLE_ENDIAN
3238 uint16_t id;
4130 uint16_t MQId;
3239 uint16_t rsvd0;
3240#endif
3241 } response;
3242
3243 } params;
3244
4131 uint16_t rsvd0;
4132#endif
4133 } response;
4134
4135 } params;
4136
3245} IOCTL_COMMON_MCC_CREATE_EXT;
4137} IOCTL_COMMON_MQ_CREATE_EXT;
3246
3247
4138
4139
4140/* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4141typedef struct
4142{
4143 union
4144 {
4145 struct
4146 {
4147#ifdef EMLXS_BIG_ENDIAN
4148 uint16_t CQId;
4149 uint16_t num_pages;
4150#endif
4151#ifdef EMLXS_LITTLE_ENDIAN
4152 uint16_t num_pages;
4153 uint16_t CQId;
4154#endif
4155 uint32_t async_event_bitmap;
4156
4157 MQ_CONTEXT_V1 context;
4158 BE_PHYS_ADDR pages[8];
4159 } request;
4160
4161 struct
4162 {
4163#ifdef EMLXS_BIG_ENDIAN
4164 uint16_t rsvd0;
4165 uint16_t MQId;
4166#endif
4167#ifdef EMLXS_LITTLE_ENDIAN
4168 uint16_t MQId;
4169 uint16_t rsvd0;
4170#endif
4171 } response;
4172
4173 } params;
4174
4175} IOCTL_COMMON_MQ_CREATE_EXT_V1;
4176
4177
3248/* IOCTL_FCOE_RQ_CREATE */
3249typedef struct
3250{
3251 union
3252 {
3253 struct
3254 {
3255#ifdef EMLXS_BIG_ENDIAN
4178/* IOCTL_FCOE_RQ_CREATE */
4179typedef struct
4180{
4181 union
4182 {
4183 struct
4184 {
4185#ifdef EMLXS_BIG_ENDIAN
3256 uint8_t rsvd0;
3257 uint8_t ulpNum;
4186 uint16_t Rsvd0;
3258 uint16_t NumPages;
3259#endif
3260#ifdef EMLXS_LITTLE_ENDIAN
3261 uint16_t NumPages;
4187 uint16_t NumPages;
4188#endif
4189#ifdef EMLXS_LITTLE_ENDIAN
4190 uint16_t NumPages;
3262 uint8_t ulpNum;
3263 uint8_t rsvd0;
4191 uint16_t Rsvd0;
3264#endif
3265 RQ_CONTEXT RQContext;
3266 BE_PHYS_ADDR Pages[8];
3267 } request;
3268
3269 struct
3270 {
3271#ifdef EMLXS_BIG_ENDIAN

--- 6 unchanged lines hidden (view full) ---

3278#endif
3279 } response;
3280
3281 } params;
3282
3283} IOCTL_FCOE_RQ_CREATE;
3284
3285
4192#endif
4193 RQ_CONTEXT RQContext;
4194 BE_PHYS_ADDR Pages[8];
4195 } request;
4196
4197 struct
4198 {
4199#ifdef EMLXS_BIG_ENDIAN

--- 6 unchanged lines hidden (view full) ---

4206#endif
4207 } response;
4208
4209 } params;
4210
4211} IOCTL_FCOE_RQ_CREATE;
4212
4213
4214/* IOCTL_FCOE_RQ_CREATE_V1 */
4215typedef struct
4216{
4217 union
4218 {
4219 struct
4220 {
4221#ifdef EMLXS_BIG_ENDIAN
4222 uint32_t DNB:1;
4223 uint32_t DFD:1;
4224 uint32_t DIM:1;
4225 uint32_t Rsvd0:13;
4226 uint32_t NumPages:16;
4227#endif
4228#ifdef EMLXS_LITTLE_ENDIAN
4229 uint32_t NumPages:16;
4230 uint32_t Rsvd0:13;
4231 uint32_t DIM:1;
4232 uint32_t DFD:1;
4233 uint32_t DNB:1;
4234#endif
4235 RQ_CONTEXT_V1 RQContext;
4236 BE_PHYS_ADDR Pages[8];
4237 } request;
4238
4239 struct
4240 {
4241#ifdef EMLXS_BIG_ENDIAN
4242 uint16_t Rsvd1;
4243 uint16_t RQId;
4244#endif
4245#ifdef EMLXS_LITTLE_ENDIAN
4246 uint16_t RQId;
4247 uint16_t Rsvd1;
4248#endif
4249 } response;
4250
4251 } params;
4252
4253} IOCTL_FCOE_RQ_CREATE_V1;
4254
4255
3286/* IOCTL_FCOE_WQ_CREATE */
3287typedef struct
3288{
3289 union
3290 {
3291 struct
3292 {
3293#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

3313#endif
3314 } response;
3315
3316 } params;
3317
3318} IOCTL_FCOE_WQ_CREATE;
3319
3320
4256/* IOCTL_FCOE_WQ_CREATE */
4257typedef struct
4258{
4259 union
4260 {
4261 struct
4262 {
4263#ifdef EMLXS_BIG_ENDIAN

--- 19 unchanged lines hidden (view full) ---

4283#endif
4284 } response;
4285
4286 } params;
4287
4288} IOCTL_FCOE_WQ_CREATE;
4289
4290
4291/* IOCTL_FCOE_WQ_CREATE_V1 */
4292typedef struct
4293{
4294 union
4295 {
4296 struct
4297 {
4298#ifdef EMLXS_BIG_ENDIAN
4299 uint16_t CQId;
4300 uint16_t NumPages;
4301
4302 uint32_t WqeCnt:16;
4303 uint32_t Rsvd1:4;
4304 uint32_t WqeSize:4;
4305 uint32_t PageSize:8;
4306#endif
4307#ifdef EMLXS_LITTLE_ENDIAN
4308 uint16_t NumPages;
4309 uint16_t CQId;
4310
4311 uint32_t PageSize:8;
4312 uint32_t WqeSize:4;
4313 uint32_t Rsvd1:4;
4314 uint32_t WqeCnt:16;
4315#endif
4316 uint32_t Rsvd:2;
4317 BE_PHYS_ADDR Pages[4];
4318 } request;
4319
4320 struct
4321 {
4322#ifdef EMLXS_BIG_ENDIAN
4323 uint16_t Rsvd0;
4324 uint16_t WQId;
4325#endif
4326#ifdef EMLXS_LITTLE_ENDIAN
4327 uint16_t WQId;
4328 uint16_t Rsvd0;
4329#endif
4330 } response;
4331
4332 } params;
4333
4334} IOCTL_FCOE_WQ_CREATE_V1;
4335
4336/* WqeSize */
4337#define WQE_SIZE_64_BYTES 0x05
4338#define WQE_SIZE_128_BYTES 0x06
4339
4340/* PageSize */
4341#define WQ_PAGE_SIZE_4K 0x01
4342#define WQ_PAGE_SIZE_8K 0x02
4343#define WQ_PAGE_SIZE_16K 0x04
4344#define WQ_PAGE_SIZE_32K 0x08
4345#define WQ_PAGE_SIZE_64K 0x10
4346
4347
4348
3321/* IOCTL_FCOE_CFG_POST_SGL_PAGES */
3322typedef struct _FCOE_SGL_PAGES
3323{
3324 BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */
3325 BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */
3326
3327} FCOE_SGL_PAGES;
3328

--- 30 unchanged lines hidden (view full) ---

3359typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
3360{
3361 union
3362 {
3363 struct
3364 {
3365#ifdef EMLXS_BIG_ENDIAN
3366 uint16_t num_pages;
4349/* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4350typedef struct _FCOE_SGL_PAGES
4351{
4352 BE_PHYS_ADDR sgl_page0; /* 1st page per XRI */
4353 BE_PHYS_ADDR sgl_page1; /* 2nd page per XRI */
4354
4355} FCOE_SGL_PAGES;
4356

--- 30 unchanged lines hidden (view full) ---

4387typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4388{
4389 union
4390 {
4391 struct
4392 {
4393#ifdef EMLXS_BIG_ENDIAN
4394 uint16_t num_pages;
3367 uint16_t starting_rpi_index;
4395 uint16_t rpi_offset;
3368#endif
3369#ifdef EMLXS_LITTLE_ENDIAN
4396#endif
4397#ifdef EMLXS_LITTLE_ENDIAN
3370 uint16_t starting_rpi_index;
4398 uint16_t rpi_offset;
3371 uint16_t num_pages;
3372#endif
3373 BE_PHYS_ADDR pages[32];
3374
3375 }request;
3376
3377 }params;
3378

--- 133 unchanged lines hidden (view full) ---

3512
3513} IOCTL_COMMON_GET_CNTL_ATTRIB;
3514
3515
3516typedef union
3517{
3518 IOCTL_COMMON_NOP NOPVar;
3519 IOCTL_FCOE_WQ_CREATE WQCreateVar;
4399 uint16_t num_pages;
4400#endif
4401 BE_PHYS_ADDR pages[32];
4402
4403 }request;
4404
4405 }params;
4406

--- 133 unchanged lines hidden (view full) ---

4540
4541} IOCTL_COMMON_GET_CNTL_ATTRIB;
4542
4543
4544typedef union
4545{
4546 IOCTL_COMMON_NOP NOPVar;
4547 IOCTL_FCOE_WQ_CREATE WQCreateVar;
4548 IOCTL_FCOE_WQ_CREATE_V1 WQCreateVar1;
4549 IOCTL_FCOE_RQ_CREATE RQCreateVar;
4550 IOCTL_FCOE_RQ_CREATE_V1 RQCreateVar1;
3520 IOCTL_COMMON_EQ_CREATE EQCreateVar;
3521 IOCTL_COMMON_CQ_CREATE CQCreateVar;
4551 IOCTL_COMMON_EQ_CREATE EQCreateVar;
4552 IOCTL_COMMON_CQ_CREATE CQCreateVar;
4553 IOCTL_COMMON_CQ_CREATE_V2 CQCreateVar2;
3522 IOCTL_COMMON_MQ_CREATE MQCreateVar;
4554 IOCTL_COMMON_MQ_CREATE MQCreateVar;
3523 IOCTL_COMMON_MCC_CREATE_EXT MCCCreateExtVar;
4555 IOCTL_COMMON_MQ_CREATE_EXT MQCreateExtVar;
4556 IOCTL_COMMON_MQ_CREATE_EXT_V1 MQCreateExtVar1;
3524 IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar;
3525 IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar;
3526 IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar;
3527 IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar;
3528 IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar;
3529 IOCTL_COMMON_FLASHROM FlashRomVar;
3530 IOCTL_COMMON_MANAGE_FAT FATVar;
3531 IOCTL_DCBX_GET_DCBX_MODE GetDCBX;
3532 IOCTL_DCBX_SET_DCBX_MODE SetDCBX;
4557 IOCTL_FCOE_CFG_POST_SGL_PAGES PostSGLVar;
4558 IOCTL_COMMON_GET_CNTL_ATTRIB GetCntlAttributesVar;
4559 IOCTL_FCOE_READ_FCF_TABLE ReadFCFTableVar;
4560 IOCTL_FCOE_ADD_FCF_TABLE AddFCFTableVar;
4561 IOCTL_FCOE_REDISCOVER_FCF_TABLE RediscoverFCFTableVar;
4562 IOCTL_COMMON_FLASHROM FlashRomVar;
4563 IOCTL_COMMON_MANAGE_FAT FATVar;
4564 IOCTL_DCBX_GET_DCBX_MODE GetDCBX;
4565 IOCTL_DCBX_SET_DCBX_MODE SetDCBX;
4566 IOCTL_COMMON_SLI4_PARAMS Sli4ParamVar;
4567 IOCTL_COMMON_EXTENTS ExtentsVar;
4568 IOCTL_COMMON_GET_PHY_DETAILS PHYDetailsVar;
4569 IOCTL_COMMON_GET_PORT_NAME PortNameVar;
4570 IOCTL_COMMON_GET_PORT_NAME_V1 PortNameVar1;
4571 IOCTL_COMMON_WRITE_OBJECT WriteObjVar;
4572 IOCTL_COMMON_BOOT_CFG BootCfgVar;
3533
3534} IOCTL_VARIANTS;
3535
3536/* Structure for MB Command SLI_CONFIG(0x9b) */
3537/* Good for SLI4 only */
3538
3539typedef struct
3540{

--- 8 unchanged lines hidden (view full) ---

3549{
3550 uint32_t varWords[63];
3551 READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */
3552 INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */
3553 CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */
3554 READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */
3555 READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */
3556 DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */
4573
4574} IOCTL_VARIANTS;
4575
4576/* Structure for MB Command SLI_CONFIG(0x9b) */
4577/* Good for SLI4 only */
4578
4579typedef struct
4580{

--- 8 unchanged lines hidden (view full) ---

4589{
4590 uint32_t varWords[63];
4591 READ_NV_VAR varRDnvp; /* cmd = x02 (READ_NVPARMS) */
4592 INIT_LINK_VAR varInitLnk; /* cmd = x05 (INIT_LINK) */
4593 CONFIG_LINK varCfgLnk; /* cmd = x07 (CONFIG_LINK) */
4594 READ_REV4_VAR varRdRev4; /* cmd = x11 (READ_REV) */
4595 READ_LNK_VAR varRdLnk; /* cmd = x12 (READ_LNK_STAT) */
4596 DUMP4_VAR varDmp4; /* cmd = x17 (DUMP) */
4597 UPDATE_CFG_VAR varUpdateCfg; /* cmd = x1b (update Cfg) */
4598 BIU_DIAG_VAR varBIUdiag; /* cmd = x84 (RUN_BIU_DIAG64) */
3557 READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */
3558 REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */
3559 UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */
3560 READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */
3561 READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */
3562 RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */
3563 REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */
3564 UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */

--- 26 unchanged lines hidden (view full) ---

3591#endif
3592#ifdef EMLXS_LITTLE_ENDIAN
3593 uint8_t mbxOwner:1; /* Low order bit first word */
3594 uint8_t mbxHc:1;
3595 uint8_t mbxReserved:6;
3596 uint8_t mbxCommand;
3597 uint16_t mbxStatus;
3598#endif
4599 READ_SPARM_VAR varRdSparm; /* cmd = x8D (READ_SPARM64) */
4600 REG_FCFI_VAR varRegFCFI; /* cmd = xA0 (REG_FCFI) */
4601 UNREG_FCFI_VAR varUnRegFCFI; /* cmd = xA2 (UNREG_FCFI) */
4602 READ_LA_VAR varReadLA; /* cmd = x95 (READ_LA64) */
4603 READ_CONFIG4_VAR varRdConfig4; /* cmd = x0B (READ_CONFIG) */
4604 RESUME_RPI_VAR varResumeRPI; /* cmd = x9E (RESUME_RPI) */
4605 REG_LOGIN_VAR varRegLogin; /* cmd = x93 (REG_RPI) */
4606 UNREG_LOGIN_VAR varUnregLogin; /* cmd = x14 (UNREG_RPI) */

--- 26 unchanged lines hidden (view full) ---

4633#endif
4634#ifdef EMLXS_LITTLE_ENDIAN
4635 uint8_t mbxOwner:1; /* Low order bit first word */
4636 uint8_t mbxHc:1;
4637 uint8_t mbxReserved:6;
4638 uint8_t mbxCommand;
4639 uint16_t mbxStatus;
4640#endif
3599 MAILVARIANTS4 un; /* 124 bytes */
4641 MAILVARIANTS4 un; /* 252 bytes */
3600} MAILBOX4; /* Used for SLI-4 */
3601
3602/*
3603 * End Structure Definitions for Mailbox Commands
3604 */
3605
3606
3607typedef struct emlxs_mbq

--- 205 unchanged lines hidden --- 		4642} MAILBOX4; /* Used for SLI-4 */
4643
4644/*
4645 * End Structure Definitions for Mailbox Commands
4646 */
4647
4648
4649typedef struct emlxs_mbq

--- 205 unchanged lines hidden ---