emlxs_sli3.c (803376f0) emlxs_sli3.c (a9800beb)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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29
30/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
31EMLXS_MSG_DEF(EMLXS_SLI3_C);
32
33static void emlxs_sli3_issue_iocb(emlxs_hba_t *hba, RING *rp, IOCBQ *iocbq);
34static void emlxs_sli3_handle_link_event(emlxs_hba_t *hba);
35static void emlxs_sli3_handle_ring_event(emlxs_hba_t *hba, int32_t ring_no,
36 uint32_t ha_copy);
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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29
30/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
31EMLXS_MSG_DEF(EMLXS_SLI3_C);
32
33static void emlxs_sli3_issue_iocb(emlxs_hba_t *hba, RING *rp, IOCBQ *iocbq);
34static void emlxs_sli3_handle_link_event(emlxs_hba_t *hba);
35static void emlxs_sli3_handle_ring_event(emlxs_hba_t *hba, int32_t ring_no,
36 uint32_t ha_copy);
37static int emlxs_sli3_mb_handle_cmd(emlxs_hba_t *hba, MAILBOXQ *mbq);
38#ifdef SFCT_SUPPORT
39static uint32_t emlxs_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp);
40#endif /* SFCT_SUPPORT */
41
42static uint32_t emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp);
43
44static uint32_t emlxs_disable_traffic_cop = 1;
45

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106static uint32_t emlxs_sli3_msi_intr(char *arg1, char *arg2);
107#endif /* MSI_SUPPORT */
108
109static void emlxs_sli3_enable_intr(emlxs_hba_t *hba);
110
111static void emlxs_sli3_disable_intr(emlxs_hba_t *hba,
112 uint32_t att);
113
37#ifdef SFCT_SUPPORT
38static uint32_t emlxs_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp);
39#endif /* SFCT_SUPPORT */
40
41static uint32_t emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp);
42
43static uint32_t emlxs_disable_traffic_cop = 1;
44

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105static uint32_t emlxs_sli3_msi_intr(char *arg1, char *arg2);
106#endif /* MSI_SUPPORT */
107
108static void emlxs_sli3_enable_intr(emlxs_hba_t *hba);
109
110static void emlxs_sli3_disable_intr(emlxs_hba_t *hba,
111 uint32_t att);
112
114static uint32_t emlxs_reset_ring(emlxs_hba_t *hba,
115 uint32_t ringno);
113
116static void emlxs_handle_ff_error(emlxs_hba_t *hba);
117
118static uint32_t emlxs_handle_mb_event(emlxs_hba_t *hba);
119
120static void emlxs_sli3_timer_check_mbox(emlxs_hba_t *hba);
121
122static uint32_t emlxs_mb_config_port(emlxs_hba_t *hba,
123 MAILBOXQ *mbq, uint32_t sli_mode,
124 uint32_t hbainit);
125static void emlxs_enable_latt(emlxs_hba_t *hba);
126
127static uint32_t emlxs_check_attention(emlxs_hba_t *hba);
128
129static uint32_t emlxs_get_attention(emlxs_hba_t *hba,
114static void emlxs_handle_ff_error(emlxs_hba_t *hba);
115
116static uint32_t emlxs_handle_mb_event(emlxs_hba_t *hba);
117
118static void emlxs_sli3_timer_check_mbox(emlxs_hba_t *hba);
119
120static uint32_t emlxs_mb_config_port(emlxs_hba_t *hba,
121 MAILBOXQ *mbq, uint32_t sli_mode,
122 uint32_t hbainit);
123static void emlxs_enable_latt(emlxs_hba_t *hba);
124
125static uint32_t emlxs_check_attention(emlxs_hba_t *hba);
126
127static uint32_t emlxs_get_attention(emlxs_hba_t *hba,
130 uint32_t msgid);
128 int32_t msgid);
131static void emlxs_proc_attention(emlxs_hba_t *hba,
132 uint32_t ha_copy);
133/* static int emlxs_handle_rcv_seq(emlxs_hba_t *hba, */
134 /* CHANNEL *cp, IOCBQ *iocbq); */
135/* static void emlxs_update_HBQ_index(emlxs_hba_t *hba, */
136 /* uint32_t hbq_id); */
137/* static void emlxs_hbq_free_all(emlxs_hba_t *hba, */
138 /* uint32_t hbq_id); */

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186 MAILBOXQ *mbq = NULL;
187 RING *rp;
188 CHANNEL *cp;
189 MATCHMAP *mp = NULL;
190 MATCHMAP *mp1 = NULL;
191 uint8_t *inptr;
192 uint8_t *outptr;
193 uint32_t status;
129static void emlxs_proc_attention(emlxs_hba_t *hba,
130 uint32_t ha_copy);
131/* static int emlxs_handle_rcv_seq(emlxs_hba_t *hba, */
132 /* CHANNEL *cp, IOCBQ *iocbq); */
133/* static void emlxs_update_HBQ_index(emlxs_hba_t *hba, */
134 /* uint32_t hbq_id); */
135/* static void emlxs_hbq_free_all(emlxs_hba_t *hba, */
136 /* uint32_t hbq_id); */

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184 MAILBOXQ *mbq = NULL;
185 RING *rp;
186 CHANNEL *cp;
187 MATCHMAP *mp = NULL;
188 MATCHMAP *mp1 = NULL;
189 uint8_t *inptr;
190 uint8_t *outptr;
191 uint32_t status;
194 uint32_t i;
192 uint16_t i;
195 uint32_t j;
196 uint32_t read_rev_reset;
197 uint32_t key = 0;
198 uint32_t fw_check;
199 uint32_t kern_update = 0;
200 uint32_t rval = 0;
201 uint32_t offset;
202 uint8_t vpd_data[DMP_VPD_SIZE];

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211 MaxIbusSize = 0;
212 read_rev_reset = 0;
213 hba->chan_count = MAX_RINGS;
214
215 if (hba->bus_type == SBUS_FC) {
216 (void) READ_SBUS_CSR_REG(hba, FC_SHS_REG(hba));
217 }
218
193 uint32_t j;
194 uint32_t read_rev_reset;
195 uint32_t key = 0;
196 uint32_t fw_check;
197 uint32_t kern_update = 0;
198 uint32_t rval = 0;
199 uint32_t offset;
200 uint8_t vpd_data[DMP_VPD_SIZE];

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209 MaxIbusSize = 0;
210 read_rev_reset = 0;
211 hba->chan_count = MAX_RINGS;
212
213 if (hba->bus_type == SBUS_FC) {
214 (void) READ_SBUS_CSR_REG(hba, FC_SHS_REG(hba));
215 }
216
219 /*
220 * Get a buffer which will be used repeatedly for mailbox commands
221 */
222 mbq = (MAILBOXQ *) kmem_zalloc((sizeof (MAILBOXQ)), KM_SLEEP);
217 /* Set the fw_check flag */
218 fw_check = cfg[CFG_FW_CHECK].current;
223
219
224 mb = (MAILBOX *)mbq;
220 if ((fw_check & 0x04) ||
221 (hba->fw_flag & FW_UPDATE_KERNEL)) {
222 kern_update = 1;
223 }
225
226 hba->mbox_queue_flag = 0;
227 hba->sli.sli3.hc_copy = 0;
228 hba->fc_edtov = FF_DEF_EDTOV;
229 hba->fc_ratov = FF_DEF_RATOV;
230 hba->fc_altov = FF_DEF_ALTOV;
231 hba->fc_arbtov = FF_DEF_ARBTOV;
232
224
225 hba->mbox_queue_flag = 0;
226 hba->sli.sli3.hc_copy = 0;
227 hba->fc_edtov = FF_DEF_EDTOV;
228 hba->fc_ratov = FF_DEF_RATOV;
229 hba->fc_altov = FF_DEF_ALTOV;
230 hba->fc_arbtov = FF_DEF_ARBTOV;
231
233 /* Set the fw_check flag */
234 fw_check = cfg[CFG_FW_CHECK].current;
232 /*
233 * Get a buffer which will be used repeatedly for mailbox commands
234 */
235 mbq = (MAILBOXQ *) kmem_zalloc((sizeof (MAILBOXQ)), KM_SLEEP);
235
236
236 if ((fw_check & 0x04) ||
237 (hba->fw_flag & FW_UPDATE_KERNEL)) {
238 kern_update = 1;
239 }
237 mb = (MAILBOX *)mbq;
240
241reset:
242 /* Initialize sli mode based on configuration parameter */
243 switch (cfg[CFG_SLI_MODE].current) {
244 case 2: /* SLI2 mode */
245 sli_mode = EMLXS_HBA_SLI2_MODE;
246 sli_mode_mask = EMLXS_SLI2_MASK;
247 break;

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878 "Unable to read configuration. Mailbox cmd=%x status=%x",
879 mb->mbxCommand, mb->mbxStatus);
880
881 rval = EIO;
882 goto failed;
883 }
884
885 /* Save the link speed capabilities */
238
239reset:
240 /* Initialize sli mode based on configuration parameter */
241 switch (cfg[CFG_SLI_MODE].current) {
242 case 2: /* SLI2 mode */
243 sli_mode = EMLXS_HBA_SLI2_MODE;
244 sli_mode_mask = EMLXS_SLI2_MASK;
245 break;

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876 "Unable to read configuration. Mailbox cmd=%x status=%x",
877 mb->mbxCommand, mb->mbxStatus);
878
879 rval = EIO;
880 goto failed;
881 }
882
883 /* Save the link speed capabilities */
886 vpd->link_speed = mb->un.varRdConfig.lmt;
884 vpd->link_speed = (uint16_t)mb->un.varRdConfig.lmt;
887 emlxs_process_link_speed(hba);
888
889 /* Set the max node count */
890 if (cfg[CFG_NUM_NODES].current > 0) {
891 hba->max_nodes =
892 min(cfg[CFG_NUM_NODES].current,
893 mb->un.varRdConfig.max_rpi);
894 } else {

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988 i, (uint32_t)*inptr, (uint32_t)*outptr);
989
990 rval = EIO;
991 goto failed;
992 }
993 }
994
995 /* Free the buffers since we were polling */
885 emlxs_process_link_speed(hba);
886
887 /* Set the max node count */
888 if (cfg[CFG_NUM_NODES].current > 0) {
889 hba->max_nodes =
890 min(cfg[CFG_NUM_NODES].current,
891 mb->un.varRdConfig.max_rpi);
892 } else {

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986 i, (uint32_t)*inptr, (uint32_t)*outptr);
987
988 rval = EIO;
989 goto failed;
990 }
991 }
992
993 /* Free the buffers since we were polling */
996 (void) emlxs_mem_put(hba, MEM_BUF, (uint8_t *)mp);
994 emlxs_mem_put(hba, MEM_BUF, (void *)mp);
997 mp = NULL;
995 mp = NULL;
998 (void) emlxs_mem_put(hba, MEM_BUF, (uint8_t *)mp1);
996 emlxs_mem_put(hba, MEM_BUF, (void *)mp1);
999 mp1 = NULL;
1000
1001 hba->channel_fcp = FC_FCP_RING;
1002 hba->channel_els = FC_ELS_RING;
1003 hba->channel_ip = FC_IP_RING;
1004 hba->channel_ct = FC_CT_RING;
1005 hba->sli.sli3.ring_count = MAX_RINGS;
1006

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1102
1103 /* Reuse mbq from previous mbox */
1104 bzero(mbq, sizeof (MAILBOXQ));
1105
1106 /*
1107 * We need to get login parameters for NID
1108 */
1109 (void) emlxs_mb_read_sparam(hba, mbq);
997 mp1 = NULL;
998
999 hba->channel_fcp = FC_FCP_RING;
1000 hba->channel_els = FC_ELS_RING;
1001 hba->channel_ip = FC_IP_RING;
1002 hba->channel_ct = FC_CT_RING;
1003 hba->sli.sli3.ring_count = MAX_RINGS;
1004

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1100
1101 /* Reuse mbq from previous mbox */
1102 bzero(mbq, sizeof (MAILBOXQ));
1103
1104 /*
1105 * We need to get login parameters for NID
1106 */
1107 (void) emlxs_mb_read_sparam(hba, mbq);
1110 mp = (MATCHMAP *)(mbq->bp);
1108 mp = (MATCHMAP *)mbq->bp;
1111 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
1112 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1113 "Unable to read parameters. Mailbox cmd=%x status=%x",
1114 mb->mbxCommand, mb->mbxStatus);
1115
1116 rval = EIO;
1117 goto failed;
1118 }
1119
1120 /* Free the buffer since we were polling */
1109 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
1110 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1111 "Unable to read parameters. Mailbox cmd=%x status=%x",
1112 mb->mbxCommand, mb->mbxStatus);
1113
1114 rval = EIO;
1115 goto failed;
1116 }
1117
1118 /* Free the buffer since we were polling */
1121 (void) emlxs_mem_put(hba, MEM_BUF, (uint8_t *)mp);
1119 emlxs_mem_put(hba, MEM_BUF, (void *)mp);
1122 mp = NULL;
1123
1124 /* If no serial number in VPD data, then use the WWPN */
1125 if (vpd->serial_num[0] == 0) {
1126 outptr = (uint8_t *)&hba->wwpn.IEEE[0];
1127 for (i = 0; i < 12; i++) {
1128 status = *outptr++;
1129 j = ((status & 0xf0) >> 4);

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1155 vpd->port_num[0] = 0;
1156 vpd->port_index = 0;
1157 }
1158
1159 /*
1160 * Make first attempt to set a port index
1161 * Check if this is a multifunction adapter
1162 */
1120 mp = NULL;
1121
1122 /* If no serial number in VPD data, then use the WWPN */
1123 if (vpd->serial_num[0] == 0) {
1124 outptr = (uint8_t *)&hba->wwpn.IEEE[0];
1125 for (i = 0; i < 12; i++) {
1126 status = *outptr++;
1127 j = ((status & 0xf0) >> 4);

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1153 vpd->port_num[0] = 0;
1154 vpd->port_index = 0;
1155 }
1156
1157 /*
1158 * Make first attempt to set a port index
1159 * Check if this is a multifunction adapter
1160 */
1163 if ((vpd->port_index == -1) &&
1161 if ((vpd->port_index == (uint32_t)-1) &&
1164 (hba->model_info.chip >= EMLXS_THOR_CHIP)) {
1165 char *buffer;
1166 int32_t i;
1167
1168 /*
1169 * The port address looks like this:
1170 * 1 - for port index 0
1171 * 1,1 - for port index 1

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1184 emlxs_strtol(&buffer[i + 1], 10);
1185 break;
1186 }
1187 }
1188 }
1189 }
1190
1191 /* Make final attempt to set a port index */
1162 (hba->model_info.chip >= EMLXS_THOR_CHIP)) {
1163 char *buffer;
1164 int32_t i;
1165
1166 /*
1167 * The port address looks like this:
1168 * 1 - for port index 0
1169 * 1,1 - for port index 1

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1182 emlxs_strtol(&buffer[i + 1], 10);
1183 break;
1184 }
1185 }
1186 }
1187 }
1188
1189 /* Make final attempt to set a port index */
1192 if (vpd->port_index == -1) {
1190 if (vpd->port_index == (uint32_t)-1) {
1193 dev_info_t *p_dip;
1194 dev_info_t *c_dip;
1195
1196 p_dip = ddi_get_parent(hba->dip);
1197 c_dip = ddi_get_child(p_dip);
1198
1199 vpd->port_index = 0;
1200 while (c_dip && (hba->dip != c_dip)) {

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1270 "Unable to configure FARP. "
1271 "Mailbox cmd=%x status=%x",
1272 mb->mbxCommand, mb->mbxStatus);
1273 }
1274 }
1275#ifdef MSI_SUPPORT
1276 /* Configure MSI map if required */
1277 if (hba->intr_count > 1) {
1191 dev_info_t *p_dip;
1192 dev_info_t *c_dip;
1193
1194 p_dip = ddi_get_parent(hba->dip);
1195 c_dip = ddi_get_child(p_dip);
1196
1197 vpd->port_index = 0;
1198 while (c_dip && (hba->dip != c_dip)) {

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1268 "Unable to configure FARP. "
1269 "Mailbox cmd=%x status=%x",
1270 mb->mbxCommand, mb->mbxStatus);
1271 }
1272 }
1273#ifdef MSI_SUPPORT
1274 /* Configure MSI map if required */
1275 if (hba->intr_count > 1) {
1276
1277 if (hba->intr_type == DDI_INTR_TYPE_MSIX) {
1278 /* always start from 0 */
1279 hba->last_msiid = 0;
1280 }
1281
1278 /* Reuse mbq from previous mbox */
1279 bzero(mbq, sizeof (MAILBOXQ));
1280
1281 emlxs_mb_config_msix(hba, mbq, hba->intr_map, hba->intr_count);
1282
1283 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) ==
1284 MBX_SUCCESS) {
1285 goto msi_configured;

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1331 (void) emlxs_mem_free_buffer(hba);
1332 fw_check = 0;
1333 goto reset;
1334 }
1335
1336msi_configured:
1337
1338
1282 /* Reuse mbq from previous mbox */
1283 bzero(mbq, sizeof (MAILBOXQ));
1284
1285 emlxs_mb_config_msix(hba, mbq, hba->intr_map, hba->intr_count);
1286
1287 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) ==
1288 MBX_SUCCESS) {
1289 goto msi_configured;

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1335 (void) emlxs_mem_free_buffer(hba);
1336 fw_check = 0;
1337 goto reset;
1338 }
1339
1340msi_configured:
1341
1342
1343 if ((hba->intr_count >= 1) &&
1344 (hba->sli_mode == EMLXS_HBA_SLI3_MODE)) {
1345 /* intr_count is a sequence of msi id */
1346 /* Setup msi2chan[msi_id] */
1347 for (i = 0; i < hba->intr_count; i ++) {
1348 hba->msi2chan[i] = i;
1349 if (i >= hba->chan_count)
1350 hba->msi2chan[i] = (i - hba->chan_count);
1351 }
1352 }
1339#endif /* MSI_SUPPORT */
1340
1341 /*
1342 * We always disable the firmware traffic cop feature
1343 */
1344 if (emlxs_disable_traffic_cop) {
1345 /* Reuse mbq from previous mbox */
1346 bzero(mbq, sizeof (MAILBOXQ));

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1457 rp = &hba->sli.sli3.ring[FC_CT_RING];
1458 for (j = 0; j < MEM_CTBUF_COUNT; j += 2) {
1459 (void) emlxs_post_buffer(hba, rp, 2);
1460 }
1461 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1462 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1463 }
1464
1353#endif /* MSI_SUPPORT */
1354
1355 /*
1356 * We always disable the firmware traffic cop feature
1357 */
1358 if (emlxs_disable_traffic_cop) {
1359 /* Reuse mbq from previous mbox */
1360 bzero(mbq, sizeof (MAILBOXQ));

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1471 rp = &hba->sli.sli3.ring[FC_CT_RING];
1472 for (j = 0; j < MEM_CTBUF_COUNT; j += 2) {
1473 (void) emlxs_post_buffer(hba, rp, 2);
1474 }
1475 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1476 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1477 }
1478
1479 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1465
1480
1466 /* Reuse mbq from previous mbox */
1467 bzero(mbq, sizeof (MAILBOXQ));
1468
1469 /*
1470 * Setup and issue mailbox INITIALIZE LINK command
1471 * At this point, the interrupt will be generated by the HW
1472 * Do this only if persist-linkdown is not set
1473 */
1474 if (cfg[CFG_PERSIST_LINKDOWN].current == 0) {
1481 /*
1482 * Setup and issue mailbox INITIALIZE LINK command
1483 * At this point, the interrupt will be generated by the HW
1484 * Do this only if persist-linkdown is not set
1485 */
1486 if (cfg[CFG_PERSIST_LINKDOWN].current == 0) {
1487 mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1);
1488 if (mbq == NULL) {
1489 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1490 "Unable to allocate mailbox buffer.");
1491
1492 rval = EIO;
1493 goto failed;
1494 }
1495
1475 emlxs_mb_init_link(hba, mbq, cfg[CFG_TOPOLOGY].current,
1476 cfg[CFG_LINK_SPEED].current);
1477
1478 rval = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
1479 if ((rval != MBX_SUCCESS) && (rval != MBX_BUSY)) {
1496 emlxs_mb_init_link(hba, mbq, cfg[CFG_TOPOLOGY].current,
1497 cfg[CFG_LINK_SPEED].current);
1498
1499 rval = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
1500 if ((rval != MBX_SUCCESS) && (rval != MBX_BUSY)) {
1480
1481 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1482 "Unable to initialize link. " \
1483 "Mailbox cmd=%x status=%x",
1484 mb->mbxCommand, mb->mbxStatus);
1485
1501 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1502 "Unable to initialize link. " \
1503 "Mailbox cmd=%x status=%x",
1504 mb->mbxCommand, mb->mbxStatus);
1505
1506 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
1507 mbq = NULL;
1486 rval = EIO;
1487 goto failed;
1488 }
1489
1490 /*
1491 * Enable link attention interrupt
1492 */
1493 emlxs_enable_latt(hba);
1494
1495 /* Wait for link to come up */
1496 i = cfg[CFG_LINKUP_DELAY].current;
1497 while (i && (hba->state < FC_LINK_UP)) {
1498 /* Check for hardware error */
1499 if (hba->state == FC_ERROR) {
1500 EMLXS_MSGF(EMLXS_CONTEXT,
1501 &emlxs_init_failed_msg,
1508 rval = EIO;
1509 goto failed;
1510 }
1511
1512 /*
1513 * Enable link attention interrupt
1514 */
1515 emlxs_enable_latt(hba);
1516
1517 /* Wait for link to come up */
1518 i = cfg[CFG_LINKUP_DELAY].current;
1519 while (i && (hba->state < FC_LINK_UP)) {
1520 /* Check for hardware error */
1521 if (hba->state == FC_ERROR) {
1522 EMLXS_MSGF(EMLXS_CONTEXT,
1523 &emlxs_init_failed_msg,
1502 "Adapter error.", mb->mbxCommand,
1503 mb->mbxStatus);
1524 "Adapter error.");
1504
1525
1526 mbq = NULL;
1505 rval = EIO;
1506 goto failed;
1507 }
1508
1509 DELAYMS(1000);
1510 i--;
1511 }
1512 } else {
1513 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN_PERSIST);
1514 }
1515
1516 /*
1517 * The leadvile driver will now handle the FLOGI at the driver level
1518 */
1519
1527 rval = EIO;
1528 goto failed;
1529 }
1530
1531 DELAYMS(1000);
1532 i--;
1533 }
1534 } else {
1535 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN_PERSIST);
1536 }
1537
1538 /*
1539 * The leadvile driver will now handle the FLOGI at the driver level
1540 */
1541
1520 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1521 return (0);
1522
1523failed:
1524
1525 EMLXS_STATE_CHANGE(hba, FC_ERROR);
1526
1527 if (hba->intr_flags & EMLXS_MSI_ADDED) {
1528 (void) EMLXS_INTR_REMOVE(hba);
1529 }
1530
1531 if (mp) {
1542 return (0);
1543
1544failed:
1545
1546 EMLXS_STATE_CHANGE(hba, FC_ERROR);
1547
1548 if (hba->intr_flags & EMLXS_MSI_ADDED) {
1549 (void) EMLXS_INTR_REMOVE(hba);
1550 }
1551
1552 if (mp) {
1532 (void) emlxs_mem_put(hba, MEM_BUF, (uint8_t *)mp);
1553 emlxs_mem_put(hba, MEM_BUF, (void *)mp);
1533 mp = NULL;
1534 }
1535
1536 if (mp1) {
1554 mp = NULL;
1555 }
1556
1557 if (mp1) {
1537 (void) emlxs_mem_put(hba, MEM_BUF, (uint8_t *)mp1);
1558 emlxs_mem_put(hba, MEM_BUF, (void *)mp1);
1538 mp1 = NULL;
1539 }
1540
1541 (void) emlxs_mem_free_buffer(hba);
1542
1543 if (mbq) {
1544 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1545 mbq = NULL;

--- 147 unchanged lines hidden (view full) ---

1693 buf_info->align = ddi_ptob(dip, 1L);
1694
1695 (void) emlxs_mem_alloc(hba, buf_info);
1696
1697 if (buf_info->virt == NULL) {
1698 goto failed;
1699 }
1700
1559 mp1 = NULL;
1560 }
1561
1562 (void) emlxs_mem_free_buffer(hba);
1563
1564 if (mbq) {
1565 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1566 mbq = NULL;

--- 147 unchanged lines hidden (view full) ---

1714 buf_info->align = ddi_ptob(dip, 1L);
1715
1716 (void) emlxs_mem_alloc(hba, buf_info);
1717
1718 if (buf_info->virt == NULL) {
1719 goto failed;
1720 }
1721
1701 hba->sli.sli3.slim2.virt = (uint8_t *)buf_info->virt;
1722 hba->sli.sli3.slim2.virt = buf_info->virt;
1702 hba->sli.sli3.slim2.phys = buf_info->phys;
1703 hba->sli.sli3.slim2.size = SLI_SLIM2_SIZE;
1704 hba->sli.sli3.slim2.data_handle = buf_info->data_handle;
1705 hba->sli.sli3.slim2.dma_handle = buf_info->dma_handle;
1706 bzero((char *)hba->sli.sli3.slim2.virt, SLI_SLIM2_SIZE);
1707 }
1708
1709 /* offset from beginning of register space */

--- 69 unchanged lines hidden (view full) ---

1779
1780 if (hba->sli.sli3.slim2.phys) {
1781 buf_info->phys = hba->sli.sli3.slim2.phys;
1782 buf_info->data_handle = hba->sli.sli3.slim2.data_handle;
1783 buf_info->dma_handle = hba->sli.sli3.slim2.dma_handle;
1784 buf_info->flags = FC_MBUF_DMA;
1785 }
1786
1723 hba->sli.sli3.slim2.phys = buf_info->phys;
1724 hba->sli.sli3.slim2.size = SLI_SLIM2_SIZE;
1725 hba->sli.sli3.slim2.data_handle = buf_info->data_handle;
1726 hba->sli.sli3.slim2.dma_handle = buf_info->dma_handle;
1727 bzero((char *)hba->sli.sli3.slim2.virt, SLI_SLIM2_SIZE);
1728 }
1729
1730 /* offset from beginning of register space */

--- 69 unchanged lines hidden (view full) ---

1800
1801 if (hba->sli.sli3.slim2.phys) {
1802 buf_info->phys = hba->sli.sli3.slim2.phys;
1803 buf_info->data_handle = hba->sli.sli3.slim2.data_handle;
1804 buf_info->dma_handle = hba->sli.sli3.slim2.dma_handle;
1805 buf_info->flags = FC_MBUF_DMA;
1806 }
1807
1787 buf_info->virt = (uint32_t *)hba->sli.sli3.slim2.virt;
1808 buf_info->virt = hba->sli.sli3.slim2.virt;
1788 buf_info->size = hba->sli.sli3.slim2.size;
1789 emlxs_mem_free(hba, buf_info);
1790
1809 buf_info->size = hba->sli.sli3.slim2.size;
1810 emlxs_mem_free(hba, buf_info);
1811
1791 hba->sli.sli3.slim2.virt = 0;
1812 hba->sli.sli3.slim2.virt = NULL;
1792 }
1793
1794
1795 return;
1796
1797} /* emlxs_sli3_unmap_hdw() */
1798
1799
1800static uint32_t
1801emlxs_sli3_hba_init(emlxs_hba_t *hba)
1802{
1803 emlxs_port_t *port = &PPORT;
1804 emlxs_port_t *vport;
1805 emlxs_config_t *cfg;
1813 }
1814
1815
1816 return;
1817
1818} /* emlxs_sli3_unmap_hdw() */
1819
1820
1821static uint32_t
1822emlxs_sli3_hba_init(emlxs_hba_t *hba)
1823{
1824 emlxs_port_t *port = &PPORT;
1825 emlxs_port_t *vport;
1826 emlxs_config_t *cfg;
1806 int32_t i;
1827 uint16_t i;
1807
1808 cfg = &CFG;
1809 i = 0;
1810
1811 /* Restart the adapter */
1812 if (emlxs_sli3_hba_reset(hba, 1, 0, 0)) {
1813 return (1);
1814 }

--- 64 unchanged lines hidden (view full) ---

1879
1880 /* Initialize all the port objects */
1881 hba->vpi_base = 0;
1882 hba->vpi_max = 0;
1883 for (i = 0; i < MAX_VPORTS; i++) {
1884 vport = &VPORT(i);
1885 vport->hba = hba;
1886 vport->vpi = i;
1828
1829 cfg = &CFG;
1830 i = 0;
1831
1832 /* Restart the adapter */
1833 if (emlxs_sli3_hba_reset(hba, 1, 0, 0)) {
1834 return (1);
1835 }

--- 64 unchanged lines hidden (view full) ---

1900
1901 /* Initialize all the port objects */
1902 hba->vpi_base = 0;
1903 hba->vpi_max = 0;
1904 for (i = 0; i < MAX_VPORTS; i++) {
1905 vport = &VPORT(i);
1906 vport->hba = hba;
1907 vport->vpi = i;
1908 vport->VPIobj.index = i;
1909 vport->VPIobj.VPI = i;
1910 vport->VPIobj.port = vport;
1911 vport->VPIobj.state = VPI_STATE_OFFLINE;
1887 }
1888
1889 /*
1890 * Initialize the max_node count to a default value if needed
1891 * This determines how many node objects we preallocate in the pool
1892 * The actual max_nodes will be set later based on adapter info
1893 */
1894 if (hba->max_nodes == 0) {

--- 215 unchanged lines hidden (view full) ---

2110 for (i = 0; i < MAX_VPORTS; i++) {
2111 vport = &VPORT(i);
2112
2113 vport->flag &= EMLXS_PORT_RESET_MASK;
2114 vport->did = 0;
2115 vport->prev_did = 0;
2116 vport->lip_type = 0;
2117 bzero(&vport->fabric_sparam, sizeof (SERV_PARM));
1912 }
1913
1914 /*
1915 * Initialize the max_node count to a default value if needed
1916 * This determines how many node objects we preallocate in the pool
1917 * The actual max_nodes will be set later based on adapter info
1918 */
1919 if (hba->max_nodes == 0) {

--- 215 unchanged lines hidden (view full) ---

2135 for (i = 0; i < MAX_VPORTS; i++) {
2136 vport = &VPORT(i);
2137
2138 vport->flag &= EMLXS_PORT_RESET_MASK;
2139 vport->did = 0;
2140 vport->prev_did = 0;
2141 vport->lip_type = 0;
2142 bzero(&vport->fabric_sparam, sizeof (SERV_PARM));
2143 bzero(&vport->prev_fabric_sparam, sizeof (SERV_PARM));
2118
2119 bzero((caddr_t)&vport->node_base, sizeof (NODELIST));
2120 vport->node_base.nlp_Rpi = 0;
2121 vport->node_base.nlp_DID = 0xffffff;
2122 vport->node_base.nlp_list_next = NULL;
2123 vport->node_base.nlp_list_prev = NULL;
2124 vport->node_base.nlp_active = 1;
2125 vport->node_count = 0;

--- 917 unchanged lines hidden (view full) ---

3043/* MBX_WAIT - returns MBX_TIMEOUT or mailbox_status */
3044/* MBX_SLEEP - returns MBX_TIMEOUT or mailbox_status */
3045/* MBX_POLL - returns MBX_TIMEOUT or mailbox_status */
3046
3047static uint32_t
3048emlxs_sli3_issue_mbox_cmd(emlxs_hba_t *hba, MAILBOXQ *mbq, int32_t flag,
3049 uint32_t tmo)
3050{
2144
2145 bzero((caddr_t)&vport->node_base, sizeof (NODELIST));
2146 vport->node_base.nlp_Rpi = 0;
2147 vport->node_base.nlp_DID = 0xffffff;
2148 vport->node_base.nlp_list_next = NULL;
2149 vport->node_base.nlp_list_prev = NULL;
2150 vport->node_base.nlp_active = 1;
2151 vport->node_count = 0;

--- 917 unchanged lines hidden (view full) ---

3069/* MBX_WAIT - returns MBX_TIMEOUT or mailbox_status */
3070/* MBX_SLEEP - returns MBX_TIMEOUT or mailbox_status */
3071/* MBX_POLL - returns MBX_TIMEOUT or mailbox_status */
3072
3073static uint32_t
3074emlxs_sli3_issue_mbox_cmd(emlxs_hba_t *hba, MAILBOXQ *mbq, int32_t flag,
3075 uint32_t tmo)
3076{
3051 emlxs_port_t *port = &PPORT;
3077 emlxs_port_t *port;
3052 SLIM2 *slim2p = (SLIM2 *)hba->sli.sli3.slim2.virt;
3053 MAILBOX *mbox;
3054 MAILBOX *mb;
3055 volatile uint32_t word0;
3056 volatile uint32_t ldata;
3057 uint32_t ha_copy;
3058 off_t offset;
3059 MATCHMAP *mbox_bp;
3060 uint32_t tmo_local;
3061 MAILBOX *swpmb;
3062
3078 SLIM2 *slim2p = (SLIM2 *)hba->sli.sli3.slim2.virt;
3079 MAILBOX *mbox;
3080 MAILBOX *mb;
3081 volatile uint32_t word0;
3082 volatile uint32_t ldata;
3083 uint32_t ha_copy;
3084 off_t offset;
3085 MATCHMAP *mbox_bp;
3086 uint32_t tmo_local;
3087 MAILBOX *swpmb;
3088
3089 if (!mbq->port) {
3090 mbq->port = &PPORT;
3091 }
3092
3093 port = (emlxs_port_t *)mbq->port;
3094
3063 mb = (MAILBOX *)mbq;
3064 swpmb = (MAILBOX *)&word0;
3065
3066 mb->mbxStatus = MBX_SUCCESS;
3067
3068 /* Check for minimum timeouts */
3069 switch (mb->mbxCommand) {
3070 /* Mailbox commands that erase/write flash */

--- 498 unchanged lines hidden (view full) ---

3569 "Adapter Busy. Unable to setup buffer list. did=%x", did);
3570
3571 return (IOERR_INTERNAL_ERROR);
3572 }
3573 /* Point of no return */
3574
3575 /* Initalize iocb */
3576 iocb->ULPCONTEXT = (uint16_t)fct_cmd->cmd_rxid;
3095 mb = (MAILBOX *)mbq;
3096 swpmb = (MAILBOX *)&word0;
3097
3098 mb->mbxStatus = MBX_SUCCESS;
3099
3100 /* Check for minimum timeouts */
3101 switch (mb->mbxCommand) {
3102 /* Mailbox commands that erase/write flash */

--- 498 unchanged lines hidden (view full) ---

3601 "Adapter Busy. Unable to setup buffer list. did=%x", did);
3602
3603 return (IOERR_INTERNAL_ERROR);
3604 }
3605 /* Point of no return */
3606
3607 /* Initalize iocb */
3608 iocb->ULPCONTEXT = (uint16_t)fct_cmd->cmd_rxid;
3577 iocb->ULPIOTAG = iotag;
3609 iocb->ULPIOTAG = (uint16_t)iotag;
3578 iocb->ULPRSVDBYTE = ((timeout > 0xff) ? 0 : timeout);
3579 iocb->ULPOWNER = OWN_CHIP;
3580 iocb->ULPCLASS = cmd_sbp->class;
3581
3582 iocb->ULPPU = 1; /* Wd4 is relative offset */
3583 iocb->un.fcpt64.fcpt_Offset = dbuf->db_relative_offset;
3584
3585 if (fct_task->task_flags & TF_WRITE_DATA) {
3586 iocb->ULPCOMMAND = CMD_FCP_TRECEIVE64_CX;
3587 } else { /* TF_READ_DATA */
3588
3589 iocb->ULPCOMMAND = CMD_FCP_TSEND64_CX;
3590
3591 if ((hba->sli_mode == EMLXS_HBA_SLI3_MODE) &&
3592 (dbuf->db_data_size ==
3610 iocb->ULPRSVDBYTE = ((timeout > 0xff) ? 0 : timeout);
3611 iocb->ULPOWNER = OWN_CHIP;
3612 iocb->ULPCLASS = cmd_sbp->class;
3613
3614 iocb->ULPPU = 1; /* Wd4 is relative offset */
3615 iocb->un.fcpt64.fcpt_Offset = dbuf->db_relative_offset;
3616
3617 if (fct_task->task_flags & TF_WRITE_DATA) {
3618 iocb->ULPCOMMAND = CMD_FCP_TRECEIVE64_CX;
3619 } else { /* TF_READ_DATA */
3620
3621 iocb->ULPCOMMAND = CMD_FCP_TSEND64_CX;
3622
3623 if ((hba->sli_mode == EMLXS_HBA_SLI3_MODE) &&
3624 (dbuf->db_data_size ==
3593 fct_task->task_expected_xfer_length))
3625 fct_task->task_expected_xfer_length)) {
3594 iocb->ULPCT = 0x1;
3595 /* enable auto-rsp AP feature */
3626 iocb->ULPCT = 0x1;
3627 /* enable auto-rsp AP feature */
3628 }
3596 }
3597
3598 return (IOERR_SUCCESS);
3599
3600} /* emlxs_sli3_prep_fct_iocb() */
3601#endif /* SFCT_SUPPORT */
3602
3603/* ARGSUSED */

--- 161 unchanged lines hidden (view full) ---

3765 iocb->ULPOWNER = OWN_CHIP;
3766
3767 if (pkt->pkt_tran_type == FC_PKT_BROADCAST) {
3768 HBASTATS.IpBcastIssued++;
3769
3770 iocb->ULPCOMMAND = CMD_XMIT_BCAST64_CN;
3771 iocb->ULPCONTEXT = 0;
3772
3629 }
3630
3631 return (IOERR_SUCCESS);
3632
3633} /* emlxs_sli3_prep_fct_iocb() */
3634#endif /* SFCT_SUPPORT */
3635
3636/* ARGSUSED */

--- 161 unchanged lines hidden (view full) ---

3798 iocb->ULPOWNER = OWN_CHIP;
3799
3800 if (pkt->pkt_tran_type == FC_PKT_BROADCAST) {
3801 HBASTATS.IpBcastIssued++;
3802
3803 iocb->ULPCOMMAND = CMD_XMIT_BCAST64_CN;
3804 iocb->ULPCONTEXT = 0;
3805
3773 if (hba->sli_mode == 3) {
3806 if (hba->sli_mode == EMLXS_HBA_SLI3_MODE) {
3774 if (hba->topology != TOPOLOGY_LOOP) {
3775 iocb->ULPCT = 0x1;
3776 }
3777 iocb->ULPCONTEXT = port->vpi;
3778 }
3807 if (hba->topology != TOPOLOGY_LOOP) {
3808 iocb->ULPCT = 0x1;
3809 }
3810 iocb->ULPCONTEXT = port->vpi;
3811 }
3779
3780 } else {
3781 HBASTATS.IpSeqIssued++;
3782
3783 iocb->ULPCOMMAND = CMD_XMIT_SEQUENCE64_CX;
3784 iocb->ULPCONTEXT = ndlp->nlp_Xri;
3785 }
3786
3787 switch (FC_TRAN_CLASS(pkt->pkt_tran_flags)) {

--- 68 unchanged lines hidden (view full) ---

3856 iocb->ULPCOMMAND = CMD_XMIT_ELS_RSP64_CX;
3857 } else {
3858 /* ELS Request */
3859 iocb->un.elsreq64.remoteID = (did == BCAST_DID) ? 0 : did;
3860 iocb->ULPCONTEXT =
3861 (did == BCAST_DID) ? pkt->pkt_cmd_fhdr.seq_id : 0;
3862 iocb->ULPCOMMAND = CMD_ELS_REQUEST64_CR;
3863
3812 } else {
3813 HBASTATS.IpSeqIssued++;
3814
3815 iocb->ULPCOMMAND = CMD_XMIT_SEQUENCE64_CX;
3816 iocb->ULPCONTEXT = ndlp->nlp_Xri;
3817 }
3818
3819 switch (FC_TRAN_CLASS(pkt->pkt_tran_flags)) {

--- 68 unchanged lines hidden (view full) ---

3888 iocb->ULPCOMMAND = CMD_XMIT_ELS_RSP64_CX;
3889 } else {
3890 /* ELS Request */
3891 iocb->un.elsreq64.remoteID = (did == BCAST_DID) ? 0 : did;
3892 iocb->ULPCONTEXT =
3893 (did == BCAST_DID) ? pkt->pkt_cmd_fhdr.seq_id : 0;
3894 iocb->ULPCOMMAND = CMD_ELS_REQUEST64_CR;
3895
3864 if (hba->topology != TOPOLOGY_LOOP) {
3865 cmd = *((uint32_t *)pkt->pkt_cmd);
3866 cmd &= ELS_CMD_MASK;
3896 if (hba->sli_mode == EMLXS_HBA_SLI3_MODE) {
3897 if (hba->topology != TOPOLOGY_LOOP) {
3898 cmd = *((uint32_t *)pkt->pkt_cmd);
3899 cmd &= ELS_CMD_MASK;
3867
3900
3868 if ((cmd == ELS_CMD_FLOGI) || (cmd == ELS_CMD_FDISC)) {
3869 iocb->ULPCT = 0x2;
3870 } else {
3871 iocb->ULPCT = 0x1;
3901 if ((cmd == ELS_CMD_FLOGI) ||
3902 (cmd == ELS_CMD_FDISC)) {
3903 iocb->ULPCT = 0x2;
3904 } else {
3905 iocb->ULPCT = 0x1;
3906 }
3872 }
3907 }
3908 iocb->ULPCONTEXT = port->vpi;
3873 }
3909 }
3874 iocb->ULPCONTEXT = port->vpi;
3875 }
3876 iocb->ULPIOTAG = iotag;
3877 iocb->ULPRSVDBYTE =
3878 ((pkt->pkt_timeout > 0xff) ? 0 : pkt->pkt_timeout);
3879 iocb->ULPOWNER = OWN_CHIP;
3880
3881 switch (FC_TRAN_CLASS(pkt->pkt_tran_flags)) {
3882 case FC_TRAN_CLASS1:

--- 137 unchanged lines hidden (view full) ---

4020 if (resid > 0) {
4021 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
4022 "emlxs_fct_bde_setup: Not enough scatter gather buffers "
4023 " size=%d resid=%d count=%d",
4024 size, resid, count);
4025 return (1);
4026 }
4027
3910 }
3911 iocb->ULPIOTAG = iotag;
3912 iocb->ULPRSVDBYTE =
3913 ((pkt->pkt_timeout > 0xff) ? 0 : pkt->pkt_timeout);
3914 iocb->ULPOWNER = OWN_CHIP;
3915
3916 switch (FC_TRAN_CLASS(pkt->pkt_tran_flags)) {
3917 case FC_TRAN_CLASS1:

--- 137 unchanged lines hidden (view full) ---

4055 if (resid > 0) {
4056 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
4057 "emlxs_fct_bde_setup: Not enough scatter gather buffers "
4058 " size=%d resid=%d count=%d",
4059 size, resid, count);
4060 return (1);
4061 }
4062
4028 if ((hba->sli_mode < 3) || (sgllen > SLI3_MAX_BDE)) {
4063 if ((hba->sli_mode < EMLXS_HBA_SLI3_MODE) ||
4064 (sgllen > SLI3_MAX_BDE)) {
4029 rval = emlxs_sli2_fct_bde_setup(port, sbp);
4030 } else {
4031 rval = emlxs_sli3_fct_bde_setup(port, sbp);
4032 }
4033
4034 return (rval);
4035
4036} /* emlxs_fct_bde_setup() */
4037#endif /* SFCT_SUPPORT */
4038
4039static uint32_t
4040emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4041{
4042 uint32_t rval;
4043 emlxs_hba_t *hba = HBA;
4044
4065 rval = emlxs_sli2_fct_bde_setup(port, sbp);
4066 } else {
4067 rval = emlxs_sli3_fct_bde_setup(port, sbp);
4068 }
4069
4070 return (rval);
4071
4072} /* emlxs_fct_bde_setup() */
4073#endif /* SFCT_SUPPORT */
4074
4075static uint32_t
4076emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4077{
4078 uint32_t rval;
4079 emlxs_hba_t *hba = HBA;
4080
4045 if (hba->sli_mode < 3) {
4081 if (hba->sli_mode < EMLXS_HBA_SLI3_MODE) {
4046 rval = emlxs_sli2_bde_setup(port, sbp);
4047 } else {
4048 rval = emlxs_sli3_bde_setup(port, sbp);
4049 }
4050
4051 return (rval);
4052
4053} /* emlxs_bde_setup() */

--- 178 unchanged lines hidden (view full) ---

4232
4233 return (DDI_INTR_CLAIMED);
4234
4235} /* emlxs_sli3_intx_intr() */
4236
4237
4238/* EMLXS_PORT_LOCK must be held when call this routine */
4239static uint32_t
4082 rval = emlxs_sli2_bde_setup(port, sbp);
4083 } else {
4084 rval = emlxs_sli3_bde_setup(port, sbp);
4085 }
4086
4087 return (rval);
4088
4089} /* emlxs_bde_setup() */

--- 178 unchanged lines hidden (view full) ---

4268
4269 return (DDI_INTR_CLAIMED);
4270
4271} /* emlxs_sli3_intx_intr() */
4272
4273
4274/* EMLXS_PORT_LOCK must be held when call this routine */
4275static uint32_t
4240emlxs_get_attention(emlxs_hba_t *hba, uint32_t msgid)
4276emlxs_get_attention(emlxs_hba_t *hba, int32_t msgid)
4241{
4242#ifdef FMA_SUPPORT
4243 emlxs_port_t *port = &PPORT;
4244#endif /* FMA_SUPPORT */
4245 uint32_t ha_copy = 0;
4246 uint32_t ha_copy2;
4247 uint32_t mask = hba->sli.sli3.hc_copy;
4248

--- 296 unchanged lines hidden (view full) ---

4545
4546 /* Get a buffer which will be used for mailbox commands */
4547 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
4548 /* Get link attention message */
4549 if (emlxs_mb_read_la(hba, mbq) == 0) {
4550 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq,
4551 MBX_NOWAIT, 0);
4552 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
4277{
4278#ifdef FMA_SUPPORT
4279 emlxs_port_t *port = &PPORT;
4280#endif /* FMA_SUPPORT */
4281 uint32_t ha_copy = 0;
4282 uint32_t ha_copy2;
4283 uint32_t mask = hba->sli.sli3.hc_copy;
4284

--- 296 unchanged lines hidden (view full) ---

4581
4582 /* Get a buffer which will be used for mailbox commands */
4583 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
4584 /* Get link attention message */
4585 if (emlxs_mb_read_la(hba, mbq) == 0) {
4586 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq,
4587 MBX_NOWAIT, 0);
4588 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
4553 (void) emlxs_mem_put(hba, MEM_MBOX,
4554 (uint8_t *)mbq);
4589 emlxs_mem_put(hba, MEM_MBOX,
4590 (void *)mbq);
4555 }
4556
4557 mutex_enter(&EMLXS_PORT_LOCK);
4558
4559
4560 /*
4561 * Clear Link Attention in HA REG
4562 */
4563 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_LATT);
4564
4565#ifdef FMA_SUPPORT
4566 /* Access handle validation */
4567 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
4568#endif /* FMA_SUPPORT */
4569
4570 mutex_exit(&EMLXS_PORT_LOCK);
4571 } else {
4591 }
4592
4593 mutex_enter(&EMLXS_PORT_LOCK);
4594
4595
4596 /*
4597 * Clear Link Attention in HA REG
4598 */
4599 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_LATT);
4600
4601#ifdef FMA_SUPPORT
4602 /* Access handle validation */
4603 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
4604#endif /* FMA_SUPPORT */
4605
4606 mutex_exit(&EMLXS_PORT_LOCK);
4607 } else {
4572 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
4608 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
4573 }
4574 }
4575
4576} /* emlxs_sli3_handle_link_event() */
4577
4578
4579/*
4580 * emlxs_sli3_handle_ring_event()

--- 555 unchanged lines hidden (view full) ---

5136 word[4], word[5], word[6], word[7], hba->state, hba->flag);
5137
5138done:
5139
5140 if (hba->flag & FC_HBQ_ENABLED) {
5141 emlxs_update_HBQ_index(hba, hbq_id);
5142 } else {
5143 if (mp) {
4609 }
4610 }
4611
4612} /* emlxs_sli3_handle_link_event() */
4613
4614
4615/*
4616 * emlxs_sli3_handle_ring_event()

--- 555 unchanged lines hidden (view full) ---

5172 word[4], word[5], word[6], word[7], hba->state, hba->flag);
5173
5174done:
5175
5176 if (hba->flag & FC_HBQ_ENABLED) {
5177 emlxs_update_HBQ_index(hba, hbq_id);
5178 } else {
5179 if (mp) {
5144 (void) emlxs_mem_put(hba, buf_type, (uint8_t *)mp);
5180 emlxs_mem_put(hba, buf_type, (void *)mp);
5145 }
5146 (void) emlxs_post_buffer(hba, rp, 1);
5147 }
5148
5149 return (0);
5150
5151} /* emlxs_handle_rcv_seq() */
5152

--- 65 unchanged lines hidden (view full) ---

5218
5219 /*
5220 * After this, the sbp / iocb should not be
5221 * accessed in the xmit path.
5222 */
5223
5224 /* Free the local iocb if there is no sbp tracking it */
5225 if (!sbp) {
5181 }
5182 (void) emlxs_post_buffer(hba, rp, 1);
5183 }
5184
5185 return (0);
5186
5187} /* emlxs_handle_rcv_seq() */
5188

--- 65 unchanged lines hidden (view full) ---

5254
5255 /*
5256 * After this, the sbp / iocb should not be
5257 * accessed in the xmit path.
5258 */
5259
5260 /* Free the local iocb if there is no sbp tracking it */
5261 if (!sbp) {
5226 (void) emlxs_mem_put(hba, MEM_IOCB, (uint8_t *)iocbq);
5262 emlxs_mem_put(hba, MEM_IOCB, (void *)iocbq);
5227 }
5228
5229 /* update local ring index to next available ring index */
5230 rp->fc_cmdidx =
5231 (rp->fc_cmdidx + 1 >= rp->fc_numCiocb) ? 0 : rp->fc_cmdidx + 1;
5232
5233
5234 return;

--- 64 unchanged lines hidden (view full) ---

5299
5300mode_A:
5301
5302 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5303 "Attempting SLIM2 Interlock...");
5304
5305interlock_A:
5306
5263 }
5264
5265 /* update local ring index to next available ring index */
5266 rp->fc_cmdidx =
5267 (rp->fc_cmdidx + 1 >= rp->fc_numCiocb) ? 0 : rp->fc_cmdidx + 1;
5268
5269
5270 return;

--- 64 unchanged lines hidden (view full) ---

5335
5336mode_A:
5337
5338 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5339 "Attempting SLIM2 Interlock...");
5340
5341interlock_A:
5342
5307 value = 0xFFFFFFFF;
5343 value = 0x55555555;
5308 word0 = 0;
5309 swpmb->mbxCommand = MBX_KILL_BOARD;
5310 swpmb->mbxOwner = OWN_CHIP;
5311
5312 /* Write value to SLIM */
5313 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5314 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1)), word0);
5315

--- 15 unchanged lines hidden (view full) ---

5331 /* interrupt board to do it right away */
5332 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5333
5334 /* First wait for command acceptence */
5335 j = 0;
5336 while (j++ < 1000) {
5337 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5338
5344 word0 = 0;
5345 swpmb->mbxCommand = MBX_KILL_BOARD;
5346 swpmb->mbxOwner = OWN_CHIP;
5347
5348 /* Write value to SLIM */
5349 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5350 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1)), word0);
5351

--- 15 unchanged lines hidden (view full) ---

5367 /* interrupt board to do it right away */
5368 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5369
5370 /* First wait for command acceptence */
5371 j = 0;
5372 while (j++ < 1000) {
5373 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5374
5339 if (value == 0) {
5375 if (value == 0xAAAAAAAA) {
5340 break;
5341 }
5342
5343 DELAYUS(50);
5344 }
5345
5376 break;
5377 }
5378
5379 DELAYUS(50);
5380 }
5381
5346 if (value == 0) {
5382 if (value == 0xAAAAAAAA) {
5347 /* Now wait for mailbox ownership to clear */
5348 while (j++ < 10000) {
5349 word0 =
5350 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5351
5352 if (swpmb->mbxOwner == 0) {
5353 break;
5354 }

--- 14 unchanged lines hidden (view full) ---

5369
5370mode_B:
5371
5372 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5373 "Attempting SLIM1 Interlock...");
5374
5375interlock_B:
5376
5383 /* Now wait for mailbox ownership to clear */
5384 while (j++ < 10000) {
5385 word0 =
5386 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5387
5388 if (swpmb->mbxOwner == 0) {
5389 break;
5390 }

--- 14 unchanged lines hidden (view full) ---

5405
5406mode_B:
5407
5408 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5409 "Attempting SLIM1 Interlock...");
5410
5411interlock_B:
5412
5377 value = 0xFFFFFFFF;
5413 value = 0x55555555;
5378 word0 = 0;
5379 swpmb->mbxCommand = MBX_KILL_BOARD;
5380 swpmb->mbxOwner = OWN_CHIP;
5381
5382 /* Write KILL BOARD to mailbox */
5383 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5384 WRITE_SLIM_ADDR(hba, ((volatile uint32_t *)mb1), word0);
5385
5386 /* interrupt board to do it right away */
5387 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5388
5389 /* First wait for command acceptence */
5390 j = 0;
5391 while (j++ < 1000) {
5392 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5393
5414 word0 = 0;
5415 swpmb->mbxCommand = MBX_KILL_BOARD;
5416 swpmb->mbxOwner = OWN_CHIP;
5417
5418 /* Write KILL BOARD to mailbox */
5419 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5420 WRITE_SLIM_ADDR(hba, ((volatile uint32_t *)mb1), word0);
5421
5422 /* interrupt board to do it right away */
5423 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5424
5425 /* First wait for command acceptence */
5426 j = 0;
5427 while (j++ < 1000) {
5428 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5429
5394 if (value == 0) {
5430 if (value == 0xAAAAAAAA) {
5395 break;
5396 }
5397
5398 DELAYUS(50);
5399 }
5400
5431 break;
5432 }
5433
5434 DELAYUS(50);
5435 }
5436
5401 if (value == 0) {
5437 if (value == 0xAAAAAAAA) {
5402 /* Now wait for mailbox ownership to clear */
5403 while (j++ < 10000) {
5404 word0 =
5405 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5406
5407 if (swpmb->mbxOwner == 0) {
5408 break;
5409 }

--- 78 unchanged lines hidden (view full) ---

5488 hba->sli.sli3.hc_copy = 0;
5489 WRITE_CSR_REG(hba, FC_HC_REG(hba), hba->sli.sli3.hc_copy);
5490 WRITE_CSR_REG(hba, FC_HA_REG(hba), 0xffffffff);
5491
5492 mb2 = FC_SLIM2_MAILBOX(hba);
5493 mb1 = FC_SLIM1_MAILBOX(hba);
5494 swpmb = (MAILBOX *)&word0;
5495
5438 /* Now wait for mailbox ownership to clear */
5439 while (j++ < 10000) {
5440 word0 =
5441 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5442
5443 if (swpmb->mbxOwner == 0) {
5444 break;
5445 }

--- 78 unchanged lines hidden (view full) ---

5524 hba->sli.sli3.hc_copy = 0;
5525 WRITE_CSR_REG(hba, FC_HC_REG(hba), hba->sli.sli3.hc_copy);
5526 WRITE_CSR_REG(hba, FC_HA_REG(hba), 0xffffffff);
5527
5528 mb2 = FC_SLIM2_MAILBOX(hba);
5529 mb1 = FC_SLIM1_MAILBOX(hba);
5530 swpmb = (MAILBOX *)&word0;
5531
5496 value = 0xFFFFFFFF;
5532 value = 0x55555555;
5497 word0 = 0;
5498 swpmb->mbxCommand = MBX_KILL_BOARD;
5499 swpmb->mbxOwner = OWN_CHIP;
5500
5501 /* Write value to SLIM */
5502 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5503 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1)), word0);
5504

--- 15 unchanged lines hidden (view full) ---

5520 /* interrupt board to do it right away */
5521 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5522
5523 /* First wait for command acceptence */
5524 j = 0;
5525 while (j++ < 1000) {
5526 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5527
5533 word0 = 0;
5534 swpmb->mbxCommand = MBX_KILL_BOARD;
5535 swpmb->mbxOwner = OWN_CHIP;
5536
5537 /* Write value to SLIM */
5538 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1), value);
5539 WRITE_SLIM_ADDR(hba, (((volatile uint32_t *)mb1)), word0);
5540

--- 15 unchanged lines hidden (view full) ---

5556 /* interrupt board to do it right away */
5557 WRITE_CSR_REG(hba, FC_CA_REG(hba), CA_MBATT);
5558
5559 /* First wait for command acceptence */
5560 j = 0;
5561 while (j++ < 1000) {
5562 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5563
5528 if (value == 0) {
5564 if (value == 0xAAAAAAAA) {
5529 break;
5530 }
5531 DELAYUS(50);
5532 }
5565 break;
5566 }
5567 DELAYUS(50);
5568 }
5533 if (value == 0) {
5569 if (value == 0xAAAAAAAA) {
5534 /* Now wait for mailbox ownership to clear */
5535 while (j++ < 10000) {
5536 word0 =
5537 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5538 if (swpmb->mbxOwner == 0) {
5539 break;
5540 }
5541 DELAYUS(50);

--- 9 unchanged lines hidden (view full) ---

5551 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.slim_acc_handle);
5552 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
5553#endif /* FMA_SUPPORT */
5554 return;
5555
5556} /* emlxs_sli3_hba_kill4quiesce */
5557
5558
5570 /* Now wait for mailbox ownership to clear */
5571 while (j++ < 10000) {
5572 word0 =
5573 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5574 if (swpmb->mbxOwner == 0) {
5575 break;
5576 }
5577 DELAYUS(50);

--- 9 unchanged lines hidden (view full) ---

5587 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.slim_acc_handle);
5588 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
5589#endif /* FMA_SUPPORT */
5590 return;
5591
5592} /* emlxs_sli3_hba_kill4quiesce */
5593
5594
5559static uint32_t
5560emlxs_reset_ring(emlxs_hba_t *hba, uint32_t ringno)
5561{
5562 emlxs_port_t *port = &PPORT;
5563 RING *rp;
5564 MAILBOXQ *mbq;
5565 MAILBOX *mb;
5566 PGP *pgp;
5567 off_t offset;
5568 NODELIST *ndlp;
5569 uint32_t i;
5570 emlxs_port_t *vport;
5571
5595
5572 rp = &hba->sli.sli3.ring[ringno];
5573 pgp =
5574 (PGP *)&((SLIM2 *)hba->sli.sli3.slim2.virt)->mbx.us.s2.port[ringno];
5575
5596
5576 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1)) == 0) {
5577 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_ring_reset_msg,
5578 "%s: Unable to allocate mailbox buffer.",
5579 emlxs_ring_xlate(ringno));
5580
5581 return ((uint32_t)FC_FAILURE);
5582 }
5583 mb = (MAILBOX *)mbq;
5584
5585 emlxs_mb_reset_ring(hba, mbq, ringno);
5586 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
5587 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_ring_reset_msg,
5588 "%s: Unable to reset ring. Mailbox cmd=%x status=%x",
5589 emlxs_ring_xlate(ringno), mb->mbxCommand, mb->mbxStatus);
5590
5591 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
5592 return ((uint32_t)FC_FAILURE);
5593 }
5594
5595 /* Free the mailbox */
5596 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
5597
5598 /* Update the response ring indicies */
5599 offset = (off_t)((uint64_t)((unsigned long)&(pgp->rspPutInx))
5600 - (uint64_t)((unsigned long)hba->sli.sli3.slim2.virt));
5601 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset, 4,
5602 DDI_DMA_SYNC_FORKERNEL);
5603 rp->fc_rspidx = rp->fc_port_rspidx = BE_SWAP32(pgp->rspPutInx);
5604
5605 /* Update the command ring indicies */
5606 offset = (off_t)((uint64_t)((unsigned long)&(pgp->cmdGetInx)) -
5607 (uint64_t)((unsigned long)hba->sli.sli3.slim2.virt));
5608 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset, 4,
5609 DDI_DMA_SYNC_FORKERNEL);
5610 rp->fc_cmdidx = rp->fc_port_cmdidx = BE_SWAP32(pgp->cmdGetInx);
5611
5612 for (i = 0; i < MAX_VPORTS; i++) {
5613 vport = &VPORT(i);
5614
5615 if (!(vport->flag & EMLXS_PORT_BOUND)) {
5616 continue;
5617 }
5618
5619 /* Clear all node XRI contexts */
5620 rw_enter(&vport->node_rwlock, RW_WRITER);
5621 mutex_enter(&EMLXS_TX_CHANNEL_LOCK);
5622 for (i = 0; i < EMLXS_NUM_HASH_QUES; i++) {
5623 ndlp = vport->node_table[i];
5624 while (ndlp != NULL) {
5625 ndlp->nlp_flag[FC_IP_RING] &= ~NLP_RPI_XRI;
5626 ndlp = ndlp->nlp_list_next;
5627 }
5628 }
5629 mutex_exit(&EMLXS_TX_CHANNEL_LOCK);
5630 rw_exit(&vport->node_rwlock);
5631 }
5632
5633 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_ring_reset_msg, "%s",
5634 emlxs_ring_xlate(ringno));
5635
5636#ifdef FMA_SUPPORT
5637 if (emlxs_fm_check_dma_handle(hba, hba->sli.sli3.slim2.dma_handle)
5638 != DDI_FM_OK) {
5639 EMLXS_MSGF(EMLXS_CONTEXT,
5640 &emlxs_invalid_dma_handle_msg,
5641 "emlxs_reset_ring: hdl=%p",
5642 hba->sli.sli3.slim2.dma_handle);
5643
5644 emlxs_thread_spawn(hba, emlxs_restart_thread,
5645 NULL, NULL);
5646
5647 return ((uint32_t)FC_FAILURE);
5648 }
5649#endif /* FMA_SUPPORT */
5650
5651
5652 return (FC_SUCCESS);
5653
5654} /* emlxs_reset_ring() */
5655
5656
5657/*
5658 * emlxs_handle_mb_event
5659 *
5660 * Description: Process a Mailbox Attention.
5661 * Called from host_interrupt to process MBATT
5662 *
5663 * Returns:
5664 *
5665 */
5666static uint32_t
5667emlxs_handle_mb_event(emlxs_hba_t *hba)
5668{
5669 emlxs_port_t *port = &PPORT;
5670 MAILBOX *mb;
5671 MAILBOX *swpmb;
5672 MAILBOX *mbox;
5597/*
5598 * emlxs_handle_mb_event
5599 *
5600 * Description: Process a Mailbox Attention.
5601 * Called from host_interrupt to process MBATT
5602 *
5603 * Returns:
5604 *
5605 */
5606static uint32_t
5607emlxs_handle_mb_event(emlxs_hba_t *hba)
5608{
5609 emlxs_port_t *port = &PPORT;
5610 MAILBOX *mb;
5611 MAILBOX *swpmb;
5612 MAILBOX *mbox;
5673 MAILBOXQ *mbq;
5613 MAILBOXQ *mbq = NULL;
5674 volatile uint32_t word0;
5675 MATCHMAP *mbox_bp;
5676 off_t offset;
5677 uint32_t i;
5678 int rc;
5679
5680 swpmb = (MAILBOX *)&word0;
5681
5614 volatile uint32_t word0;
5615 MATCHMAP *mbox_bp;
5616 off_t offset;
5617 uint32_t i;
5618 int rc;
5619
5620 swpmb = (MAILBOX *)&word0;
5621
5622 mutex_enter(&EMLXS_PORT_LOCK);
5682 switch (hba->mbox_queue_flag) {
5683 case 0:
5684 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_stray_mbox_intr_msg,
5685 "No mailbox active.");
5623 switch (hba->mbox_queue_flag) {
5624 case 0:
5625 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_stray_mbox_intr_msg,
5626 "No mailbox active.");
5627
5628 mutex_exit(&EMLXS_PORT_LOCK);
5686 return (0);
5687
5688 case MBX_POLL:
5689
5690 /* Mark mailbox complete, this should wake up any polling */
5691 /* threads. This can happen if interrupts are enabled while */
5692 /* a polled mailbox command is outstanding. If we don't set */
5693 /* MBQ_COMPLETED here, the polling thread may wait until */
5694 /* timeout error occurs */
5695
5696 mutex_enter(&EMLXS_MBOX_LOCK);
5697 mbq = (MAILBOXQ *)hba->mbox_mbq;
5629 return (0);
5630
5631 case MBX_POLL:
5632
5633 /* Mark mailbox complete, this should wake up any polling */
5634 /* threads. This can happen if interrupts are enabled while */
5635 /* a polled mailbox command is outstanding. If we don't set */
5636 /* MBQ_COMPLETED here, the polling thread may wait until */
5637 /* timeout error occurs */
5638
5639 mutex_enter(&EMLXS_MBOX_LOCK);
5640 mbq = (MAILBOXQ *)hba->mbox_mbq;
5698 mutex_exit(&EMLXS_MBOX_LOCK);
5699 if (mbq) {
5641 if (mbq) {
5642 port = (emlxs_port_t *)mbq->port;
5700 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,
5701 "Mailbox event. Completing Polled command.");
5702 mbq->flag |= MBQ_COMPLETED;
5703 }
5643 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,
5644 "Mailbox event. Completing Polled command.");
5645 mbq->flag |= MBQ_COMPLETED;
5646 }
5647 mutex_exit(&EMLXS_MBOX_LOCK);
5704
5648
5649 mutex_exit(&EMLXS_PORT_LOCK);
5705 return (0);
5706
5707 case MBX_SLEEP:
5708 case MBX_NOWAIT:
5650 return (0);
5651
5652 case MBX_SLEEP:
5653 case MBX_NOWAIT:
5709 mutex_enter(&EMLXS_MBOX_LOCK);
5710 mbq = (MAILBOXQ *)hba->mbox_mbq;
5654 /* Check mbox_timer, it acts as a service flag too */
5655 /* The first to service the mbox queue will clear the timer */
5656 if (hba->mbox_timer) {
5657 hba->mbox_timer = 0;
5658
5659 mutex_enter(&EMLXS_MBOX_LOCK);
5660 mbq = (MAILBOXQ *)hba->mbox_mbq;
5661 mutex_exit(&EMLXS_MBOX_LOCK);
5662 }
5663
5664 if (!mbq) {
5665 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,
5666 "Mailbox event. No service required.");
5667 mutex_exit(&EMLXS_PORT_LOCK);
5668 return (0);
5669 }
5670
5711 mb = (MAILBOX *)mbq;
5671 mb = (MAILBOX *)mbq;
5712 mutex_exit(&EMLXS_MBOX_LOCK);
5672 mutex_exit(&EMLXS_PORT_LOCK);
5713 break;
5714
5715 default:
5716 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_completion_error_msg,
5717 "Invalid Mailbox flag (%x).");
5673 break;
5674
5675 default:
5676 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_completion_error_msg,
5677 "Invalid Mailbox flag (%x).");
5678
5679 mutex_exit(&EMLXS_PORT_LOCK);
5718 return (0);
5719 }
5720
5680 return (0);
5681 }
5682
5683 /* Set port context */
5684 port = (emlxs_port_t *)mbq->port;
5685
5721 /* Get first word of mailbox */
5722 if (hba->flag & FC_SLIM2_MODE) {
5723 mbox = FC_SLIM2_MAILBOX(hba);
5724 offset = (off_t)((uint64_t)((unsigned long)mbox)
5725 - (uint64_t)((unsigned long)hba->sli.sli3.slim2.virt));
5726
5727 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
5728 sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);

--- 20 unchanged lines hidden (view full) ---

5749 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
5750 offset, sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);
5751 word0 = *((volatile uint32_t *)mbox);
5752 word0 = BE_SWAP32(word0);
5753 } else {
5754 word0 =
5755 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mbox));
5756 }
5686 /* Get first word of mailbox */
5687 if (hba->flag & FC_SLIM2_MODE) {
5688 mbox = FC_SLIM2_MAILBOX(hba);
5689 offset = (off_t)((uint64_t)((unsigned long)mbox)
5690 - (uint64_t)((unsigned long)hba->sli.sli3.slim2.virt));
5691
5692 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
5693 sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);

--- 20 unchanged lines hidden (view full) ---

5714 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
5715 offset, sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);
5716 word0 = *((volatile uint32_t *)mbox);
5717 word0 = BE_SWAP32(word0);
5718 } else {
5719 word0 =
5720 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mbox));
5721 }
5757 }
5722 }
5758
5759 /* Now that we are the owner, DMA Sync entire mailbox if needed */
5760 if (hba->flag & FC_SLIM2_MODE) {
5761 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
5762 MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORKERNEL);
5763
5764 BE_SWAP32_BCOPY((uint8_t *)mbox, (uint8_t *)mb,
5765 MAILBOX_CMD_BSIZE);

--- 84 unchanged lines hidden (view full) ---

5850 /* Clean up the mailbox area */
5851 emlxs_mb_fini(hba, mb, mb->mbxStatus);
5852
5853 mbq = (MAILBOXQ *)emlxs_mb_get(hba);
5854 if (mbq) {
5855 /* Attempt to send pending mailboxes */
5856 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
5857 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
5723
5724 /* Now that we are the owner, DMA Sync entire mailbox if needed */
5725 if (hba->flag & FC_SLIM2_MODE) {
5726 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
5727 MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORKERNEL);
5728
5729 BE_SWAP32_BCOPY((uint8_t *)mbox, (uint8_t *)mb,
5730 MAILBOX_CMD_BSIZE);

--- 84 unchanged lines hidden (view full) ---

5815 /* Clean up the mailbox area */
5816 emlxs_mb_fini(hba, mb, mb->mbxStatus);
5817
5818 mbq = (MAILBOXQ *)emlxs_mb_get(hba);
5819 if (mbq) {
5820 /* Attempt to send pending mailboxes */
5821 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
5822 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
5858 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
5823 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
5859 }
5860 }
5861 return (0);
5862
5863} /* emlxs_handle_mb_event() */
5864
5865
5866extern void

--- 22 unchanged lines hidden (view full) ---

5889
5890 mutex_enter(&EMLXS_PORT_LOCK);
5891
5892 /* Return if timer hasn't expired */
5893 if (!hba->mbox_timer || (hba->timer_tics < hba->mbox_timer)) {
5894 mutex_exit(&EMLXS_PORT_LOCK);
5895 return;
5896 }
5824 }
5825 }
5826 return (0);
5827
5828} /* emlxs_handle_mb_event() */
5829
5830
5831extern void

--- 22 unchanged lines hidden (view full) ---

5854
5855 mutex_enter(&EMLXS_PORT_LOCK);
5856
5857 /* Return if timer hasn't expired */
5858 if (!hba->mbox_timer || (hba->timer_tics < hba->mbox_timer)) {
5859 mutex_exit(&EMLXS_PORT_LOCK);
5860 return;
5861 }
5897 hba->mbox_timer = 0;
5898
5899 /* Mailbox timed out, first check for error attention */
5900 ha_copy = emlxs_check_attention(hba);
5901
5902 if (ha_copy & HA_ERATT) {
5862
5863 /* Mailbox timed out, first check for error attention */
5864 ha_copy = emlxs_check_attention(hba);
5865
5866 if (ha_copy & HA_ERATT) {
5867 hba->mbox_timer = 0;
5903 mutex_exit(&EMLXS_PORT_LOCK);
5904 emlxs_handle_ff_error(hba);
5905 return;
5906 }
5907
5908 if (hba->mbox_queue_flag) {
5909 /* Get first word of mailbox */
5910 if (hba->flag & FC_SLIM2_MODE) {

--- 32 unchanged lines hidden (view full) ---

5943
5944 mutex_exit(&EMLXS_PORT_LOCK);
5945
5946 (void) emlxs_handle_mb_event(hba);
5947
5948 return;
5949 }
5950
5868 mutex_exit(&EMLXS_PORT_LOCK);
5869 emlxs_handle_ff_error(hba);
5870 return;
5871 }
5872
5873 if (hba->mbox_queue_flag) {
5874 /* Get first word of mailbox */
5875 if (hba->flag & FC_SLIM2_MODE) {

--- 32 unchanged lines hidden (view full) ---

5908
5909 mutex_exit(&EMLXS_PORT_LOCK);
5910
5911 (void) emlxs_handle_mb_event(hba);
5912
5913 return;
5914 }
5915
5951 if (hba->mbox_mbq) {
5952 mb = (MAILBOX *)hba->mbox_mbq;
5953 }
5916 /* The first to service the mbox queue will clear the timer */
5917 /* We will service the mailbox here */
5918 hba->mbox_timer = 0;
5919
5920 mutex_enter(&EMLXS_MBOX_LOCK);
5921 mb = (MAILBOX *)hba->mbox_mbq;
5922 mutex_exit(&EMLXS_MBOX_LOCK);
5954 }
5955
5956 if (mb) {
5957 switch (hba->mbox_queue_flag) {
5958 case MBX_NOWAIT:
5959 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_timeout_msg,
5960 "%s: Nowait.",
5961 emlxs_mb_cmd_xlate(mb->mbxCommand));

--- 318 unchanged lines hidden (view full) ---

6280 return (1);
6281 }
6282 mb = (MAILBOX *)mbq;
6283
6284 /* Allocate HBQ Host buffer and Initialize the HBQEs */
6285 if (emlxs_hbq_alloc(hba, hbq_id)) {
6286 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6287 "emlxs_hbq_setup: Unable to allocate HBQ.");
5923 }
5924
5925 if (mb) {
5926 switch (hba->mbox_queue_flag) {
5927 case MBX_NOWAIT:
5928 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_timeout_msg,
5929 "%s: Nowait.",
5930 emlxs_mb_cmd_xlate(mb->mbxCommand));

--- 318 unchanged lines hidden (view full) ---

6249 return (1);
6250 }
6251 mb = (MAILBOX *)mbq;
6252
6253 /* Allocate HBQ Host buffer and Initialize the HBQEs */
6254 if (emlxs_hbq_alloc(hba, hbq_id)) {
6255 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6256 "emlxs_hbq_setup: Unable to allocate HBQ.");
6288 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
6257 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6289 return (1);
6290 }
6291
6292 hbq->HBQ_recvNotify = 1;
6293 hbq->HBQ_num_mask = 0; /* Bind to ring */
6294 hbq->HBQ_profile = 0; /* Selection profile */
6295 /* 0=all, 7=logentry */
6296 hbq->HBQ_ringMask = 1 << ringno; /* b0100 * ringno - Binds */

--- 39 unchanged lines hidden (view full) ---

6336
6337 /* Issue CONFIG_HBQ */
6338 emlxs_mb_config_hbq(hba, mbq, hbq_id);
6339 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
6340 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
6341 "emlxs_hbq_setup: Unable to config HBQ. cmd=%x status=%x",
6342 mb->mbxCommand, mb->mbxStatus);
6343
6258 return (1);
6259 }
6260
6261 hbq->HBQ_recvNotify = 1;
6262 hbq->HBQ_num_mask = 0; /* Bind to ring */
6263 hbq->HBQ_profile = 0; /* Selection profile */
6264 /* 0=all, 7=logentry */
6265 hbq->HBQ_ringMask = 1 << ringno; /* b0100 * ringno - Binds */

--- 39 unchanged lines hidden (view full) ---

6305
6306 /* Issue CONFIG_HBQ */
6307 emlxs_mb_config_hbq(hba, mbq, hbq_id);
6308 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
6309 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
6310 "emlxs_hbq_setup: Unable to config HBQ. cmd=%x status=%x",
6311 mb->mbxCommand, mb->mbxStatus);
6312
6344 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
6313 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6345 emlxs_hbq_free_all(hba, hbq_id);
6346 return (1);
6347 }
6348
6349 /* Setup HBQ Get/Put indexes */
6350 ioa2 = (void *)((char *)hba->sli.sli3.slim_addr +
6351 (hba->sli.sli3.hgp_hbq_offset + (hbq_id * sizeof (uint32_t))));
6352 WRITE_SLIM_ADDR(hba, (volatile uint32_t *)ioa2, hbq->HBQ_PutIdx);
6353
6354 hba->sli.sli3.hbq_count++;
6355
6314 emlxs_hbq_free_all(hba, hbq_id);
6315 return (1);
6316 }
6317
6318 /* Setup HBQ Get/Put indexes */
6319 ioa2 = (void *)((char *)hba->sli.sli3.slim_addr +
6320 (hba->sli.sli3.hgp_hbq_offset + (hbq_id * sizeof (uint32_t))));
6321 WRITE_SLIM_ADDR(hba, (volatile uint32_t *)ioa2, hbq->HBQ_PutIdx);
6322
6323 hba->sli.sli3.hbq_count++;
6324
6356 (void) emlxs_mem_put(hba, MEM_MBOX, (uint8_t *)mbq);
6325 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6357
6358#ifdef FMA_SUPPORT
6359 /* Access handle validation */
6360 if (emlxs_fm_check_acc_handle(hba, hba->sli.sli3.slim_acc_handle)
6361 != DDI_FM_OK) {
6362 EMLXS_MSGF(EMLXS_CONTEXT,
6363 &emlxs_invalid_access_handle_msg, NULL);
6364 emlxs_hbq_free_all(hba, hbq_id);

--- 42 unchanged lines hidden (view full) ---

6407 return;
6408 }
6409
6410
6411 hbq = &hba->sli.sli3.hbq_table[hbq_id];
6412
6413 if (hbq->HBQ_host_buf.virt != 0) {
6414 for (j = 0; j < hbq->HBQ_PostBufCnt; j++) {
6326
6327#ifdef FMA_SUPPORT
6328 /* Access handle validation */
6329 if (emlxs_fm_check_acc_handle(hba, hba->sli.sli3.slim_acc_handle)
6330 != DDI_FM_OK) {
6331 EMLXS_MSGF(EMLXS_CONTEXT,
6332 &emlxs_invalid_access_handle_msg, NULL);
6333 emlxs_hbq_free_all(hba, hbq_id);

--- 42 unchanged lines hidden (view full) ---

6376 return;
6377 }
6378
6379
6380 hbq = &hba->sli.sli3.hbq_table[hbq_id];
6381
6382 if (hbq->HBQ_host_buf.virt != 0) {
6383 for (j = 0; j < hbq->HBQ_PostBufCnt; j++) {
6415 (void) emlxs_mem_put(hba, seg,
6416 (uint8_t *)hbq->HBQ_PostBufs[j]);
6384 emlxs_mem_put(hba, seg,
6385 (void *)hbq->HBQ_PostBufs[j]);
6417 hbq->HBQ_PostBufs[j] = NULL;
6418 }
6419 hbq->HBQ_PostBufCnt = 0;
6420
6421 buf_info = &bufinfo;
6422 bzero(buf_info, sizeof (MBUF_INFO));
6423
6424 buf_info->size = hbq->HBQ_host_buf.size;

--- 185 unchanged lines hidden --- 		6386 hbq->HBQ_PostBufs[j] = NULL;
6387 }
6388 hbq->HBQ_PostBufCnt = 0;
6389
6390 buf_info = &bufinfo;
6391 bzero(buf_info, sizeof (MBUF_INFO));
6392
6393 buf_info->size = hbq->HBQ_host_buf.size;

--- 185 unchanged lines hidden ---