| t4_regs_values.h (de483253) | t4_regs_values.h (3dde7c95) |
|---|---|
| 1/* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12/* | 1/* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12/* |
| 13 * This file is part of the Chelsio T4 support code. | 13 * This file is part of the Chelsio T4/T5/T6 support code. |
| 14 * | 14 * |
| 15 * Copyright (C) 2003-2013 Chelsio Communications. All rights reserved. | 15 * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved. |
| 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23#ifndef __T4_REGS_VALUES_H__ | 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23#ifndef __T4_REGS_VALUES_H__ |
| 24#define __T4_REGS_VALUES_H__ | 24#define __T4_REGS_VALUES_H__ |
| 25 26/* 27 * This file contains definitions for various T4 register value hardware 28 * constants. The types of values encoded here are predominantly those for 29 * register fields which control "modal" behavior. For the most part, we do 30 * not include definitions for register fields which are simple numeric 31 * metrics, etc. 32 * --- 13 unchanged lines hidden (view full) --- 46 * ================ 47 */ 48 49/* 50 * SGE register field values. 51 */ 52 53/* CONTROL register */ | 25 26/* 27 * This file contains definitions for various T4 register value hardware 28 * constants. The types of values encoded here are predominantly those for 29 * register fields which control "modal" behavior. For the most part, we do 30 * not include definitions for register fields which are simple numeric 31 * metrics, etc. 32 * --- 13 unchanged lines hidden (view full) --- 46 * ================ 47 */ 48 49/* 50 * SGE register field values. 51 */ 52 53/* CONTROL register */ |
| 54#define X_FLSPLITMODE_FLSPLITMIN 0 55#define X_FLSPLITMODE_ETHHDR 1 56#define X_FLSPLITMODE_IPHDR 2 57#define X_FLSPLITMODE_TCPHDR 3 | 54#define X_FLSPLITMODE_FLSPLITMIN 0 55#define X_FLSPLITMODE_ETHHDR 1 56#define X_FLSPLITMODE_IPHDR 2 57#define X_FLSPLITMODE_TCPHDR 3 |
| 58 | 58 |
| 59#define X_DCASYSTYPE_FSB 0 60#define X_DCASYSTYPE_CSI 1 | 59#define X_DCASYSTYPE_FSB 0 60#define X_DCASYSTYPE_CSI 1 |
| 61 | 61 |
| 62#define X_EGSTATPAGESIZE_64B 0 63#define X_EGSTATPAGESIZE_128B 1 | 62#define X_EGSTATPAGESIZE_64B 0 63#define X_EGSTATPAGESIZE_128B 1 |
| 64 | 64 |
| 65#define X_RXPKTCPLMODE_DATA 0 66#define X_RXPKTCPLMODE_SPLIT 1 | 65#define X_RXPKTCPLMODE_DATA 0 66#define X_RXPKTCPLMODE_SPLIT 1 |
| 67 | 67 |
| 68#define X_INGPCIEBOUNDARY_SHIFT 5 69#define X_INGPCIEBOUNDARY_32B 0 70#define X_INGPCIEBOUNDARY_64B 1 71#define X_INGPCIEBOUNDARY_128B 2 72#define X_INGPCIEBOUNDARY_256B 3 73#define X_INGPCIEBOUNDARY_512B 4 74#define X_INGPCIEBOUNDARY_1024B 5 75#define X_INGPCIEBOUNDARY_2048B 6 76#define X_INGPCIEBOUNDARY_4096B 7 | 68#define X_INGPCIEBOUNDARY_SHIFT 5 69#define X_INGPCIEBOUNDARY_32B 0 70#define X_INGPCIEBOUNDARY_64B 1 71#define X_INGPCIEBOUNDARY_128B 2 72#define X_INGPCIEBOUNDARY_256B 3 73#define X_INGPCIEBOUNDARY_512B 4 74#define X_INGPCIEBOUNDARY_1024B 5 75#define X_INGPCIEBOUNDARY_2048B 6 76#define X_INGPCIEBOUNDARY_4096B 7 |
| 77 | 77 |
| 78#define X_INGPADBOUNDARY_SHIFT 5 79#define X_INGPADBOUNDARY_32B 0 80#define X_INGPADBOUNDARY_64B 1 81#define X_INGPADBOUNDARY_128B 2 82#define X_INGPADBOUNDARY_256B 3 83#define X_INGPADBOUNDARY_512B 4 84#define X_INGPADBOUNDARY_1024B 5 85#define X_INGPADBOUNDARY_2048B 6 86#define X_INGPADBOUNDARY_4096B 7 | 78#define X_T6_INGPADBOUNDARY_SHIFT 3 79#define X_T6_INGPADBOUNDARY_8B 0 80#define X_T6_INGPADBOUNDARY_16B 1 81#define X_T6_INGPADBOUNDARY_32B 2 82#define X_T6_INGPADBOUNDARY_64B 3 83#define X_T6_INGPADBOUNDARY_128B 4 84#define X_T6_INGPADBOUNDARY_256B 5 85#define X_T6_INGPADBOUNDARY_512B 6 86#define X_T6_INGPADBOUNDARY_1024B 7 |
| 87 | 87 |
| 88#define X_EGRPCIEBOUNDARY_SHIFT 5 89#define X_EGRPCIEBOUNDARY_32B 0 90#define X_EGRPCIEBOUNDARY_64B 1 91#define X_EGRPCIEBOUNDARY_128B 2 92#define X_EGRPCIEBOUNDARY_256B 3 93#define X_EGRPCIEBOUNDARY_512B 4 94#define X_EGRPCIEBOUNDARY_1024B 5 95#define X_EGRPCIEBOUNDARY_2048B 6 96#define X_EGRPCIEBOUNDARY_4096B 7 | 88#define X_INGPADBOUNDARY_SHIFT 5 89#define X_INGPADBOUNDARY_32B 0 90#define X_INGPADBOUNDARY_64B 1 91#define X_INGPADBOUNDARY_128B 2 92#define X_INGPADBOUNDARY_256B 3 93#define X_INGPADBOUNDARY_512B 4 94#define X_INGPADBOUNDARY_1024B 5 95#define X_INGPADBOUNDARY_2048B 6 96#define X_INGPADBOUNDARY_4096B 7 |
| 97 | 97 |
| 98#define X_EGRPCIEBOUNDARY_SHIFT 5 99#define X_EGRPCIEBOUNDARY_32B 0 100#define X_EGRPCIEBOUNDARY_64B 1 101#define X_EGRPCIEBOUNDARY_128B 2 102#define X_EGRPCIEBOUNDARY_256B 3 103#define X_EGRPCIEBOUNDARY_512B 4 104#define X_EGRPCIEBOUNDARY_1024B 5 105#define X_EGRPCIEBOUNDARY_2048B 6 106#define X_EGRPCIEBOUNDARY_4096B 7 107 108/* CONTROL2 register */ 109#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ... 110#define X_INGPACKBOUNDARY_16B 0 // Note weird value! 111#define X_INGPACKBOUNDARY_64B 1 112#define X_INGPACKBOUNDARY_128B 2 113#define X_INGPACKBOUNDARY_256B 3 114#define X_INGPACKBOUNDARY_512B 4 115#define X_INGPACKBOUNDARY_1024B 5 116#define X_INGPACKBOUNDARY_2048B 6 117#define X_INGPACKBOUNDARY_4096B 7 118 |
|
| 98/* GTS register */ | 119/* GTS register */ |
| 99#define SGE_TIMERREGS 6 100#define X_TIMERREG_COUNTER0 0 101#define X_TIMERREG_COUNTER1 1 102#define X_TIMERREG_COUNTER2 2 103#define X_TIMERREG_COUNTER3 3 104#define X_TIMERREG_COUNTER4 4 105#define X_TIMERREG_COUNTER5 5 106#define X_TIMERREG_RESTART_COUNTER 6 107#define X_TIMERREG_UPDATE_CIDX 7 | 120#define SGE_TIMERREGS 6 121#define X_TIMERREG_COUNTER0 0 122#define X_TIMERREG_COUNTER1 1 123#define X_TIMERREG_COUNTER2 2 124#define X_TIMERREG_COUNTER3 3 125#define X_TIMERREG_COUNTER4 4 126#define X_TIMERREG_COUNTER5 5 127#define X_TIMERREG_RESTART_COUNTER 6 128#define X_TIMERREG_UPDATE_CIDX 7 |
| 108 109/* 110 * Egress Context field values 111 */ | 129 130/* 131 * Egress Context field values 132 */ |
| 112#define EC_WR_UNITS 16 | 133#define EC_WR_UNITS 16 |
| 113 | 134 |
| 114#define X_FETCHBURSTMIN_SHIFT 4 115#define X_FETCHBURSTMIN_16B 0 116#define X_FETCHBURSTMIN_32B 1 117#define X_FETCHBURSTMIN_64B 2 118#define X_FETCHBURSTMIN_128B 3 | 135#define X_FETCHBURSTMIN_SHIFT 4 136#define X_FETCHBURSTMIN_16B 0 137#define X_FETCHBURSTMIN_32B 1 138#define X_FETCHBURSTMIN_64B 2 139#define X_FETCHBURSTMIN_128B 3 |
| 119 | 140 |
| 120#define X_FETCHBURSTMAX_SHIFT 6 121#define X_FETCHBURSTMAX_64B 0 122#define X_FETCHBURSTMAX_128B 1 123#define X_FETCHBURSTMAX_256B 2 124#define X_FETCHBURSTMAX_512B 3 | 141#define X_FETCHBURSTMAX_SHIFT 6 142#define X_FETCHBURSTMAX_64B 0 143#define X_FETCHBURSTMAX_128B 1 144#define X_FETCHBURSTMAX_256B 2 145#define X_FETCHBURSTMAX_512B 3 |
| 125 | 146 |
| 126#define X_HOSTFCMODE_NONE 0 127#define X_HOSTFCMODE_INGRESS_QUEUE 1 128#define X_HOSTFCMODE_STATUS_PAGE 2 129#define X_HOSTFCMODE_BOTH 3 | 147#define X_HOSTFCMODE_NONE 0 148#define X_HOSTFCMODE_INGRESS_QUEUE 1 149#define X_HOSTFCMODE_STATUS_PAGE 2 150#define X_HOSTFCMODE_BOTH 3 |
| 130 | 151 |
| 131#define X_HOSTFCOWNER_UP 0 132#define X_HOSTFCOWNER_SGE 1 | 152#define X_HOSTFCOWNER_UP 0 153#define X_HOSTFCOWNER_SGE 1 |
| 133 | 154 |
| 134#define X_CIDXFLUSHTHRESH_1 0 135#define X_CIDXFLUSHTHRESH_2 1 136#define X_CIDXFLUSHTHRESH_4 2 137#define X_CIDXFLUSHTHRESH_8 3 138#define X_CIDXFLUSHTHRESH_16 4 139#define X_CIDXFLUSHTHRESH_32 5 140#define X_CIDXFLUSHTHRESH_64 6 141#define X_CIDXFLUSHTHRESH_128 7 | 155#define X_CIDXFLUSHTHRESH_1 0 156#define X_CIDXFLUSHTHRESH_2 1 157#define X_CIDXFLUSHTHRESH_4 2 158#define X_CIDXFLUSHTHRESH_8 3 159#define X_CIDXFLUSHTHRESH_16 4 160#define X_CIDXFLUSHTHRESH_32 5 161#define X_CIDXFLUSHTHRESH_64 6 162#define X_CIDXFLUSHTHRESH_128 7 |
| 142 | 163 |
| 143#define X_IDXSIZE_UNIT 64 | 164#define X_IDXSIZE_UNIT 64 |
| 144 | 165 |
| 145#define X_BASEADDRESS_ALIGN 512 | 166#define X_BASEADDRESS_ALIGN 512 |
| 146 147/* 148 * Ingress Context field values 149 */ | 167 168/* 169 * Ingress Context field values 170 */ |
| 150#define X_UPDATESCHEDULING_TIMER 0 151#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 | 171#define X_UPDATESCHEDULING_TIMER 0 172#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 |
| 152 | 173 |
| 153#define X_UPDATEDELIVERY_NONE 0 154#define X_UPDATEDELIVERY_INTERRUPT 1 155#define X_UPDATEDELIVERY_STATUS_PAGE 2 156#define X_UPDATEDELIVERY_BOTH 3 | 174#define X_UPDATEDELIVERY_NONE 0 175#define X_UPDATEDELIVERY_INTERRUPT 1 176#define X_UPDATEDELIVERY_STATUS_PAGE 2 177#define X_UPDATEDELIVERY_BOTH 3 |
| 157 | 178 |
| 158#define X_INTERRUPTDESTINATION_PCIE 0 159#define X_INTERRUPTDESTINATION_IQ 1 | 179#define X_INTERRUPTDESTINATION_PCIE 0 180#define X_INTERRUPTDESTINATION_IQ 1 |
| 160 | 181 |
| 161#define X_QUEUEENTRYSIZE_16B 0 162#define X_QUEUEENTRYSIZE_32B 1 163#define X_QUEUEENTRYSIZE_64B 2 164#define X_QUEUEENTRYSIZE_128B 3 | 182#define X_QUEUEENTRYSIZE_16B 0 183#define X_QUEUEENTRYSIZE_32B 1 184#define X_QUEUEENTRYSIZE_64B 2 185#define X_QUEUEENTRYSIZE_128B 3 |
| 165 | 186 |
| 166#define IC_SIZE_UNIT 16 167#define IC_BASEADDRESS_ALIGN 512 | 187#define IC_SIZE_UNIT 16 188#define IC_BASEADDRESS_ALIGN 512 |
| 168 | 189 |
| 169#define X_RSPD_TYPE_FLBUF 0 170#define X_RSPD_TYPE_CPL 1 171#define X_RSPD_TYPE_INTR 2 | 190#define X_RSPD_TYPE_FLBUF 0 191#define X_RSPD_TYPE_CPL 1 192#define X_RSPD_TYPE_INTR 2 |
| 172 173/* | 193 194/* |
| 195 * Context field definitions. This is by no means a complete list of SGE 196 * Context fields. In the vast majority of cases the firmware initializes 197 * things the way they need to be set up. But in a few small cases, we need 198 * to compute new values and ship them off to the firmware to be applied to 199 * the SGE Conexts ... 200 */ 201 202/* 203 * Congestion Manager Definitions. 204 */ 205#define S_CONMCTXT_CNGTPMODE 19 206#define M_CONMCTXT_CNGTPMODE 0x3 207#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE) 208#define G_CONMCTXT_CNGTPMODE(x) \ 209 (((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE) 210#define S_CONMCTXT_CNGCHMAP 0 211#define M_CONMCTXT_CNGCHMAP 0xffff 212#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP) 213#define G_CONMCTXT_CNGCHMAP(x) \ 214 (((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP) 215 216#define X_CONMCTXT_CNGTPMODE_DISABLE 0 217#define X_CONMCTXT_CNGTPMODE_QUEUE 1 218#define X_CONMCTXT_CNGTPMODE_CHANNEL 2 219#define X_CONMCTXT_CNGTPMODE_BOTH 3 220 221/* 222 * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 223 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 224 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 225 * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues, 226 * we have a Going To Sleep register at offsets 8x+4. 227 * 228 * As noted above, we have many instances of the Simple Doorbell and Going To 229 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 230 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 231 * avoid buffering of the writes to the Simple Doorbell and we want to use a 232 * non-contiguous offset for the Going To Sleep writes in order to avoid 233 * possible combining between them. 234 */ 235#define SGE_UDB_SIZE 128 236#define SGE_UDB_KDOORBELL 8 237#define SGE_UDB_GTS 20 238#define SGE_UDB_WCDOORBELL 64 239 240/* |
|
| 174 * CIM definitions. 175 * ================ 176 */ 177 178/* 179 * CIM register field values. 180 */ | 241 * CIM definitions. 242 * ================ 243 */ 244 245/* 246 * CIM register field values. 247 */ |
| 181#define X_MBOWNER_NONE 0 182#define X_MBOWNER_FW 1 183#define X_MBOWNER_PL 2 | 248#define X_MBOWNER_NONE 0 249#define X_MBOWNER_FW 1 250#define X_MBOWNER_PL 2 251#define X_MBOWNER_FW_DEFERRED 3 |
| 184 185/* 186 * PCI-E definitions. 187 * ================== 188 */ 189 190#define X_WINDOW_SHIFT 10 191#define X_PCIEOFST_SHIFT 10 --- 4 unchanged lines hidden (view full) --- 196 */ 197 198/* 199 * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 200 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 201 * selects for a particular field being present. These fields, when present 202 * in the Compressed Filter Tuple, have the following widths in bits. 203 */ | 252 253/* 254 * PCI-E definitions. 255 * ================== 256 */ 257 258#define X_WINDOW_SHIFT 10 259#define X_PCIEOFST_SHIFT 10 --- 4 unchanged lines hidden (view full) --- 264 */ 265 266/* 267 * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 268 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 269 * selects for a particular field being present. These fields, when present 270 * in the Compressed Filter Tuple, have the following widths in bits. 271 */ |
| 272#define S_FT_FIRST S_FCOE 273#define S_FT_LAST S_FRAGMENTATION 274 |
|
| 204#define W_FT_FCOE 1 205#define W_FT_PORT 3 206#define W_FT_VNIC_ID 17 207#define W_FT_VLAN 17 208#define W_FT_TOS 8 209#define W_FT_PROTOCOL 8 210#define W_FT_ETHERTYPE 16 211#define W_FT_MACMATCH 9 --- 18 unchanged lines hidden (view full) --- 230#define M_FT_VNID_ID_PF 0x7U 231#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 232#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 233 234#define S_FT_VNID_ID_VLD 16 235#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 236#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 237 | 275#define W_FT_FCOE 1 276#define W_FT_PORT 3 277#define W_FT_VNIC_ID 17 278#define W_FT_VLAN 17 279#define W_FT_TOS 8 280#define W_FT_PROTOCOL 8 281#define W_FT_ETHERTYPE 16 282#define W_FT_MACMATCH 9 --- 18 unchanged lines hidden (view full) --- 301#define M_FT_VNID_ID_PF 0x7U 302#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 303#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 304 305#define S_FT_VNID_ID_VLD 16 306#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 307#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 308 |
| 238 | |
| 239#endif /* __T4_REGS_VALUES_H__ */ | 309#endif /* __T4_REGS_VALUES_H__ */ |