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<  * This file is part of the Chelsio T4 Ethernet driver.
---
>  * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
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<  * Copyright (C) 2009-2013 Chelsio Communications.  All rights reserved.
---
>  * Copyright (C) 2009-2017 Chelsio Communications.  All rights reserved.
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< #ifndef __CXGBE_T4_HW_H
< #define	__CXGBE_T4_HW_H
---
> #ifndef __T4_HW_H
> #define __T4_HW_H
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< 	NCHAN		= 4,	/* # of HW channels */
< 	MAX_MTU		= 9600,	/* max MAC MTU, excluding header + FCS */
< 	EEPROMSIZE	= 17408,/* Serial EEPROM physical size */
< 	EEPROMVSIZE	= 32768,/* Serial EEPROM virtual address space size */
< 	EEPROMPFSIZE	= 1024,	/* EEPROM writable area size for PFn, n>0 */
< 	RSS_NENTRIES	= 2048,	/* # of entries in RSS mapping table */
< 	TCB_SIZE	= 128,	/* TCB size */
< 	NMTUS		= 16,	/* size of MTU table */
< 	NCCTRL_WIN	= 32,	/* # of congestion control windows */
< 	NTX_SCHED	= 8,	/* # of HW Tx scheduling queues */
< 	PM_NSTATS	= 5,	/* # of PM stats */
< 	MBOX_LEN	= 64,	/* mailbox size in bytes */
< 	TRACE_LEN	= 112,	/* length of trace data and mask */
< 	FILTER_OPT_LEN	= 36,	/* filter tuple width of optional components */
< 	NWOL_PAT	= 8,	/* # of WoL patterns */
< 	WOL_PAT_LEN	= 128,	/* length of WoL patterns */
< 	UDBS_SEG_SIZE	= 128,	/* Segment size of BAR2 doorbells */
< 	UDBS_SEG_SHIFT	= 7,	/* log2(UDBS_SEG_SIZE) */
< 	UDBS_DB_OFFSET	= 8,	/* offset of the 4B doorbell in a segment */
< 	UDBS_WR_OFFSET	= 64,	/* offset of the work request in a segment */
---
> 	NCHAN           = 4,     /* # of HW channels */
> 	MAX_MTU         = 9600,  /* max MAC MTU, excluding header + FCS */
> 	EEPROMSIZE      = 17408, /* Serial EEPROM physical size */
> 	EEPROMVSIZE     = 32768, /* Serial EEPROM virtual address space size */
> 	EEPROMPFSIZE    = 1024,  /* EEPROM writable area size for PFn, n>0 */
> 	RSS_NENTRIES    = 2048,  /* # of entries in RSS mapping table */
> 	TCB_SIZE        = 128,   /* TCB size */
> 	NMTUS           = 16,    /* size of MTU table */
> 	NCCTRL_WIN      = 32,    /* # of congestion control windows */
> 	NTX_SCHED       = 8,     /* # of HW Tx scheduling queues */
> 	PM_NSTATS       = 5,     /* # of PM stats */
> 	T6_PM_NSTATS    = 7,     /* # of PM stats in T6 */
> 	MBOX_LEN        = 64,    /* mailbox size in bytes */
> 	TRACE_LEN       = 112,   /* length of trace data and mask */
> 	FILTER_OPT_LEN  = 36,    /* filter tuple width of optional components */
> 	UDBS_SEG_SIZE   = 128,   /* segment size for BAR2 user doorbells */
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< 	CIM_NUM_IBQ	= 6,	/* # of CIM IBQs */
< 	CIM_NUM_OBQ	= 6,	/* # of CIM OBQs */
< 	CIM_NUM_OBQ_T5	= 8,	/* # of CIM OBQs for T5 adapter */
< 	CIMLA_SIZE	= 2048,	/* # of 32-bit words in CIM LA */
< 	CIM_PIFLA_SIZE	= 64,	/* # of 192-bit words in CIM PIF LA */
< 	CIM_MALA_SIZE	= 64,	/* # of 160-bit words in CIM MA LA */
< 	CIM_IBQ_SIZE	= 128,	/* # of 128-bit words in a CIM IBQ */
< 	CIM_OBQ_SIZE	= 128,	/* # of 128-bit words in a CIM OBQ */
< 	TPLA_SIZE	= 128,	/* # of 64-bit words in TP LA */
< 	ULPRX_LA_SIZE	= 512,	/* # of 256-bit words in ULP_RX LA */
---
> 	CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
> 	CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
> 	CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
> 	CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
> 	CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
> 	CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
> 	CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
> 	CIM_OBQ_SIZE   = 128,   /* # of 128-bit words in a CIM OBQ */
> 	TPLA_SIZE      = 128,   /* # of 64-bit words in TP LA */
> 	ULPRX_LA_SIZE  = 512,   /* # of 256-bit words in ULP_RX LA */
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< 	SF_PAGE_SIZE = 256,		/* serial flash page size */
< 	SF_SEC_SIZE = 64 * 1024,	/* serial flash sector size */
---
> 	SF_PAGE_SIZE = 256,           /* serial flash page size */
> 	SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
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< 	SGE_MAX_WR_LEN = 512,	/* max WR size in bytes */
< 	SGE_CTXT_SIZE = 24,	/* size of SGE context */
< 	SGE_NTIMERS = 6,	/* # of interrupt holdoff timer values */
< 	SGE_NCOUNTERS = 4,	/* # of interrupt packet counter values */
---
> 	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
> 	SGE_CTXT_SIZE = 24,       /* size of SGE context */
> 	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
> 	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
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< struct sge_qstat {		/* data written to SGE queue status entries */
< 	volatile __be32 qid;
< 	volatile __be16 cidx;
< 	volatile __be16 pidx;
---
> /* PCI-e memory window access */
> enum pcie_memwin {
> 	MEMWIN_NIC      = 0,
> 	MEMWIN_RSVD1    = 1,
> 	MEMWIN_RSVD2    = 2,
> 	MEMWIN_RDMA     = 3,
> 	MEMWIN_RSVD4    = 4,
> 	MEMWIN_FOISCSI  = 5,
> 	MEMWIN_CSIOSTOR = 6,
> 	MEMWIN_RSVD7    = 7,
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< #define	S_QSTAT_PIDX    0
< #define	M_QSTAT_PIDX    0xffff
< #define	G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
---
> struct sge_qstat {                /* data written to SGE queue status entries */
> 	__be32 qid;
> 	__be16 cidx;
> 	__be16 pidx;
> };
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< #define	S_QSTAT_CIDX    16
< #define	M_QSTAT_CIDX    0xffff
< #define	G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
---
> #define S_QSTAT_PIDX    0
> #define M_QSTAT_PIDX    0xffff
> #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
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> #define S_QSTAT_CIDX    16
> #define M_QSTAT_CIDX    0xffff
> #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
> 
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< #define	S_RSPD_NEWBUF    31
< #define	V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
< #define	F_RSPD_NEWBUF    V_RSPD_NEWBUF(1U)
---
> #define S_RSPD_NEWBUF    31
> #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
> #define F_RSPD_NEWBUF    V_RSPD_NEWBUF(1U)
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< #define	S_RSPD_LEN    0
< #define	M_RSPD_LEN    0x7fffffff
< #define	V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
< #define	G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
---
> #define S_RSPD_LEN    0
> #define M_RSPD_LEN    0x7fffffff
> #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
> #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
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< #define	S_RSPD_QID    S_RSPD_LEN
< #define	M_RSPD_QID    M_RSPD_LEN
< #define	V_RSPD_QID(x) V_RSPD_LEN(x)
< #define	G_RSPD_QID(x) G_RSPD_LEN(x)
---
> #define S_RSPD_QID    S_RSPD_LEN
> #define M_RSPD_QID    M_RSPD_LEN
> #define V_RSPD_QID(x) V_RSPD_LEN(x)
> #define G_RSPD_QID(x) G_RSPD_LEN(x)
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< #define	S_RSPD_GEN    7
< #define	V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
< #define	F_RSPD_GEN    V_RSPD_GEN(1U)
---
> #define S_RSPD_GEN    7
> #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
> #define F_RSPD_GEN    V_RSPD_GEN(1U)
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< #define	S_RSPD_QOVFL    6
< #define	V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
< #define	F_RSPD_QOVFL    V_RSPD_QOVFL(1U)
---
> #define S_RSPD_QOVFL    6
> #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
> #define F_RSPD_QOVFL    V_RSPD_QOVFL(1U)
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< #define	S_RSPD_TYPE    4
< #define	M_RSPD_TYPE    0x3
< #define	V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
< #define	G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
---
> #define S_RSPD_TYPE    4
> #define M_RSPD_TYPE    0x3
> #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
> #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
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< #define	S_QINTR_CNT_EN    0
< #define	V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
< #define	F_QINTR_CNT_EN    V_QINTR_CNT_EN(1U)
---
> #define S_QINTR_CNT_EN    0
> #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
> #define F_QINTR_CNT_EN    V_QINTR_CNT_EN(1U)
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< #define	S_QINTR_TIMER_IDX    1
< #define	M_QINTR_TIMER_IDX    0x7
< #define	V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
< #define	G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
---
> #define S_QINTR_TIMER_IDX    1
> #define M_QINTR_TIMER_IDX    0x7
> #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
> #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
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< #define	PPOD_PAGES 4U
---
> #define PPOD_PAGES 4U
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< #define	S_PPOD_COLOR    0
< #define	M_PPOD_COLOR    0x3F
< #define	V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
---
> #define S_PPOD_COLOR    0
> #define M_PPOD_COLOR    0x3F
> #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
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< #define	S_PPOD_TAG    6
< #define	M_PPOD_TAG    0xFFFFFF
< #define	V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
< #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
---
> #define S_PPOD_TAG    6
> #define M_PPOD_TAG    0xFFFFFF
> #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
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< #define	S_PPOD_PGSZ    30
< #define	M_PPOD_PGSZ    0x3
< #define	V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
< #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
---
> #define S_PPOD_PGSZ    30
> #define M_PPOD_PGSZ    0x3
> #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
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< #define	S_PPOD_TID    32
< #define	M_PPOD_TID    0xFFFFFF
< #define	V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
---
> #define S_PPOD_TID    32
> #define M_PPOD_TID    0xFFFFFF
> #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
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< #define	S_PPOD_VALID    56
< #define	V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
< #define	F_PPOD_VALID    V_PPOD_VALID(1ULL)
---
> #define S_PPOD_VALID    56
> #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
> #define F_PPOD_VALID    V_PPOD_VALID(1ULL)
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< #define	S_PPOD_LEN    32
< #define	M_PPOD_LEN    0xFFFFFFFF
< #define	V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
---
> #define S_PPOD_LEN    32
> #define M_PPOD_LEN    0xFFFFFFFF
> #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
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< #define	S_PPOD_OFST    0
< #define	M_PPOD_OFST    0xFFFFFFFF
< #define	V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
---
> #define S_PPOD_OFST    0
> #define M_PPOD_OFST    0xFFFFFFFF
> #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
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< #define	FLASH_START(start)	((start) * SF_SEC_SIZE)
< #define	FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
---
> #define FLASH_START(start)	((start) * SF_SEC_SIZE)
> #define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
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< 
---
>  
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< 	 * Location of Firmware Configuration File in FLASH.  Since the FPGA
< 	 * "FLASH" is smaller we need to store the Configuration File in a
< 	 * different location -- which will overlap the end of the firmware
< 	 * image if firmware ever gets that large ...
---
> 	 * Location of Firmware Configuration File in FLASH.
262,263c265,269
< 	FLASH_FPGA_CFG_START_SEC = 15,
< 	FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
---
> 	/*
> 	 * We don't support FLASH devices which can't support the full
> 	 * standard set of sections which we need for normal operations.
> 	 */
> 	FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
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< 	 * Sectors 32-63 are reserved for FLASH failover.
---
> 	 * Sectors 32-63 for CUDBG.
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> 	FLASH_CUDBG_START_SEC = 32,
> 	FLASH_CUDBG_NSECS = 32,
> 	FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
> 	FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
> 
> 	/*
> 	 * Size of defined FLASH regions.
> 	 */
> 	FLASH_END_SEC = 64,
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< #endif /* __CXGBE_T4_HW_H */
---
> #define S_SGE_TIMESTAMP 0
> #define M_SGE_TIMESTAMP 0xfffffffffffffffULL
> #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
> #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
> 
> #endif /* __T4_HW_H */