1/*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12/*
13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
14 *
15 * Copyright (C) 2009-2017 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23#ifndef __T4_HW_H
24#define __T4_HW_H
25
26#include "osdep.h"
27
28enum {
29 NCHAN = 4, /* # of HW channels */
30 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
31 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
32 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
33 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
34 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
35 TCB_SIZE = 128, /* TCB size */
36 NMTUS = 16, /* size of MTU table */
37 NCCTRL_WIN = 32, /* # of congestion control windows */
38 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
39 PM_NSTATS = 5, /* # of PM stats */
40 T6_PM_NSTATS = 7, /* # of PM stats in T6 */
41 MBOX_LEN = 64, /* mailbox size in bytes */
42 TRACE_LEN = 112, /* length of trace data and mask */
43 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
44 UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */
45};
46
47enum {
48 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
49 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
50 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
51 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
52 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
53 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
54 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
55 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
56 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
57 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
58};
59
60enum {
61 SF_PAGE_SIZE = 256, /* serial flash page size */
62 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
63};
64
65/* SGE context types */
66enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
67
68enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
69
70enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
71
72enum {
73 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
74 SGE_CTXT_SIZE = 24, /* size of SGE context */
75 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
76 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
77 SGE_MAX_IQ_SIZE = 65520,
78};
79
80/* PCI-e memory window access */
81enum pcie_memwin {
82 MEMWIN_NIC = 0,
83 MEMWIN_RSVD1 = 1,
84 MEMWIN_RSVD2 = 2,
85 MEMWIN_RDMA = 3,
86 MEMWIN_RSVD4 = 4,
87 MEMWIN_FOISCSI = 5,
88 MEMWIN_CSIOSTOR = 6,
89 MEMWIN_RSVD7 = 7,
90};
91
92struct sge_qstat { /* data written to SGE queue status entries */
93 __be32 qid;
94 __be16 cidx;
95 __be16 pidx;
96};
97
98#define S_QSTAT_PIDX 0
99#define M_QSTAT_PIDX 0xffff
100#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
101
102#define S_QSTAT_CIDX 16
103#define M_QSTAT_CIDX 0xffff
104#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
105
106/*
107 * Structure for last 128 bits of response descriptors
108 */
109struct rsp_ctrl {
110 __be32 hdrbuflen_pidx;
111 __be32 pldbuflen_qid;
112 union {
113 u8 type_gen;
114 __be64 last_flit;
115 } u;
116};
117
118#define S_RSPD_NEWBUF 31
119#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
120#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
121
122#define S_RSPD_LEN 0
123#define M_RSPD_LEN 0x7fffffff
124#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
125#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
126
127#define S_RSPD_QID S_RSPD_LEN
128#define M_RSPD_QID M_RSPD_LEN
129#define V_RSPD_QID(x) V_RSPD_LEN(x)
130#define G_RSPD_QID(x) G_RSPD_LEN(x)
131
132#define S_RSPD_GEN 7
133#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
134#define F_RSPD_GEN V_RSPD_GEN(1U)
135
136#define S_RSPD_QOVFL 6
137#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
138#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
139
140#define S_RSPD_TYPE 4
141#define M_RSPD_TYPE 0x3
142#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
143#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
144
145/* Rx queue interrupt deferral fields: counter enable and timer index */
146#define S_QINTR_CNT_EN 0
147#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
148#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
149
150#define S_QINTR_TIMER_IDX 1
151#define M_QINTR_TIMER_IDX 0x7
152#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
153#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
154
155/* # of pages a pagepod can hold without needing another pagepod */
156#define PPOD_PAGES 4U
157
158struct pagepod {
159 __be64 vld_tid_pgsz_tag_color;
160 __be64 len_offset;
161 __be64 rsvd;
162 __be64 addr[PPOD_PAGES + 1];
163};
164
165#define S_PPOD_COLOR 0
166#define M_PPOD_COLOR 0x3F
167#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
168
169#define S_PPOD_TAG 6
170#define M_PPOD_TAG 0xFFFFFF
171#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
172
173#define S_PPOD_PGSZ 30
174#define M_PPOD_PGSZ 0x3
175#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
176
177#define S_PPOD_TID 32
178#define M_PPOD_TID 0xFFFFFF
179#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
180
181#define S_PPOD_VALID 56
182#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
183#define F_PPOD_VALID V_PPOD_VALID(1ULL)
184
185#define S_PPOD_LEN 32
186#define M_PPOD_LEN 0xFFFFFFFF
187#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
188
189#define S_PPOD_OFST 0
190#define M_PPOD_OFST 0xFFFFFFFF
191#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
192
193/*
194 * Flash layout.
195 */
196#define FLASH_START(start) ((start) * SF_SEC_SIZE)
197#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
198
199enum {
200 /*
201 * Various Expansion-ROM boot images, etc.
202 */
203 FLASH_EXP_ROM_START_SEC = 0,
204 FLASH_EXP_ROM_NSECS = 6,
205 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
--- 18 unchanged lines hidden (view full) ---
224
225 /*
226 * Location of firmware image in FLASH.
227 */
228 FLASH_FW_START_SEC = 8,
229 FLASH_FW_NSECS = 16,
230 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
231 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
232
233 /*
234 * Location of bootstrap firmware image in FLASH.
235 */
236 FLASH_FWBOOTSTRAP_START_SEC = 27,
237 FLASH_FWBOOTSTRAP_NSECS = 1,
238 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
239 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
240
--- 9 unchanged lines hidden (view full) ---
250 * FCoE persistent/crash information.
251 */
252 FLASH_FCOE_CRASH_START_SEC = 30,
253 FLASH_FCOE_CRASH_NSECS = 1,
254 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
255 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
256
257 /*
258 * Location of Firmware Configuration File in FLASH.
259 */
260 FLASH_CFG_START_SEC = 31,
261 FLASH_CFG_NSECS = 1,
262 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
263 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
264
265 /*
266 * We don't support FLASH devices which can't support the full
267 * standard set of sections which we need for normal operations.
268 */
269 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
270
271 /*
272 * Sectors 32-63 for CUDBG.
273 */
274 FLASH_CUDBG_START_SEC = 32,
275 FLASH_CUDBG_NSECS = 32,
276 FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
277 FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
278
279 /*
280 * Size of defined FLASH regions.
281 */
282 FLASH_END_SEC = 64,
283};
284
285#undef FLASH_START
286#undef FLASH_MAX_SIZE
287
288#define S_SGE_TIMESTAMP 0
289#define M_SGE_TIMESTAMP 0xfffffffffffffffULL
290#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
291#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
292
293#endif /* __T4_HW_H */
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12/*
13 * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
14 *
15 * Copyright (C) 2009-2017 Chelsio Communications. All rights reserved.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
21 */
22
23#ifndef __T4_HW_H
24#define __T4_HW_H
25
26#include "osdep.h"
27
28enum {
29 NCHAN = 4, /* # of HW channels */
30 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
31 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
32 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
33 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
34 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
35 TCB_SIZE = 128, /* TCB size */
36 NMTUS = 16, /* size of MTU table */
37 NCCTRL_WIN = 32, /* # of congestion control windows */
38 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
39 PM_NSTATS = 5, /* # of PM stats */
40 T6_PM_NSTATS = 7, /* # of PM stats in T6 */
41 MBOX_LEN = 64, /* mailbox size in bytes */
42 TRACE_LEN = 112, /* length of trace data and mask */
43 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
44 UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */
45};
46
47enum {
48 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
49 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
50 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
51 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
52 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
53 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
54 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
55 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
56 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
57 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
58};
59
60enum {
61 SF_PAGE_SIZE = 256, /* serial flash page size */
62 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
63};
64
65/* SGE context types */
66enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
67
68enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
69
70enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
71
72enum {
73 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
74 SGE_CTXT_SIZE = 24, /* size of SGE context */
75 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
76 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
77 SGE_MAX_IQ_SIZE = 65520,
78};
79
80/* PCI-e memory window access */
81enum pcie_memwin {
82 MEMWIN_NIC = 0,
83 MEMWIN_RSVD1 = 1,
84 MEMWIN_RSVD2 = 2,
85 MEMWIN_RDMA = 3,
86 MEMWIN_RSVD4 = 4,
87 MEMWIN_FOISCSI = 5,
88 MEMWIN_CSIOSTOR = 6,
89 MEMWIN_RSVD7 = 7,
90};
91
92struct sge_qstat { /* data written to SGE queue status entries */
93 __be32 qid;
94 __be16 cidx;
95 __be16 pidx;
96};
97
98#define S_QSTAT_PIDX 0
99#define M_QSTAT_PIDX 0xffff
100#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
101
102#define S_QSTAT_CIDX 16
103#define M_QSTAT_CIDX 0xffff
104#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
105
106/*
107 * Structure for last 128 bits of response descriptors
108 */
109struct rsp_ctrl {
110 __be32 hdrbuflen_pidx;
111 __be32 pldbuflen_qid;
112 union {
113 u8 type_gen;
114 __be64 last_flit;
115 } u;
116};
117
118#define S_RSPD_NEWBUF 31
119#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
120#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
121
122#define S_RSPD_LEN 0
123#define M_RSPD_LEN 0x7fffffff
124#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
125#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
126
127#define S_RSPD_QID S_RSPD_LEN
128#define M_RSPD_QID M_RSPD_LEN
129#define V_RSPD_QID(x) V_RSPD_LEN(x)
130#define G_RSPD_QID(x) G_RSPD_LEN(x)
131
132#define S_RSPD_GEN 7
133#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
134#define F_RSPD_GEN V_RSPD_GEN(1U)
135
136#define S_RSPD_QOVFL 6
137#define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
138#define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
139
140#define S_RSPD_TYPE 4
141#define M_RSPD_TYPE 0x3
142#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
143#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
144
145/* Rx queue interrupt deferral fields: counter enable and timer index */
146#define S_QINTR_CNT_EN 0
147#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
148#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
149
150#define S_QINTR_TIMER_IDX 1
151#define M_QINTR_TIMER_IDX 0x7
152#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
153#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
154
155/* # of pages a pagepod can hold without needing another pagepod */
156#define PPOD_PAGES 4U
157
158struct pagepod {
159 __be64 vld_tid_pgsz_tag_color;
160 __be64 len_offset;
161 __be64 rsvd;
162 __be64 addr[PPOD_PAGES + 1];
163};
164
165#define S_PPOD_COLOR 0
166#define M_PPOD_COLOR 0x3F
167#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
168
169#define S_PPOD_TAG 6
170#define M_PPOD_TAG 0xFFFFFF
171#define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
172
173#define S_PPOD_PGSZ 30
174#define M_PPOD_PGSZ 0x3
175#define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
176
177#define S_PPOD_TID 32
178#define M_PPOD_TID 0xFFFFFF
179#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
180
181#define S_PPOD_VALID 56
182#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
183#define F_PPOD_VALID V_PPOD_VALID(1ULL)
184
185#define S_PPOD_LEN 32
186#define M_PPOD_LEN 0xFFFFFFFF
187#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
188
189#define S_PPOD_OFST 0
190#define M_PPOD_OFST 0xFFFFFFFF
191#define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
192
193/*
194 * Flash layout.
195 */
196#define FLASH_START(start) ((start) * SF_SEC_SIZE)
197#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
198
199enum {
200 /*
201 * Various Expansion-ROM boot images, etc.
202 */
203 FLASH_EXP_ROM_START_SEC = 0,
204 FLASH_EXP_ROM_NSECS = 6,
205 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
--- 18 unchanged lines hidden (view full) ---
224
225 /*
226 * Location of firmware image in FLASH.
227 */
228 FLASH_FW_START_SEC = 8,
229 FLASH_FW_NSECS = 16,
230 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
231 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
232
233 /*
234 * Location of bootstrap firmware image in FLASH.
235 */
236 FLASH_FWBOOTSTRAP_START_SEC = 27,
237 FLASH_FWBOOTSTRAP_NSECS = 1,
238 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
239 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
240
--- 9 unchanged lines hidden (view full) ---
250 * FCoE persistent/crash information.
251 */
252 FLASH_FCOE_CRASH_START_SEC = 30,
253 FLASH_FCOE_CRASH_NSECS = 1,
254 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
255 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
256
257 /*
258 * Location of Firmware Configuration File in FLASH.
259 */
260 FLASH_CFG_START_SEC = 31,
261 FLASH_CFG_NSECS = 1,
262 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
263 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
264
265 /*
266 * We don't support FLASH devices which can't support the full
267 * standard set of sections which we need for normal operations.
268 */
269 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
270
271 /*
272 * Sectors 32-63 for CUDBG.
273 */
274 FLASH_CUDBG_START_SEC = 32,
275 FLASH_CUDBG_NSECS = 32,
276 FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
277 FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
278
279 /*
280 * Size of defined FLASH regions.
281 */
282 FLASH_END_SEC = 64,
283};
284
285#undef FLASH_START
286#undef FLASH_MAX_SIZE
287
288#define S_SGE_TIMESTAMP 0
289#define M_SGE_TIMESTAMP 0xfffffffffffffffULL
290#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
291#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
292
293#endif /* __T4_HW_H */