ahci.h (bf21cd93) ahci.h (4c87aefe)
1/*-
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
27 * $FreeBSD: head/usr.sbin/bhyve/ahci.h 256056 2013-10-04 18:31:38Z grehan $
29 * $FreeBSD$
28 */
29
30#ifndef _AHCI_H_
31#define _AHCI_H_
32
33/* ATA register defines */
30 */
31
32#ifndef _AHCI_H_
33#define _AHCI_H_
34
35/* ATA register defines */
34#define ATA_DATA 0 /* (RW) data */
36#define ATA_DATA 0 /* (RW) data */
35
37
36#define ATA_FEATURE 1 /* (W) feature */
37#define ATA_F_DMA 0x01 /* enable DMA */
38#define ATA_F_OVL 0x02 /* enable overlap */
38#define ATA_FEATURE 1 /* (W) feature */
39#define ATA_F_DMA 0x01 /* enable DMA */
40#define ATA_F_OVL 0x02 /* enable overlap */
39
41
40#define ATA_COUNT 2 /* (W) sector count */
42#define ATA_COUNT 2 /* (W) sector count */
41
43
42#define ATA_SECTOR 3 /* (RW) sector # */
43#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
44#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
45#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
46#define ATA_D_LBA 0x40 /* use LBA addressing */
47#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
44#define ATA_SECTOR 3 /* (RW) sector # */
45#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
46#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
47#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
48#define ATA_D_LBA 0x40 /* use LBA addressing */
49#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
48
50
49#define ATA_COMMAND 7 /* (W) command */
51#define ATA_COMMAND 7 /* (W) command */
50
52
51#define ATA_ERROR 8 /* (R) error */
52#define ATA_E_ILI 0x01 /* illegal length */
53#define ATA_E_NM 0x02 /* no media */
54#define ATA_E_ABORT 0x04 /* command aborted */
55#define ATA_E_MCR 0x08 /* media change request */
56#define ATA_E_IDNF 0x10 /* ID not found */
57#define ATA_E_MC 0x20 /* media changed */
58#define ATA_E_UNC 0x40 /* uncorrectable data */
59#define ATA_E_ICRC 0x80 /* UDMA crc error */
60#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
53#define ATA_ERROR 8 /* (R) error */
54#define ATA_E_ILI 0x01 /* illegal length */
55#define ATA_E_NM 0x02 /* no media */
56#define ATA_E_ABORT 0x04 /* command aborted */
57#define ATA_E_MCR 0x08 /* media change request */
58#define ATA_E_IDNF 0x10 /* ID not found */
59#define ATA_E_MC 0x20 /* media changed */
60#define ATA_E_UNC 0x40 /* uncorrectable data */
61#define ATA_E_ICRC 0x80 /* UDMA crc error */
62#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
61
63
62#define ATA_IREASON 9 /* (R) interrupt reason */
63#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
64#define ATA_I_IN 0x02 /* read (1) | write (0) */
65#define ATA_I_RELEASE 0x04 /* released bus (1) */
66#define ATA_I_TAGMASK 0xf8 /* tag mask */
64#define ATA_IREASON 9 /* (R) interrupt reason */
65#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
66#define ATA_I_IN 0x02 /* read (1) | write (0) */
67#define ATA_I_RELEASE 0x04 /* released bus (1) */
68#define ATA_I_TAGMASK 0xf8 /* tag mask */
67
69
68#define ATA_STATUS 10 /* (R) status */
69#define ATA_ALTSTAT 11 /* (R) alternate status */
70#define ATA_S_ERROR 0x01 /* error */
71#define ATA_S_INDEX 0x02 /* index */
72#define ATA_S_CORR 0x04 /* data corrected */
73#define ATA_S_DRQ 0x08 /* data request */
74#define ATA_S_DSC 0x10 /* drive seek completed */
75#define ATA_S_SERVICE 0x10 /* drive needs service */
76#define ATA_S_DWF 0x20 /* drive write fault */
77#define ATA_S_DMA 0x20 /* DMA ready */
78#define ATA_S_READY 0x40 /* drive ready */
79#define ATA_S_BUSY 0x80 /* busy */
70#define ATA_STATUS 10 /* (R) status */
71#define ATA_ALTSTAT 11 /* (R) alternate status */
72#define ATA_S_ERROR 0x01 /* error */
73#define ATA_S_INDEX 0x02 /* index */
74#define ATA_S_CORR 0x04 /* data corrected */
75#define ATA_S_DRQ 0x08 /* data request */
76#define ATA_S_DSC 0x10 /* drive seek completed */
77#define ATA_S_SERVICE 0x10 /* drive needs service */
78#define ATA_S_DWF 0x20 /* drive write fault */
79#define ATA_S_DMA 0x20 /* DMA ready */
80#define ATA_S_READY 0x40 /* drive ready */
81#define ATA_S_BUSY 0x80 /* busy */
80
82
81#define ATA_CONTROL 12 /* (W) control */
82#define ATA_A_IDS 0x02 /* disable interrupts */
83#define ATA_A_RESET 0x04 /* RESET controller */
84#define ATA_A_4BIT 0x08 /* 4 head bits */
85#define ATA_A_HOB 0x80 /* High Order Byte enable */
83#define ATA_CONTROL 12 /* (W) control */
84#define ATA_A_IDS 0x02 /* disable interrupts */
85#define ATA_A_RESET 0x04 /* RESET controller */
86#define ATA_A_4BIT 0x08 /* 4 head bits */
87#define ATA_A_HOB 0x80 /* High Order Byte enable */
86
87/* SATA register defines */
88
89/* SATA register defines */
88#define ATA_SSTATUS 13
89#define ATA_SS_DET_MASK 0x0000000f
90#define ATA_SS_DET_NO_DEVICE 0x00000000
91#define ATA_SS_DET_DEV_PRESENT 0x00000001
92#define ATA_SS_DET_PHY_ONLINE 0x00000003
93#define ATA_SS_DET_PHY_OFFLINE 0x00000004
90#define ATA_SSTATUS 13
91#define ATA_SS_DET_MASK 0x0000000f
92#define ATA_SS_DET_NO_DEVICE 0x00000000
93#define ATA_SS_DET_DEV_PRESENT 0x00000001
94#define ATA_SS_DET_PHY_ONLINE 0x00000003
95#define ATA_SS_DET_PHY_OFFLINE 0x00000004
94
96
95#define ATA_SS_SPD_MASK 0x000000f0
96#define ATA_SS_SPD_NO_SPEED 0x00000000
97#define ATA_SS_SPD_GEN1 0x00000010
98#define ATA_SS_SPD_GEN2 0x00000020
99#define ATA_SS_SPD_GEN3 0x00000040
97#define ATA_SS_SPD_MASK 0x000000f0
98#define ATA_SS_SPD_NO_SPEED 0x00000000
99#define ATA_SS_SPD_GEN1 0x00000010
100#define ATA_SS_SPD_GEN2 0x00000020
101#define ATA_SS_SPD_GEN3 0x00000030
100
102
101#define ATA_SS_IPM_MASK 0x00000f00
102#define ATA_SS_IPM_NO_DEVICE 0x00000000
103#define ATA_SS_IPM_ACTIVE 0x00000100
104#define ATA_SS_IPM_PARTIAL 0x00000200
105#define ATA_SS_IPM_SLUMBER 0x00000600
103#define ATA_SS_IPM_MASK 0x00000f00
104#define ATA_SS_IPM_NO_DEVICE 0x00000000
105#define ATA_SS_IPM_ACTIVE 0x00000100
106#define ATA_SS_IPM_PARTIAL 0x00000200
107#define ATA_SS_IPM_SLUMBER 0x00000600
108#define ATA_SS_IPM_DEVSLEEP 0x00000800
106
109
107#define ATA_SERROR 14
108#define ATA_SE_DATA_CORRECTED 0x00000001
109#define ATA_SE_COMM_CORRECTED 0x00000002
110#define ATA_SE_DATA_ERR 0x00000100
111#define ATA_SE_COMM_ERR 0x00000200
112#define ATA_SE_PROT_ERR 0x00000400
113#define ATA_SE_HOST_ERR 0x00000800
114#define ATA_SE_PHY_CHANGED 0x00010000
115#define ATA_SE_PHY_IERROR 0x00020000
116#define ATA_SE_COMM_WAKE 0x00040000
117#define ATA_SE_DECODE_ERR 0x00080000
118#define ATA_SE_PARITY_ERR 0x00100000
119#define ATA_SE_CRC_ERR 0x00200000
120#define ATA_SE_HANDSHAKE_ERR 0x00400000
121#define ATA_SE_LINKSEQ_ERR 0x00800000
122#define ATA_SE_TRANSPORT_ERR 0x01000000
123#define ATA_SE_UNKNOWN_FIS 0x02000000
124#define ATA_SE_EXCHANGED 0x04000000
110#define ATA_SERROR 14
111#define ATA_SE_DATA_CORRECTED 0x00000001
112#define ATA_SE_COMM_CORRECTED 0x00000002
113#define ATA_SE_DATA_ERR 0x00000100
114#define ATA_SE_COMM_ERR 0x00000200
115#define ATA_SE_PROT_ERR 0x00000400
116#define ATA_SE_HOST_ERR 0x00000800
117#define ATA_SE_PHY_CHANGED 0x00010000
118#define ATA_SE_PHY_IERROR 0x00020000
119#define ATA_SE_COMM_WAKE 0x00040000
120#define ATA_SE_DECODE_ERR 0x00080000
121#define ATA_SE_PARITY_ERR 0x00100000
122#define ATA_SE_CRC_ERR 0x00200000
123#define ATA_SE_HANDSHAKE_ERR 0x00400000
124#define ATA_SE_LINKSEQ_ERR 0x00800000
125#define ATA_SE_TRANSPORT_ERR 0x01000000
126#define ATA_SE_UNKNOWN_FIS 0x02000000
127#define ATA_SE_EXCHANGED 0x04000000
125
128
126#define ATA_SCONTROL 15
127#define ATA_SC_DET_MASK 0x0000000f
128#define ATA_SC_DET_IDLE 0x00000000
129#define ATA_SC_DET_RESET 0x00000001
130#define ATA_SC_DET_DISABLE 0x00000004
129#define ATA_SCONTROL 15
130#define ATA_SC_DET_MASK 0x0000000f
131#define ATA_SC_DET_IDLE 0x00000000
132#define ATA_SC_DET_RESET 0x00000001
133#define ATA_SC_DET_DISABLE 0x00000004
131
134
132#define ATA_SC_SPD_MASK 0x000000f0
133#define ATA_SC_SPD_NO_SPEED 0x00000000
134#define ATA_SC_SPD_SPEED_GEN1 0x00000010
135#define ATA_SC_SPD_SPEED_GEN2 0x00000020
136#define ATA_SC_SPD_SPEED_GEN3 0x00000040
135#define ATA_SC_SPD_MASK 0x000000f0
136#define ATA_SC_SPD_NO_SPEED 0x00000000
137#define ATA_SC_SPD_SPEED_GEN1 0x00000010
138#define ATA_SC_SPD_SPEED_GEN2 0x00000020
139#define ATA_SC_SPD_SPEED_GEN3 0x00000030
137
140
138#define ATA_SC_IPM_MASK 0x00000f00
139#define ATA_SC_IPM_NONE 0x00000000
140#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
141#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
141#define ATA_SC_IPM_MASK 0x00000f00
142#define ATA_SC_IPM_NONE 0x00000000
143#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
144#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
145#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
142
146
143#define ATA_SACTIVE 16
147#define ATA_SACTIVE 16
144
148
145#define AHCI_MAX_PORTS 32
146#define AHCI_MAX_SLOTS 32
149#define AHCI_MAX_PORTS 32
150#define AHCI_MAX_SLOTS 32
151#define AHCI_MAX_IRQS 16
147
148/* SATA AHCI v1.0 register defines */
152
153/* SATA AHCI v1.0 register defines */
149#define AHCI_CAP 0x00
150#define AHCI_CAP_NPMASK 0x0000001f
151#define AHCI_CAP_SXS 0x00000020
152#define AHCI_CAP_EMS 0x00000040
153#define AHCI_CAP_CCCS 0x00000080
154#define AHCI_CAP_NCS 0x00001F00
155#define AHCI_CAP_NCS_SHIFT 8
156#define AHCI_CAP_PSC 0x00002000
157#define AHCI_CAP_SSC 0x00004000
158#define AHCI_CAP_PMD 0x00008000
159#define AHCI_CAP_FBSS 0x00010000
160#define AHCI_CAP_SPM 0x00020000
161#define AHCI_CAP_SAM 0x00080000
162#define AHCI_CAP_ISS 0x00F00000
163#define AHCI_CAP_ISS_SHIFT 20
164#define AHCI_CAP_SCLO 0x01000000
165#define AHCI_CAP_SAL 0x02000000
166#define AHCI_CAP_SALP 0x04000000
167#define AHCI_CAP_SSS 0x08000000
168#define AHCI_CAP_SMPS 0x10000000
169#define AHCI_CAP_SSNTF 0x20000000
170#define AHCI_CAP_SNCQ 0x40000000
171#define AHCI_CAP_64BIT 0x80000000
154#define AHCI_CAP 0x00
155#define AHCI_CAP_NPMASK 0x0000001f
156#define AHCI_CAP_SXS 0x00000020
157#define AHCI_CAP_EMS 0x00000040
158#define AHCI_CAP_CCCS 0x00000080
159#define AHCI_CAP_NCS 0x00001F00
160#define AHCI_CAP_NCS_SHIFT 8
161#define AHCI_CAP_PSC 0x00002000
162#define AHCI_CAP_SSC 0x00004000
163#define AHCI_CAP_PMD 0x00008000
164#define AHCI_CAP_FBSS 0x00010000
165#define AHCI_CAP_SPM 0x00020000
166#define AHCI_CAP_SAM 0x00080000
167#define AHCI_CAP_ISS 0x00F00000
168#define AHCI_CAP_ISS_SHIFT 20
169#define AHCI_CAP_SCLO 0x01000000
170#define AHCI_CAP_SAL 0x02000000
171#define AHCI_CAP_SALP 0x04000000
172#define AHCI_CAP_SSS 0x08000000
173#define AHCI_CAP_SMPS 0x10000000
174#define AHCI_CAP_SSNTF 0x20000000
175#define AHCI_CAP_SNCQ 0x40000000
176#define AHCI_CAP_64BIT 0x80000000
172
177
173#define AHCI_GHC 0x04
174#define AHCI_GHC_AE 0x80000000
175#define AHCI_GHC_MRSM 0x00000004
176#define AHCI_GHC_IE 0x00000002
177#define AHCI_GHC_HR 0x00000001
178#define AHCI_GHC 0x04
179#define AHCI_GHC_AE 0x80000000
180#define AHCI_GHC_MRSM 0x00000004
181#define AHCI_GHC_IE 0x00000002
182#define AHCI_GHC_HR 0x00000001
178
183
179#define AHCI_IS 0x08
180#define AHCI_PI 0x0c
181#define AHCI_VS 0x10
184#define AHCI_IS 0x08
185#define AHCI_PI 0x0c
186#define AHCI_VS 0x10
182
187
183#define AHCI_CCCC 0x14
184#define AHCI_CCCC_TV_MASK 0xffff0000
185#define AHCI_CCCC_TV_SHIFT 16
186#define AHCI_CCCC_CC_MASK 0x0000ff00
187#define AHCI_CCCC_CC_SHIFT 8
188#define AHCI_CCCC_INT_MASK 0x000000f8
189#define AHCI_CCCC_INT_SHIFT 3
190#define AHCI_CCCC_EN 0x00000001
191#define AHCI_CCCP 0x18
188#define AHCI_CCCC 0x14
189#define AHCI_CCCC_TV_MASK 0xffff0000
190#define AHCI_CCCC_TV_SHIFT 16
191#define AHCI_CCCC_CC_MASK 0x0000ff00
192#define AHCI_CCCC_CC_SHIFT 8
193#define AHCI_CCCC_INT_MASK 0x000000f8
194#define AHCI_CCCC_INT_SHIFT 3
195#define AHCI_CCCC_EN 0x00000001
196#define AHCI_CCCP 0x18
192
197
193#define AHCI_EM_LOC 0x1C
194#define AHCI_EM_CTL 0x20
195#define AHCI_EM_MR 0x00000001
196#define AHCI_EM_TM 0x00000100
197#define AHCI_EM_RST 0x00000200
198#define AHCI_EM_LED 0x00010000
199#define AHCI_EM_SAFTE 0x00020000
200#define AHCI_EM_SES2 0x00040000
201#define AHCI_EM_SGPIO 0x00080000
202#define AHCI_EM_SMB 0x01000000
203#define AHCI_EM_XMT 0x02000000
204#define AHCI_EM_ALHD 0x04000000
205#define AHCI_EM_PM 0x08000000
198#define AHCI_EM_LOC 0x1C
199#define AHCI_EM_CTL 0x20
200#define AHCI_EM_MR 0x00000001
201#define AHCI_EM_TM 0x00000100
202#define AHCI_EM_RST 0x00000200
203#define AHCI_EM_LED 0x00010000
204#define AHCI_EM_SAFTE 0x00020000
205#define AHCI_EM_SES2 0x00040000
206#define AHCI_EM_SGPIO 0x00080000
207#define AHCI_EM_SMB 0x01000000
208#define AHCI_EM_XMT 0x02000000
209#define AHCI_EM_ALHD 0x04000000
210#define AHCI_EM_PM 0x08000000
206
211
207#define AHCI_CAP2 0x24
208#define AHCI_CAP2_BOH 0x00000001
209#define AHCI_CAP2_NVMP 0x00000002
210#define AHCI_CAP2_APST 0x00000004
212#define AHCI_CAP2 0x24
213#define AHCI_CAP2_BOH 0x00000001
214#define AHCI_CAP2_NVMP 0x00000002
215#define AHCI_CAP2_APST 0x00000004
216#define AHCI_CAP2_SDS 0x00000008
217#define AHCI_CAP2_SADM 0x00000010
218#define AHCI_CAP2_DESO 0x00000020
211
219
212#define AHCI_OFFSET 0x100
213#define AHCI_STEP 0x80
220#define AHCI_OFFSET 0x100
221#define AHCI_STEP 0x80
214
222
215#define AHCI_P_CLB 0x00
216#define AHCI_P_CLBU 0x04
217#define AHCI_P_FB 0x08
218#define AHCI_P_FBU 0x0c
219#define AHCI_P_IS 0x10
220#define AHCI_P_IE 0x14
221#define AHCI_P_IX_DHR 0x00000001
222#define AHCI_P_IX_PS 0x00000002
223#define AHCI_P_IX_DS 0x00000004
224#define AHCI_P_IX_SDB 0x00000008
225#define AHCI_P_IX_UF 0x00000010
226#define AHCI_P_IX_DP 0x00000020
227#define AHCI_P_IX_PC 0x00000040
228#define AHCI_P_IX_MP 0x00000080
223#define AHCI_P_CLB 0x00
224#define AHCI_P_CLBU 0x04
225#define AHCI_P_FB 0x08
226#define AHCI_P_FBU 0x0c
227#define AHCI_P_IS 0x10
228#define AHCI_P_IE 0x14
229#define AHCI_P_IX_DHR 0x00000001
230#define AHCI_P_IX_PS 0x00000002
231#define AHCI_P_IX_DS 0x00000004
232#define AHCI_P_IX_SDB 0x00000008
233#define AHCI_P_IX_UF 0x00000010
234#define AHCI_P_IX_DP 0x00000020
235#define AHCI_P_IX_PC 0x00000040
236#define AHCI_P_IX_MP 0x00000080
229
237
230#define AHCI_P_IX_PRC 0x00400000
231#define AHCI_P_IX_IPM 0x00800000
232#define AHCI_P_IX_OF 0x01000000
233#define AHCI_P_IX_INF 0x04000000
234#define AHCI_P_IX_IF 0x08000000
235#define AHCI_P_IX_HBD 0x10000000
236#define AHCI_P_IX_HBF 0x20000000
237#define AHCI_P_IX_TFE 0x40000000
238#define AHCI_P_IX_CPD 0x80000000
238#define AHCI_P_IX_PRC 0x00400000
239#define AHCI_P_IX_IPM 0x00800000
240#define AHCI_P_IX_OF 0x01000000
241#define AHCI_P_IX_INF 0x04000000
242#define AHCI_P_IX_IF 0x08000000
243#define AHCI_P_IX_HBD 0x10000000
244#define AHCI_P_IX_HBF 0x20000000
245#define AHCI_P_IX_TFE 0x40000000
246#define AHCI_P_IX_CPD 0x80000000
239
247
240#define AHCI_P_CMD 0x18
241#define AHCI_P_CMD_ST 0x00000001
242#define AHCI_P_CMD_SUD 0x00000002
243#define AHCI_P_CMD_POD 0x00000004
244#define AHCI_P_CMD_CLO 0x00000008
245#define AHCI_P_CMD_FRE 0x00000010
246#define AHCI_P_CMD_CCS_MASK 0x00001f00
247#define AHCI_P_CMD_CCS_SHIFT 8
248#define AHCI_P_CMD_ISS 0x00002000
249#define AHCI_P_CMD_FR 0x00004000
250#define AHCI_P_CMD_CR 0x00008000
251#define AHCI_P_CMD_CPS 0x00010000
252#define AHCI_P_CMD_PMA 0x00020000
253#define AHCI_P_CMD_HPCP 0x00040000
254#define AHCI_P_CMD_MPSP 0x00080000
255#define AHCI_P_CMD_CPD 0x00100000
256#define AHCI_P_CMD_ESP 0x00200000
257#define AHCI_P_CMD_FBSCP 0x00400000
258#define AHCI_P_CMD_APSTE 0x00800000
259#define AHCI_P_CMD_ATAPI 0x01000000
260#define AHCI_P_CMD_DLAE 0x02000000
261#define AHCI_P_CMD_ALPE 0x04000000
262#define AHCI_P_CMD_ASP 0x08000000
263#define AHCI_P_CMD_ICC_MASK 0xf0000000
264#define AHCI_P_CMD_NOOP 0x00000000
265#define AHCI_P_CMD_ACTIVE 0x10000000
266#define AHCI_P_CMD_PARTIAL 0x20000000
267#define AHCI_P_CMD_SLUMBER 0x60000000
248#define AHCI_P_CMD 0x18
249#define AHCI_P_CMD_ST 0x00000001
250#define AHCI_P_CMD_SUD 0x00000002
251#define AHCI_P_CMD_POD 0x00000004
252#define AHCI_P_CMD_CLO 0x00000008
253#define AHCI_P_CMD_FRE 0x00000010
254#define AHCI_P_CMD_CCS_MASK 0x00001f00
255#define AHCI_P_CMD_CCS_SHIFT 8
256#define AHCI_P_CMD_ISS 0x00002000
257#define AHCI_P_CMD_FR 0x00004000
258#define AHCI_P_CMD_CR 0x00008000
259#define AHCI_P_CMD_CPS 0x00010000
260#define AHCI_P_CMD_PMA 0x00020000
261#define AHCI_P_CMD_HPCP 0x00040000
262#define AHCI_P_CMD_MPSP 0x00080000
263#define AHCI_P_CMD_CPD 0x00100000
264#define AHCI_P_CMD_ESP 0x00200000
265#define AHCI_P_CMD_FBSCP 0x00400000
266#define AHCI_P_CMD_APSTE 0x00800000
267#define AHCI_P_CMD_ATAPI 0x01000000
268#define AHCI_P_CMD_DLAE 0x02000000
269#define AHCI_P_CMD_ALPE 0x04000000
270#define AHCI_P_CMD_ASP 0x08000000
271#define AHCI_P_CMD_ICC_MASK 0xf0000000
272#define AHCI_P_CMD_NOOP 0x00000000
273#define AHCI_P_CMD_ACTIVE 0x10000000
274#define AHCI_P_CMD_PARTIAL 0x20000000
275#define AHCI_P_CMD_SLUMBER 0x60000000
276#define AHCI_P_CMD_DEVSLEEP 0x80000000
268
277
269#define AHCI_P_TFD 0x20
270#define AHCI_P_SIG 0x24
271#define AHCI_P_SSTS 0x28
272#define AHCI_P_SCTL 0x2c
273#define AHCI_P_SERR 0x30
274#define AHCI_P_SACT 0x34
275#define AHCI_P_CI 0x38
276#define AHCI_P_SNTF 0x3C
277#define AHCI_P_FBS 0x40
278#define AHCI_P_FBS_EN 0x00000001
279#define AHCI_P_FBS_DEC 0x00000002
280#define AHCI_P_FBS_SDE 0x00000004
281#define AHCI_P_FBS_DEV 0x00000f00
282#define AHCI_P_FBS_DEV_SHIFT 8
283#define AHCI_P_FBS_ADO 0x0000f000
284#define AHCI_P_FBS_ADO_SHIFT 12
285#define AHCI_P_FBS_DWE 0x000f0000
286#define AHCI_P_FBS_DWE_SHIFT 16
278#define AHCI_P_TFD 0x20
279#define AHCI_P_SIG 0x24
280#define AHCI_P_SSTS 0x28
281#define AHCI_P_SCTL 0x2c
282#define AHCI_P_SERR 0x30
283#define AHCI_P_SACT 0x34
284#define AHCI_P_CI 0x38
285#define AHCI_P_SNTF 0x3C
286#define AHCI_P_FBS 0x40
287#define AHCI_P_FBS_EN 0x00000001
288#define AHCI_P_FBS_DEC 0x00000002
289#define AHCI_P_FBS_SDE 0x00000004
290#define AHCI_P_FBS_DEV 0x00000f00
291#define AHCI_P_FBS_DEV_SHIFT 8
292#define AHCI_P_FBS_ADO 0x0000f000
293#define AHCI_P_FBS_ADO_SHIFT 12
294#define AHCI_P_FBS_DWE 0x000f0000
295#define AHCI_P_FBS_DWE_SHIFT 16
296#define AHCI_P_DEVSLP 0x44
297#define AHCI_P_DEVSLP_ADSE 0x00000001
298#define AHCI_P_DEVSLP_DSP 0x00000002
299#define AHCI_P_DEVSLP_DETO 0x000003fc
300#define AHCI_P_DEVSLP_DETO_SHIFT 2
301#define AHCI_P_DEVSLP_MDAT 0x00007c00
302#define AHCI_P_DEVSLP_MDAT_SHIFT 10
303#define AHCI_P_DEVSLP_DITO 0x01ff8000
304#define AHCI_P_DEVSLP_DITO_SHIFT 15
305#define AHCI_P_DEVSLP_DM 0x0e000000
306#define AHCI_P_DEVSLP_DM_SHIFT 25
287
288/* Just to be sure, if building as module. */
289#if MAXPHYS < 512 * 1024
290#undef MAXPHYS
307
308/* Just to be sure, if building as module. */
309#if MAXPHYS < 512 * 1024
310#undef MAXPHYS
291#define MAXPHYS 512 * 1024
311#define MAXPHYS 512 * 1024
292#endif
293/* Pessimistic prognosis on number of required S/G entries */
312#endif
313/* Pessimistic prognosis on number of required S/G entries */
294#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
314#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
295/* Command list. 32 commands. First, 1Kbyte aligned. */
315/* Command list. 32 commands. First, 1Kbyte aligned. */
296#define AHCI_CL_OFFSET 0
297#define AHCI_CL_SIZE 32
316#define AHCI_CL_OFFSET 0
317#define AHCI_CL_SIZE 32
298/* Command tables. Up to 32 commands, Each, 128byte aligned. */
318/* Command tables. Up to 32 commands, Each, 128byte aligned. */
299#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
300#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
319#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
320#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
301/* Total main work area. */
321/* Total main work area. */
302#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
322#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
303
304#endif /* _AHCI_H_ */
323
324#endif /* _AHCI_H_ */