17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51ae08745Sheppo * Common Development and Distribution License (the "License"). 61ae08745Sheppo * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate #include <sys/errno.h> 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/param.h> 317c478bd9Sstevel@tonic-gate #include <sys/cpu.h> 327c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 337c478bd9Sstevel@tonic-gate #include <sys/clock.h> 347c478bd9Sstevel@tonic-gate #include <sys/promif.h> 357c478bd9Sstevel@tonic-gate #include <sys/promimpl.h> 367c478bd9Sstevel@tonic-gate #include <sys/systm.h> 377c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 387c478bd9Sstevel@tonic-gate #include <sys/debug.h> 397c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 407c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 417c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h> 427c478bd9Sstevel@tonic-gate #include <sys/kobj.h> 437c478bd9Sstevel@tonic-gate #include <sys/cmp.h> 447c478bd9Sstevel@tonic-gate #include <sys/async.h> 457c478bd9Sstevel@tonic-gate #include <vm/page.h> 461ae08745Sheppo #include <vm/hat_sfmmu.h> 471ae08745Sheppo #include <sys/sysmacros.h> 481ae08745Sheppo #include <sys/mach_descrip.h> 491ae08745Sheppo #include <sys/mdesc.h> 501ae08745Sheppo #include <sys/archsystm.h> 511ae08745Sheppo #include <sys/error.h> 521ae08745Sheppo #include <sys/mmu.h> 531ae08745Sheppo #include <sys/bitmap.h> 544bac2208Snarayan #include <sys/intreg.h> 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate struct cpu_node cpunodes[NCPU]; 577c478bd9Sstevel@tonic-gate 581ae08745Sheppo uint64_t cpu_q_entries; 591ae08745Sheppo uint64_t dev_q_entries; 601ae08745Sheppo uint64_t cpu_rq_entries; 611ae08745Sheppo uint64_t cpu_nrq_entries; 62aaa10e67Sha uint64_t ncpu_guest_max; 631ae08745Sheppo 641ae08745Sheppo void fill_cpu(md_t *, mde_cookie_t); 651ae08745Sheppo 661ae08745Sheppo static uint64_t get_mmu_ctx_bits(md_t *, mde_cookie_t); 6705d3dc4bSpaulsan static uint64_t get_mmu_tsbs(md_t *, mde_cookie_t); 6805d3dc4bSpaulsan static uint64_t get_mmu_shcontexts(md_t *, mde_cookie_t); 691ae08745Sheppo static uint64_t get_cpu_pagesizes(md_t *, mde_cookie_t); 701ae08745Sheppo static char *construct_isalist(md_t *, mde_cookie_t, char **); 714bac2208Snarayan static void init_md_broken(md_t *, mde_cookie_t *); 721ae08745Sheppo static int get_l2_cache_info(md_t *, mde_cookie_t, uint64_t *, uint64_t *, 731ae08745Sheppo uint64_t *); 741ae08745Sheppo static void get_q_sizes(md_t *, mde_cookie_t); 751ae08745Sheppo static void get_va_bits(md_t *, mde_cookie_t); 761ae08745Sheppo static size_t get_ra_limit(md_t *); 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate uint64_t system_clock_freq; 797c478bd9Sstevel@tonic-gate uint_t niommu_tsbs = 0; 807c478bd9Sstevel@tonic-gate 81fedab560Sae /* prevent compilation with VAC defined */ 82fedab560Sae #ifdef VAC 83fedab560Sae #error "The sun4v architecture does not support VAC" 84fedab560Sae #endif 85fedab560Sae 86fedab560Sae #define S_VAC_SIZE MMU_PAGESIZE 87fedab560Sae #define S_VAC_SHIFT MMU_PAGESHIFT 88fedab560Sae 89fedab560Sae int vac_size = S_VAC_SIZE; 90fedab560Sae uint_t vac_mask = MMU_PAGEMASK & (S_VAC_SIZE - 1); 91fedab560Sae int vac_shift = S_VAC_SHIFT; 92fedab560Sae uintptr_t shm_alignment = S_VAC_SIZE; 93fedab560Sae 941ae08745Sheppo void 951ae08745Sheppo map_wellknown_devices() 961ae08745Sheppo { 971ae08745Sheppo } 987c478bd9Sstevel@tonic-gate 997c478bd9Sstevel@tonic-gate void 1001ae08745Sheppo fill_cpu(md_t *mdp, mde_cookie_t cpuc) 1017c478bd9Sstevel@tonic-gate { 1021ae08745Sheppo struct cpu_node *cpunode; 1031ae08745Sheppo uint64_t cpuid; 1041ae08745Sheppo uint64_t clk_freq; 1051ae08745Sheppo char *namebuf; 1061ae08745Sheppo char *namebufp; 1071ae08745Sheppo int namelen; 1081ae08745Sheppo uint64_t associativity = 0, linesize = 0, size = 0; 1091ae08745Sheppo 1101ae08745Sheppo if (md_get_prop_val(mdp, cpuc, "id", &cpuid)) { 1111ae08745Sheppo return; 1121ae08745Sheppo } 1137c478bd9Sstevel@tonic-gate 1144bac2208Snarayan /* All out-of-range cpus will be stopped later. */ 1151ae08745Sheppo if (cpuid >= NCPU) { 1161ae08745Sheppo cmn_err(CE_CONT, "fill_cpu: out of range cpuid %ld - " 1174bac2208Snarayan "cpu excluded from configuration\n", cpuid); 1181ae08745Sheppo 1191ae08745Sheppo return; 1201ae08745Sheppo } 1211ae08745Sheppo 1221ae08745Sheppo cpunode = &cpunodes[cpuid]; 1231ae08745Sheppo cpunode->cpuid = (int)cpuid; 1241ae08745Sheppo cpunode->device_id = cpuid; 1251ae08745Sheppo 1261ae08745Sheppo if (sizeof (cpunode->fru_fmri) > strlen(CPU_FRU_FMRI)) 1271ae08745Sheppo (void) strcpy(cpunode->fru_fmri, CPU_FRU_FMRI); 1281ae08745Sheppo 1291ae08745Sheppo if (md_get_prop_data(mdp, cpuc, 1301ae08745Sheppo "compatible", (uint8_t **)&namebuf, &namelen)) { 1311ae08745Sheppo cmn_err(CE_PANIC, "fill_cpu: Cannot read compatible " 1321ae08745Sheppo "property"); 1331ae08745Sheppo } 1341ae08745Sheppo namebufp = namebuf; 1351ae08745Sheppo if (strncmp(namebufp, "SUNW,", 5) == 0) 1361ae08745Sheppo namebufp += 5; 1371ae08745Sheppo if (strlen(namebufp) > sizeof (cpunode->name)) 1381ae08745Sheppo cmn_err(CE_PANIC, "Compatible property too big to " 1391ae08745Sheppo "fit into the cpunode name buffer"); 1401ae08745Sheppo (void) strcpy(cpunode->name, namebufp); 1411ae08745Sheppo 1421ae08745Sheppo if (md_get_prop_val(mdp, cpuc, 1431ae08745Sheppo "clock-frequency", &clk_freq)) { 1441ae08745Sheppo clk_freq = 0; 1451ae08745Sheppo } 1461ae08745Sheppo cpunode->clock_freq = clk_freq; 1471ae08745Sheppo 1481ae08745Sheppo ASSERT(cpunode->clock_freq != 0); 1497c478bd9Sstevel@tonic-gate /* 1501ae08745Sheppo * Compute scaling factor based on rate of %tick. This is used 1511ae08745Sheppo * to convert from ticks derived from %tick to nanoseconds. See 1521ae08745Sheppo * comment in sun4u/sys/clock.h for details. 1537c478bd9Sstevel@tonic-gate */ 1541ae08745Sheppo cpunode->tick_nsec_scale = (uint_t)(((uint64_t)NANOSEC << 1551ae08745Sheppo (32 - TICK_NSEC_SHIFT)) / cpunode->clock_freq); 1567c478bd9Sstevel@tonic-gate 1577c478bd9Sstevel@tonic-gate /* 1581ae08745Sheppo * The nodeid is not used in sun4v at all. Setting it 1591ae08745Sheppo * to positive value to make starting of slave CPUs 1601ae08745Sheppo * code happy. 1617c478bd9Sstevel@tonic-gate */ 1621ae08745Sheppo cpunode->nodeid = cpuid + 1; 1637c478bd9Sstevel@tonic-gate 1647c478bd9Sstevel@tonic-gate /* 1651ae08745Sheppo * Obtain the L2 cache information from MD. 1661ae08745Sheppo * If "Cache" node exists, then set L2 cache properties 1671ae08745Sheppo * as read from MD. 1681ae08745Sheppo * If node does not exists, then set the L2 cache properties 1691ae08745Sheppo * in individual CPU module. 1707c478bd9Sstevel@tonic-gate */ 1711ae08745Sheppo if ((!get_l2_cache_info(mdp, cpuc, 1721ae08745Sheppo &associativity, &size, &linesize)) || 1731ae08745Sheppo associativity == 0 || size == 0 || linesize == 0) { 1741ae08745Sheppo cpu_fiximp(cpunode); 1751ae08745Sheppo } else { 1761ae08745Sheppo /* 1771ae08745Sheppo * Do not expect L2 cache properties to be bigger 1781ae08745Sheppo * than 32-bit quantity. 1791ae08745Sheppo */ 1801ae08745Sheppo cpunode->ecache_associativity = (int)associativity; 1811ae08745Sheppo cpunode->ecache_size = (int)size; 1821ae08745Sheppo cpunode->ecache_linesize = (int)linesize; 1837c478bd9Sstevel@tonic-gate } 1841ae08745Sheppo 1851ae08745Sheppo cpunode->ecache_setsize = 1861ae08745Sheppo cpunode->ecache_size / cpunode->ecache_associativity; 1871ae08745Sheppo 188*59ac0c16Sdavemq /* 189*59ac0c16Sdavemq * Initialize the mapping for exec unit, chip and core. 190*59ac0c16Sdavemq */ 1911ae08745Sheppo cpunode->exec_unit_mapping = NO_EU_MAPPING_FOUND; 192*59ac0c16Sdavemq cpunode->l2_cache_mapping = NO_MAPPING_FOUND; 193*59ac0c16Sdavemq cpunode->core_mapping = NO_CORE_MAPPING_FOUND; 1941ae08745Sheppo 1951ae08745Sheppo if (ecache_setsize == 0) 1961ae08745Sheppo ecache_setsize = cpunode->ecache_setsize; 1971ae08745Sheppo if (ecache_alignsize == 0) 1981ae08745Sheppo ecache_alignsize = cpunode->ecache_linesize; 1991ae08745Sheppo 2007c478bd9Sstevel@tonic-gate } 2017c478bd9Sstevel@tonic-gate 2021ae08745Sheppo void 2031ae08745Sheppo empty_cpu(int cpuid) 2047c478bd9Sstevel@tonic-gate { 2051ae08745Sheppo bzero(&cpunodes[cpuid], sizeof (struct cpu_node)); 2061ae08745Sheppo } 2077c478bd9Sstevel@tonic-gate 208*59ac0c16Sdavemq /* 209*59ac0c16Sdavemq * Use L2 cache node to derive the chip mapping. 210*59ac0c16Sdavemq */ 211*59ac0c16Sdavemq void 212*59ac0c16Sdavemq setup_chip_mappings(md_t *mdp) 213*59ac0c16Sdavemq { 214*59ac0c16Sdavemq uint64_t ncache, ncpu; 215*59ac0c16Sdavemq mde_cookie_t *node, *cachelist; 216*59ac0c16Sdavemq int i, j; 217*59ac0c16Sdavemq processorid_t cpuid; 218*59ac0c16Sdavemq int idx = 0; 219*59ac0c16Sdavemq 220*59ac0c16Sdavemq ncache = md_alloc_scan_dag(mdp, md_root_node(mdp), "cache", 221*59ac0c16Sdavemq "fwd", &cachelist); 222*59ac0c16Sdavemq 223*59ac0c16Sdavemq /* 224*59ac0c16Sdavemq * The "cache" node is optional in MD, therefore ncaches can be 0. 225*59ac0c16Sdavemq */ 226*59ac0c16Sdavemq if (ncache < 1) { 227*59ac0c16Sdavemq return; 228*59ac0c16Sdavemq } 229*59ac0c16Sdavemq 230*59ac0c16Sdavemq for (i = 0; i < ncache; i++) { 231*59ac0c16Sdavemq uint64_t cache_level; 232*59ac0c16Sdavemq uint64_t lcpuid; 233*59ac0c16Sdavemq 234*59ac0c16Sdavemq if (md_get_prop_val(mdp, cachelist[i], "level", &cache_level)) 235*59ac0c16Sdavemq continue; 236*59ac0c16Sdavemq 237*59ac0c16Sdavemq if (cache_level != 2) 238*59ac0c16Sdavemq continue; 239*59ac0c16Sdavemq 240*59ac0c16Sdavemq /* 241*59ac0c16Sdavemq * Found a l2 cache node. Find out the cpu nodes it 242*59ac0c16Sdavemq * points to. 243*59ac0c16Sdavemq */ 244*59ac0c16Sdavemq ncpu = md_alloc_scan_dag(mdp, cachelist[i], "cpu", 245*59ac0c16Sdavemq "back", &node); 246*59ac0c16Sdavemq 247*59ac0c16Sdavemq if (ncpu < 1) 248*59ac0c16Sdavemq continue; 249*59ac0c16Sdavemq 250*59ac0c16Sdavemq for (j = 0; j < ncpu; j++) { 251*59ac0c16Sdavemq if (md_get_prop_val(mdp, node[j], "id", &lcpuid)) 252*59ac0c16Sdavemq continue; 253*59ac0c16Sdavemq if (lcpuid >= NCPU) 254*59ac0c16Sdavemq continue; 255*59ac0c16Sdavemq cpuid = (processorid_t)lcpuid; 256*59ac0c16Sdavemq cpunodes[cpuid].l2_cache_mapping = idx; 257*59ac0c16Sdavemq } 258*59ac0c16Sdavemq md_free_scan_dag(mdp, &node); 259*59ac0c16Sdavemq 260*59ac0c16Sdavemq idx++; 261*59ac0c16Sdavemq } 262*59ac0c16Sdavemq 263*59ac0c16Sdavemq md_free_scan_dag(mdp, &cachelist); 264*59ac0c16Sdavemq } 265*59ac0c16Sdavemq 2661ae08745Sheppo void 2671ae08745Sheppo setup_exec_unit_mappings(md_t *mdp) 2681ae08745Sheppo { 2691ae08745Sheppo uint64_t num, num_eunits; 2701ae08745Sheppo mde_cookie_t cpus_node; 2711ae08745Sheppo mde_cookie_t *node, *eunit; 2721ae08745Sheppo int idx, i, j; 2731ae08745Sheppo processorid_t cpuid; 2741ae08745Sheppo char *eunit_name = broken_md_flag ? "exec_unit" : "exec-unit"; 275fb2f18f8Sesaxe enum eu_type { INTEGER, FPU } etype; 2767c478bd9Sstevel@tonic-gate 2771ae08745Sheppo /* 2781ae08745Sheppo * Find the cpu integer exec units - and 2791ae08745Sheppo * setup the mappings appropriately. 2801ae08745Sheppo */ 2811ae08745Sheppo num = md_alloc_scan_dag(mdp, md_root_node(mdp), "cpus", "fwd", &node); 2821ae08745Sheppo if (num < 1) 2834bac2208Snarayan cmn_err(CE_PANIC, "No cpus node in machine description"); 2841ae08745Sheppo if (num > 1) 2851ae08745Sheppo cmn_err(CE_PANIC, "More than 1 cpus node in machine" 2861ae08745Sheppo " description"); 2871ae08745Sheppo 2881ae08745Sheppo cpus_node = node[0]; 2891ae08745Sheppo md_free_scan_dag(mdp, &node); 2901ae08745Sheppo 2911ae08745Sheppo num_eunits = md_alloc_scan_dag(mdp, cpus_node, eunit_name, 2921ae08745Sheppo "fwd", &eunit); 2931ae08745Sheppo if (num_eunits > 0) { 294fb2f18f8Sesaxe char *int_str = broken_md_flag ? "int" : "integer"; 295fb2f18f8Sesaxe char *fpu_str = "fp"; 2961ae08745Sheppo 2971ae08745Sheppo /* Spin through and find all the integer exec units */ 2981ae08745Sheppo for (i = 0; i < num_eunits; i++) { 2991ae08745Sheppo char *p; 3001ae08745Sheppo char *val; 3011ae08745Sheppo int vallen; 3021ae08745Sheppo uint64_t lcpuid; 3031ae08745Sheppo 304fb2f18f8Sesaxe /* ignore nodes with no type */ 3051ae08745Sheppo if (md_get_prop_data(mdp, eunit[i], "type", 306ad8d2eb8Szx (uint8_t **)&val, &vallen)) 307ad8d2eb8Szx continue; 3081ae08745Sheppo 3091ae08745Sheppo for (p = val; *p != '\0'; p += strlen(p) + 1) { 310fb2f18f8Sesaxe if (strcmp(p, int_str) == 0) { 311fb2f18f8Sesaxe etype = INTEGER; 3121ae08745Sheppo goto found; 313fb2f18f8Sesaxe } 314fb2f18f8Sesaxe if (strcmp(p, fpu_str) == 0) { 315fb2f18f8Sesaxe etype = FPU; 316fb2f18f8Sesaxe goto found; 317fb2f18f8Sesaxe } 3187c478bd9Sstevel@tonic-gate } 3191ae08745Sheppo 3201ae08745Sheppo continue; 3211ae08745Sheppo found: 3221ae08745Sheppo idx = NCPU + i; 3237c478bd9Sstevel@tonic-gate /* 3241ae08745Sheppo * find the cpus attached to this EU and 3251ae08745Sheppo * update their mapping indices 3267c478bd9Sstevel@tonic-gate */ 3271ae08745Sheppo num = md_alloc_scan_dag(mdp, eunit[i], "cpu", 3281ae08745Sheppo "back", &node); 3291ae08745Sheppo 3301ae08745Sheppo if (num < 1) 3311ae08745Sheppo cmn_err(CE_PANIC, "exec-unit node in MD" 3321ae08745Sheppo " not attached to a cpu node"); 3331ae08745Sheppo 3341ae08745Sheppo for (j = 0; j < num; j++) { 3351ae08745Sheppo if (md_get_prop_val(mdp, node[j], "id", 3361ae08745Sheppo &lcpuid)) 3371ae08745Sheppo continue; 3381ae08745Sheppo if (lcpuid >= NCPU) 3391ae08745Sheppo continue; 3401ae08745Sheppo cpuid = (processorid_t)lcpuid; 341fb2f18f8Sesaxe switch (etype) { 342fb2f18f8Sesaxe case INTEGER: 343fb2f18f8Sesaxe cpunodes[cpuid].exec_unit_mapping = idx; 344fb2f18f8Sesaxe break; 345fb2f18f8Sesaxe case FPU: 346fb2f18f8Sesaxe cpunodes[cpuid].fpu_mapping = idx; 347fb2f18f8Sesaxe break; 348fb2f18f8Sesaxe } 3491ae08745Sheppo } 3501ae08745Sheppo md_free_scan_dag(mdp, &node); 3517c478bd9Sstevel@tonic-gate } 3527c478bd9Sstevel@tonic-gate 3531ae08745Sheppo 3541ae08745Sheppo md_free_scan_dag(mdp, &eunit); 3557c478bd9Sstevel@tonic-gate } 3567c478bd9Sstevel@tonic-gate } 3577c478bd9Sstevel@tonic-gate 3581ae08745Sheppo /* 3591ae08745Sheppo * All the common setup of sun4v CPU modules is done by this routine. 3601ae08745Sheppo */ 3611ae08745Sheppo void 3621ae08745Sheppo cpu_setup_common(char **cpu_module_isa_set) 3637c478bd9Sstevel@tonic-gate { 3641ae08745Sheppo extern int mmu_exported_pagesize_mask; 3651ae08745Sheppo int nocpus, i; 3661ae08745Sheppo size_t ra_limit; 3671ae08745Sheppo mde_cookie_t *cpulist; 3681ae08745Sheppo md_t *mdp; 3691ae08745Sheppo 3701ae08745Sheppo if ((mdp = md_get_handle()) == NULL) 3711ae08745Sheppo cmn_err(CE_PANIC, "Unable to initialize machine description"); 3721ae08745Sheppo 3731ae08745Sheppo nocpus = md_alloc_scan_dag(mdp, 3741ae08745Sheppo md_root_node(mdp), "cpu", "fwd", &cpulist); 3751ae08745Sheppo if (nocpus < 1) { 3761ae08745Sheppo cmn_err(CE_PANIC, "cpu_common_setup: cpulist allocation " 3771ae08745Sheppo "failed or incorrect number of CPUs in MD"); 3781ae08745Sheppo } 3797c478bd9Sstevel@tonic-gate 3804bac2208Snarayan init_md_broken(mdp, cpulist); 3814bac2208Snarayan 3821ae08745Sheppo if (use_page_coloring) { 3831ae08745Sheppo do_pg_coloring = 1; 3841ae08745Sheppo } 3851ae08745Sheppo 3861ae08745Sheppo /* 3871e2e7a75Shuah * Get the valid mmu page sizes mask, Q sizes and isalist/r 3881ae08745Sheppo * from the MD for the first available CPU in cpulist. 3891e2e7a75Shuah * 3901e2e7a75Shuah * Do not expect the MMU page sizes mask to be more than 32-bit. 3911ae08745Sheppo */ 3921ae08745Sheppo mmu_exported_pagesize_mask = (int)get_cpu_pagesizes(mdp, cpulist[0]); 3931ae08745Sheppo 39405d3dc4bSpaulsan /* 39505d3dc4bSpaulsan * Get the number of contexts and tsbs supported. 39605d3dc4bSpaulsan */ 39705d3dc4bSpaulsan if (get_mmu_shcontexts(mdp, cpulist[0]) >= MIN_NSHCONTEXTS && 39805d3dc4bSpaulsan get_mmu_tsbs(mdp, cpulist[0]) >= MIN_NTSBS) { 39905d3dc4bSpaulsan shctx_on = 1; 40005d3dc4bSpaulsan } 40105d3dc4bSpaulsan 4021ae08745Sheppo for (i = 0; i < nocpus; i++) 4031ae08745Sheppo fill_cpu(mdp, cpulist[i]); 4041ae08745Sheppo 405*59ac0c16Sdavemq setup_chip_mappings(mdp); 4061ae08745Sheppo setup_exec_unit_mappings(mdp); 4071ae08745Sheppo 4081ae08745Sheppo /* 4091ae08745Sheppo * If MD is broken then append the passed ISA set, 4101ae08745Sheppo * otherwise trust the MD. 4111ae08745Sheppo */ 4121ae08745Sheppo 4131ae08745Sheppo if (broken_md_flag) 4141ae08745Sheppo isa_list = construct_isalist(mdp, cpulist[0], 4151ae08745Sheppo cpu_module_isa_set); 4161ae08745Sheppo else 4171ae08745Sheppo isa_list = construct_isalist(mdp, cpulist[0], NULL); 4181ae08745Sheppo 4191ae08745Sheppo get_q_sizes(mdp, cpulist[0]); 4201ae08745Sheppo 4211ae08745Sheppo get_va_bits(mdp, cpulist[0]); 4221ae08745Sheppo 4231ae08745Sheppo /* 4241ae08745Sheppo * ra_limit is the highest real address in the machine. 4251ae08745Sheppo */ 4261ae08745Sheppo ra_limit = get_ra_limit(mdp); 4271ae08745Sheppo 4281ae08745Sheppo md_free_scan_dag(mdp, &cpulist); 4291ae08745Sheppo 4301ae08745Sheppo (void) md_fini_handle(mdp); 4311ae08745Sheppo 4321ae08745Sheppo /* 4331ae08745Sheppo * Block stores invalidate all pages of the d$ so pagecopy 4341ae08745Sheppo * et. al. do not need virtual translations with virtual 4351ae08745Sheppo * coloring taken into consideration. 4361ae08745Sheppo */ 4371ae08745Sheppo pp_consistent_coloring = 0; 4381ae08745Sheppo 4391ae08745Sheppo /* 4401ae08745Sheppo * The kpm mapping window. 4411ae08745Sheppo * kpm_size: 4421ae08745Sheppo * The size of a single kpm range. 4431ae08745Sheppo * The overall size will be: kpm_size * vac_colors. 4441ae08745Sheppo * kpm_vbase: 4451ae08745Sheppo * The virtual start address of the kpm range within the kernel 4461ae08745Sheppo * virtual address space. kpm_vbase has to be kpm_size aligned. 4471ae08745Sheppo */ 4481ae08745Sheppo 4491ae08745Sheppo /* 4501ae08745Sheppo * Make kpm_vbase, kpm_size aligned to kpm_size_shift. 4511ae08745Sheppo * To do this find the nearest power of 2 size that the 4521ae08745Sheppo * actual ra_limit fits within. 4531ae08745Sheppo * If it is an even power of two use that, otherwise use the 4541ae08745Sheppo * next power of two larger than ra_limit. 4551ae08745Sheppo */ 4561ae08745Sheppo 4571ae08745Sheppo ASSERT(ra_limit != 0); 4581ae08745Sheppo 4591ae08745Sheppo kpm_size_shift = (ra_limit & (ra_limit - 1)) != 0 ? 460ad8d2eb8Szx highbit(ra_limit) : highbit(ra_limit) - 1; 4611ae08745Sheppo 4621ae08745Sheppo /* 4631ae08745Sheppo * No virtual caches on sun4v so size matches size shift 4641ae08745Sheppo */ 4651ae08745Sheppo kpm_size = 1ul << kpm_size_shift; 4661ae08745Sheppo 4671ae08745Sheppo if (va_bits < VA_ADDRESS_SPACE_BITS) { 4687c478bd9Sstevel@tonic-gate /* 4691ae08745Sheppo * In case of VA hole 4701ae08745Sheppo * kpm_base = hole_end + 1TB 4711ae08745Sheppo * Starting 1TB beyond where VA hole ends because on Niagara 4721ae08745Sheppo * processor software must not use pages within 4GB of the 4731ae08745Sheppo * VA hole as instruction pages to avoid problems with 4741ae08745Sheppo * prefetching into the VA hole. 4757c478bd9Sstevel@tonic-gate */ 4761ae08745Sheppo kpm_vbase = (caddr_t)((0ull - (1ull << (va_bits - 1))) + 4771ae08745Sheppo (1ull << 40)); 4781ae08745Sheppo } else { /* Number of VA bits 64 ... no VA hole */ 4791ae08745Sheppo kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8 EB */ 4807c478bd9Sstevel@tonic-gate } 4811ae08745Sheppo 4821ae08745Sheppo /* 4831ae08745Sheppo * The traptrace code uses either %tick or %stick for 4841ae08745Sheppo * timestamping. The sun4v require use of %stick. 4851ae08745Sheppo */ 4861ae08745Sheppo traptrace_use_stick = 1; 4877c478bd9Sstevel@tonic-gate } 4887c478bd9Sstevel@tonic-gate 4891ae08745Sheppo /* 4901ae08745Sheppo * Get the nctxs from MD. If absent panic. 4911ae08745Sheppo */ 4921ae08745Sheppo static uint64_t 4931ae08745Sheppo get_mmu_ctx_bits(md_t *mdp, mde_cookie_t cpu_node_cookie) 4947c478bd9Sstevel@tonic-gate { 4951ae08745Sheppo uint64_t ctx_bits; 4967c478bd9Sstevel@tonic-gate 4971ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#context-bits", 4981ae08745Sheppo &ctx_bits)) 4991ae08745Sheppo ctx_bits = 0; 5007c478bd9Sstevel@tonic-gate 5011ae08745Sheppo if (ctx_bits < MIN_NCTXS_BITS || ctx_bits > MAX_NCTXS_BITS) 5021ae08745Sheppo cmn_err(CE_PANIC, "Incorrect %ld number of contexts bits " 5031ae08745Sheppo "returned by MD", ctx_bits); 5047c478bd9Sstevel@tonic-gate 5051ae08745Sheppo return (ctx_bits); 5061ae08745Sheppo } 5077c478bd9Sstevel@tonic-gate 50805d3dc4bSpaulsan /* 50905d3dc4bSpaulsan * Get the number of tsbs from MD. If absent the default value is 0. 51005d3dc4bSpaulsan */ 51105d3dc4bSpaulsan static uint64_t 51205d3dc4bSpaulsan get_mmu_tsbs(md_t *mdp, mde_cookie_t cpu_node_cookie) 51305d3dc4bSpaulsan { 51405d3dc4bSpaulsan uint64_t number_tsbs; 51505d3dc4bSpaulsan 51605d3dc4bSpaulsan if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-max-#tsbs", 51705d3dc4bSpaulsan &number_tsbs)) 51805d3dc4bSpaulsan number_tsbs = 0; 51905d3dc4bSpaulsan 52005d3dc4bSpaulsan return (number_tsbs); 52105d3dc4bSpaulsan } 52205d3dc4bSpaulsan 52305d3dc4bSpaulsan /* 52405d3dc4bSpaulsan * Get the number of shared contexts from MD. This property more accurately 52505d3dc4bSpaulsan * describes the total number of contexts available, not just "shared contexts". 52605d3dc4bSpaulsan * If absent the default value is 1, 52705d3dc4bSpaulsan * 52805d3dc4bSpaulsan */ 52905d3dc4bSpaulsan static uint64_t 53005d3dc4bSpaulsan get_mmu_shcontexts(md_t *mdp, mde_cookie_t cpu_node_cookie) 53105d3dc4bSpaulsan { 53205d3dc4bSpaulsan uint64_t number_contexts; 53305d3dc4bSpaulsan 53405d3dc4bSpaulsan if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#shared-contexts", 53505d3dc4bSpaulsan &number_contexts)) 53605d3dc4bSpaulsan number_contexts = 0; 53705d3dc4bSpaulsan 53805d3dc4bSpaulsan return (number_contexts); 53905d3dc4bSpaulsan } 54005d3dc4bSpaulsan 5411ae08745Sheppo /* 5421ae08745Sheppo * Initalize supported page sizes information. 5431ae08745Sheppo * Set to 0, if the page sizes mask information is absent in MD. 5441ae08745Sheppo */ 5451ae08745Sheppo static uint64_t 5461ae08745Sheppo get_cpu_pagesizes(md_t *mdp, mde_cookie_t cpu_node_cookie) 5471ae08745Sheppo { 5481ae08745Sheppo uint64_t mmu_page_size_list; 5497c478bd9Sstevel@tonic-gate 5501ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-page-size-list", 5511ae08745Sheppo &mmu_page_size_list)) 5521ae08745Sheppo mmu_page_size_list = 0; 5531ae08745Sheppo 5541ae08745Sheppo if (mmu_page_size_list == 0 || mmu_page_size_list > MAX_PAGESIZE_MASK) 5551ae08745Sheppo cmn_err(CE_PANIC, "Incorrect 0x%lx pagesize mask returned" 5561ae08745Sheppo "by MD", mmu_page_size_list); 5571ae08745Sheppo 5581ae08745Sheppo return (mmu_page_size_list); 5591ae08745Sheppo } 5601ae08745Sheppo 5611ae08745Sheppo /* 5621ae08745Sheppo * This routine gets the isalist information from MD and appends 5631ae08745Sheppo * the CPU module ISA set if required. 5641ae08745Sheppo */ 5651ae08745Sheppo static char * 5661ae08745Sheppo construct_isalist(md_t *mdp, mde_cookie_t cpu_node_cookie, 5671ae08745Sheppo char **cpu_module_isa_set) 5681ae08745Sheppo { 5691ae08745Sheppo extern int at_flags; 5701ae08745Sheppo char *md_isalist; 5711ae08745Sheppo int md_isalen; 5721ae08745Sheppo char *isabuf; 5731ae08745Sheppo int isalen; 5741ae08745Sheppo char **isa_set; 5751ae08745Sheppo char *p, *q; 5761ae08745Sheppo int cpu_module_isalen = 0, found = 0; 5771ae08745Sheppo 5781ae08745Sheppo (void) md_get_prop_data(mdp, cpu_node_cookie, 5791ae08745Sheppo "isalist", (uint8_t **)&isabuf, &isalen); 5807c478bd9Sstevel@tonic-gate 5817c478bd9Sstevel@tonic-gate /* 5821ae08745Sheppo * We support binaries for all the cpus that have shipped so far. 5831ae08745Sheppo * The kernel emulates instructions that are not supported by hardware. 5847c478bd9Sstevel@tonic-gate */ 5851ae08745Sheppo at_flags = EF_SPARC_SUN_US3 | EF_SPARC_32PLUS | EF_SPARC_SUN_US1; 5867c478bd9Sstevel@tonic-gate 5871ae08745Sheppo /* 5881ae08745Sheppo * Construct the space separated isa_list. 5891ae08745Sheppo */ 5901ae08745Sheppo if (cpu_module_isa_set != NULL) { 5911ae08745Sheppo for (isa_set = cpu_module_isa_set; *isa_set != NULL; 5921ae08745Sheppo isa_set++) { 5931ae08745Sheppo cpu_module_isalen += strlen(*isa_set); 5941ae08745Sheppo cpu_module_isalen++; /* for space character */ 5951ae08745Sheppo } 5961ae08745Sheppo } 5977c478bd9Sstevel@tonic-gate 5981ae08745Sheppo /* 5991ae08745Sheppo * Allocate the buffer of MD isa buffer length + CPU module 6001ae08745Sheppo * isa buffer length. 6011ae08745Sheppo */ 6021ae08745Sheppo md_isalen = isalen + cpu_module_isalen + 2; 6031ae08745Sheppo md_isalist = (char *)prom_alloc((caddr_t)0, md_isalen, 0); 6041ae08745Sheppo if (md_isalist == NULL) 6051ae08745Sheppo cmn_err(CE_PANIC, "construct_isalist: Allocation failed for " 6061ae08745Sheppo "md_isalist"); 6071ae08745Sheppo 6081ae08745Sheppo md_isalist[0] = '\0'; /* create an empty string to start */ 6091ae08745Sheppo for (p = isabuf, q = p + isalen; p < q; p += strlen(p) + 1) { 6101ae08745Sheppo (void) strlcat(md_isalist, p, md_isalen); 6111ae08745Sheppo (void) strcat(md_isalist, " "); 6121ae08745Sheppo } 6137c478bd9Sstevel@tonic-gate 6147c478bd9Sstevel@tonic-gate /* 6151ae08745Sheppo * Check if the isa_set is present in isalist returned by MD. 6161ae08745Sheppo * If yes, then no need to append it, if no then append it to 6171ae08745Sheppo * isalist returned by MD. 6187c478bd9Sstevel@tonic-gate */ 6191ae08745Sheppo if (cpu_module_isa_set != NULL) { 6201ae08745Sheppo for (isa_set = cpu_module_isa_set; *isa_set != NULL; 6211ae08745Sheppo isa_set++) { 6221ae08745Sheppo found = 0; 6231ae08745Sheppo for (p = isabuf, q = p + isalen; p < q; 6241ae08745Sheppo p += strlen(p) + 1) { 6251ae08745Sheppo if (strcmp(p, *isa_set) == 0) { 6261ae08745Sheppo found = 1; 6271ae08745Sheppo break; 6281ae08745Sheppo } 6291ae08745Sheppo } 6301ae08745Sheppo if (!found) { 6311ae08745Sheppo (void) strlcat(md_isalist, *isa_set, md_isalen); 6321ae08745Sheppo (void) strcat(md_isalist, " "); 6331ae08745Sheppo } 6341ae08745Sheppo } 6351ae08745Sheppo } 6361ae08745Sheppo 6371ae08745Sheppo /* Get rid of any trailing white spaces */ 6381ae08745Sheppo md_isalist[strlen(md_isalist) - 1] = '\0'; 6391ae08745Sheppo 6401ae08745Sheppo return (md_isalist); 6417c478bd9Sstevel@tonic-gate } 6427c478bd9Sstevel@tonic-gate 6431ae08745Sheppo uint64_t 6441ae08745Sheppo get_ra_limit(md_t *mdp) 6451ae08745Sheppo { 6461ae08745Sheppo mde_cookie_t *mem_list; 6471ae08745Sheppo mde_cookie_t *mblock_list; 6481ae08745Sheppo int i; 6491ae08745Sheppo int memnodes; 6501ae08745Sheppo int nmblock; 6511ae08745Sheppo uint64_t base; 6521ae08745Sheppo uint64_t size; 6531ae08745Sheppo uint64_t ra_limit = 0, new_limit = 0; 6541ae08745Sheppo 6551ae08745Sheppo memnodes = md_alloc_scan_dag(mdp, 6561ae08745Sheppo md_root_node(mdp), "memory", "fwd", &mem_list); 6571ae08745Sheppo 6581ae08745Sheppo ASSERT(memnodes == 1); 6591ae08745Sheppo 6601ae08745Sheppo nmblock = md_alloc_scan_dag(mdp, 6611ae08745Sheppo mem_list[0], "mblock", "fwd", &mblock_list); 6621ae08745Sheppo if (nmblock < 1) 6631ae08745Sheppo cmn_err(CE_PANIC, "cannot find mblock nodes in MD"); 6641ae08745Sheppo 6651ae08745Sheppo for (i = 0; i < nmblock; i++) { 6661ae08745Sheppo if (md_get_prop_val(mdp, mblock_list[i], "base", &base)) 6671ae08745Sheppo cmn_err(CE_PANIC, "base property missing from MD" 6681ae08745Sheppo " mblock node"); 6691ae08745Sheppo if (md_get_prop_val(mdp, mblock_list[i], "size", &size)) 6701ae08745Sheppo cmn_err(CE_PANIC, "size property missing from MD" 6711ae08745Sheppo " mblock node"); 6721ae08745Sheppo 6731ae08745Sheppo ASSERT(size != 0); 6741ae08745Sheppo 6751ae08745Sheppo new_limit = base + size; 6761ae08745Sheppo 6771ae08745Sheppo if (base > new_limit) 6781ae08745Sheppo cmn_err(CE_PANIC, "mblock in MD wrapped around"); 6791ae08745Sheppo 6801ae08745Sheppo if (new_limit > ra_limit) 681ad8d2eb8Szx ra_limit = new_limit; 6821ae08745Sheppo } 6831ae08745Sheppo 6841ae08745Sheppo ASSERT(ra_limit != 0); 6851ae08745Sheppo 6861ae08745Sheppo if (ra_limit > MAX_REAL_ADDRESS) { 6871ae08745Sheppo cmn_err(CE_WARN, "Highest real address in MD too large" 6881ae08745Sheppo " clipping to %llx\n", MAX_REAL_ADDRESS); 6891ae08745Sheppo ra_limit = MAX_REAL_ADDRESS; 6901ae08745Sheppo } 6911ae08745Sheppo 6921ae08745Sheppo md_free_scan_dag(mdp, &mblock_list); 6931ae08745Sheppo 6941ae08745Sheppo md_free_scan_dag(mdp, &mem_list); 6951ae08745Sheppo 6961ae08745Sheppo return (ra_limit); 6971ae08745Sheppo } 6987c478bd9Sstevel@tonic-gate 6997c478bd9Sstevel@tonic-gate /* 7001ae08745Sheppo * This routine sets the globals for CPU and DEV mondo queue entries and 7011ae08745Sheppo * resumable and non-resumable error queue entries. 7024bac2208Snarayan * 7034bac2208Snarayan * First, look up the number of bits available to pass an entry number. 7044bac2208Snarayan * This can vary by platform and may result in allocating an unreasonably 7054bac2208Snarayan * (or impossibly) large amount of memory for the corresponding table, 7064bac2208Snarayan * so we clamp it by 'max_entries'. If the prop is missing, use 7074bac2208Snarayan * 'default_entries'. 7087c478bd9Sstevel@tonic-gate */ 7091ae08745Sheppo static uint64_t 7101ae08745Sheppo get_single_q_size(md_t *mdp, mde_cookie_t cpu_node_cookie, 7114bac2208Snarayan char *qnamep, uint64_t default_entries, uint64_t max_entries) 7121ae08745Sheppo { 7131ae08745Sheppo uint64_t entries; 7141ae08745Sheppo 7154bac2208Snarayan if (default_entries > max_entries) 7164bac2208Snarayan cmn_err(CE_CONT, "!get_single_q_size: dflt %ld > " 7174bac2208Snarayan "max %ld for %s\n", default_entries, max_entries, qnamep); 7184bac2208Snarayan 7191ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, qnamep, &entries)) { 7201ae08745Sheppo if (!broken_md_flag) 7211ae08745Sheppo cmn_err(CE_PANIC, "Missing %s property in MD cpu node", 722ad8d2eb8Szx qnamep); 7231ae08745Sheppo entries = default_entries; 7241ae08745Sheppo } else { 7251ae08745Sheppo entries = 1 << entries; 7261ae08745Sheppo } 7274bac2208Snarayan 7284bac2208Snarayan entries = MIN(entries, max_entries); 7294bac2208Snarayan 7301ae08745Sheppo return (entries); 7311ae08745Sheppo } 7321ae08745Sheppo 7334bac2208Snarayan /* Scaling constant used to compute size of cpu mondo queue */ 7344bac2208Snarayan #define CPU_MONDO_Q_MULTIPLIER 8 7351ae08745Sheppo 7367c478bd9Sstevel@tonic-gate static void 7371ae08745Sheppo get_q_sizes(md_t *mdp, mde_cookie_t cpu_node_cookie) 7387c478bd9Sstevel@tonic-gate { 7394bac2208Snarayan uint64_t max_qsize; 7404bac2208Snarayan mde_cookie_t *platlist; 7414bac2208Snarayan int nrnode; 7424bac2208Snarayan 7434bac2208Snarayan /* 7444bac2208Snarayan * Compute the maximum number of entries for the cpu mondo queue. 7454bac2208Snarayan * Use the appropriate property in the platform node, if it is 7464bac2208Snarayan * available. Else, base it on NCPU. 7474bac2208Snarayan */ 7484bac2208Snarayan nrnode = md_alloc_scan_dag(mdp, 7494bac2208Snarayan md_root_node(mdp), "platform", "fwd", &platlist); 7504bac2208Snarayan 7514bac2208Snarayan ASSERT(nrnode == 1); 7524bac2208Snarayan 753aaa10e67Sha ncpu_guest_max = NCPU; 754aaa10e67Sha (void) md_get_prop_val(mdp, platlist[0], "max-cpus", &ncpu_guest_max); 755aaa10e67Sha max_qsize = ncpu_guest_max * CPU_MONDO_Q_MULTIPLIER; 7564bac2208Snarayan 7574bac2208Snarayan md_free_scan_dag(mdp, &platlist); 7584bac2208Snarayan 7591ae08745Sheppo cpu_q_entries = get_single_q_size(mdp, cpu_node_cookie, 7604bac2208Snarayan "q-cpu-mondo-#bits", DEFAULT_CPU_Q_ENTRIES, max_qsize); 7611ae08745Sheppo 7621ae08745Sheppo dev_q_entries = get_single_q_size(mdp, cpu_node_cookie, 763b0fc0e77Sgovinda "q-dev-mondo-#bits", DEFAULT_DEV_Q_ENTRIES, MAXIVNUM); 7641ae08745Sheppo 7651ae08745Sheppo cpu_rq_entries = get_single_q_size(mdp, cpu_node_cookie, 7664bac2208Snarayan "q-resumable-#bits", CPU_RQ_ENTRIES, MAX_CPU_RQ_ENTRIES); 7671ae08745Sheppo 7681ae08745Sheppo cpu_nrq_entries = get_single_q_size(mdp, cpu_node_cookie, 7694bac2208Snarayan "q-nonresumable-#bits", CPU_NRQ_ENTRIES, MAX_CPU_NRQ_ENTRIES); 7701ae08745Sheppo } 7711ae08745Sheppo 7721ae08745Sheppo 7731ae08745Sheppo static void 7741ae08745Sheppo get_va_bits(md_t *mdp, mde_cookie_t cpu_node_cookie) 7751ae08745Sheppo { 7761ae08745Sheppo uint64_t value = VA_ADDRESS_SPACE_BITS; 7771ae08745Sheppo 7781ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#va-bits", &value)) 7791ae08745Sheppo cmn_err(CE_PANIC, "mmu-#va-bits property not found in MD"); 7807c478bd9Sstevel@tonic-gate 7817c478bd9Sstevel@tonic-gate 7821ae08745Sheppo if (value == 0 || value > VA_ADDRESS_SPACE_BITS) 7831ae08745Sheppo cmn_err(CE_PANIC, "Incorrect number of va bits in MD"); 7847c478bd9Sstevel@tonic-gate 7851ae08745Sheppo /* Do not expect number of VA bits to be more than 32-bit quantity */ 7867c478bd9Sstevel@tonic-gate 7871ae08745Sheppo va_bits = (int)value; 7887c478bd9Sstevel@tonic-gate 7897c478bd9Sstevel@tonic-gate /* 7901ae08745Sheppo * Correct the value for VA bits on UltraSPARC-T1 based systems 7911ae08745Sheppo * in case of broken MD. 7927c478bd9Sstevel@tonic-gate */ 7931ae08745Sheppo if (broken_md_flag) 7941ae08745Sheppo va_bits = DEFAULT_VA_ADDRESS_SPACE_BITS; 7957c478bd9Sstevel@tonic-gate } 7967c478bd9Sstevel@tonic-gate 7971ae08745Sheppo /* 7981ae08745Sheppo * This routine returns the L2 cache information such as -- associativity, 7991ae08745Sheppo * size and linesize. 8001ae08745Sheppo */ 8011ae08745Sheppo static int 8021ae08745Sheppo get_l2_cache_info(md_t *mdp, mde_cookie_t cpu_node_cookie, 8031ae08745Sheppo uint64_t *associativity, uint64_t *size, uint64_t *linesize) 8041ae08745Sheppo { 8051ae08745Sheppo mde_cookie_t *cachelist; 8061ae08745Sheppo int ncaches, i; 8071ae08745Sheppo uint64_t max_level; 8081ae08745Sheppo 8091ae08745Sheppo ncaches = md_alloc_scan_dag(mdp, cpu_node_cookie, "cache", 8101ae08745Sheppo "fwd", &cachelist); 8111ae08745Sheppo /* 8121ae08745Sheppo * The "cache" node is optional in MD, therefore ncaches can be 0. 8131ae08745Sheppo */ 8141ae08745Sheppo if (ncaches < 1) { 8151ae08745Sheppo return (0); 8161ae08745Sheppo } 8171ae08745Sheppo 8181ae08745Sheppo max_level = 0; 8191ae08745Sheppo for (i = 0; i < ncaches; i++) { 8201ae08745Sheppo uint64_t cache_level; 8211ae08745Sheppo uint64_t local_assoc; 8221ae08745Sheppo uint64_t local_size; 8231ae08745Sheppo uint64_t local_lsize; 8241ae08745Sheppo 8251ae08745Sheppo if (md_get_prop_val(mdp, cachelist[i], "level", &cache_level)) 8261ae08745Sheppo continue; 8271ae08745Sheppo 8281ae08745Sheppo if (cache_level <= max_level) continue; 8291ae08745Sheppo 8301ae08745Sheppo /* If properties are missing from this cache ignore it */ 8311ae08745Sheppo 8321ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 8331ae08745Sheppo "associativity", &local_assoc))) { 8341ae08745Sheppo continue; 8351ae08745Sheppo } 8361ae08745Sheppo 8371ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 8381ae08745Sheppo "size", &local_size))) { 8391ae08745Sheppo continue; 8401ae08745Sheppo } 8411ae08745Sheppo 8421ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 8431ae08745Sheppo "line-size", &local_lsize))) { 8441ae08745Sheppo continue; 8451ae08745Sheppo } 8461ae08745Sheppo 8471ae08745Sheppo max_level = cache_level; 8481ae08745Sheppo *associativity = local_assoc; 8491ae08745Sheppo *size = local_size; 8501ae08745Sheppo *linesize = local_lsize; 8511ae08745Sheppo } 8527c478bd9Sstevel@tonic-gate 8531ae08745Sheppo md_free_scan_dag(mdp, &cachelist); 8541ae08745Sheppo 8551ae08745Sheppo return ((max_level > 0) ? 1 : 0); 8561ae08745Sheppo } 8571ae08745Sheppo 8584bac2208Snarayan 8591ae08745Sheppo /* 8604bac2208Snarayan * Set the broken_md_flag to 1 if the MD doesn't have 8614bac2208Snarayan * the domaining-enabled property in the platform node and the 8624bac2208Snarayan * platform uses the UltraSPARC-T1 cpu. This flag is used to 8634bac2208Snarayan * workaround some of the incorrect MD properties. 8641ae08745Sheppo */ 8651ae08745Sheppo static void 8664bac2208Snarayan init_md_broken(md_t *mdp, mde_cookie_t *cpulist) 8677c478bd9Sstevel@tonic-gate { 8681ae08745Sheppo int nrnode; 8691ae08745Sheppo mde_cookie_t *platlist, rootnode; 8701ae08745Sheppo uint64_t val = 0; 8714bac2208Snarayan char *namebuf; 8724bac2208Snarayan int namelen; 8731ae08745Sheppo 8741ae08745Sheppo rootnode = md_root_node(mdp); 8751ae08745Sheppo ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 8764bac2208Snarayan ASSERT(cpulist); 8771ae08745Sheppo 8784bac2208Snarayan nrnode = md_alloc_scan_dag(mdp, rootnode, "platform", "fwd", 8791ae08745Sheppo &platlist); 8801ae08745Sheppo 881f273041fSjm if (nrnode < 1) 882f273041fSjm cmn_err(CE_PANIC, "init_md_broken: platform node missing"); 8831ae08745Sheppo 8844bac2208Snarayan if (md_get_prop_data(mdp, cpulist[0], 8854bac2208Snarayan "compatible", (uint8_t **)&namebuf, &namelen)) { 8864bac2208Snarayan cmn_err(CE_PANIC, "init_md_broken: " 8874bac2208Snarayan "Cannot read 'compatible' property of 'cpu' node"); 8884bac2208Snarayan } 8897c478bd9Sstevel@tonic-gate 8904bac2208Snarayan if (md_get_prop_val(mdp, platlist[0], 891ad8d2eb8Szx "domaining-enabled", &val) == -1 && 8924bac2208Snarayan strcmp(namebuf, "SUNW,UltraSPARC-T1") == 0) 8931ae08745Sheppo broken_md_flag = 1; 8941ae08745Sheppo 8951ae08745Sheppo md_free_scan_dag(mdp, &platlist); 8967c478bd9Sstevel@tonic-gate } 897