17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51ae08745Sheppo * Common Development and Distribution License (the "License"). 61ae08745Sheppo * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate #include <sys/errno.h> 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/param.h> 317c478bd9Sstevel@tonic-gate #include <sys/cpu.h> 327c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 337c478bd9Sstevel@tonic-gate #include <sys/clock.h> 347c478bd9Sstevel@tonic-gate #include <sys/promif.h> 357c478bd9Sstevel@tonic-gate #include <sys/promimpl.h> 367c478bd9Sstevel@tonic-gate #include <sys/systm.h> 377c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 387c478bd9Sstevel@tonic-gate #include <sys/debug.h> 397c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 407c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 417c478bd9Sstevel@tonic-gate #include <sys/cpu_module.h> 427c478bd9Sstevel@tonic-gate #include <sys/kobj.h> 437c478bd9Sstevel@tonic-gate #include <sys/cmp.h> 447c478bd9Sstevel@tonic-gate #include <sys/async.h> 457c478bd9Sstevel@tonic-gate #include <vm/page.h> 461ae08745Sheppo #include <vm/hat_sfmmu.h> 471ae08745Sheppo #include <sys/sysmacros.h> 481ae08745Sheppo #include <sys/mach_descrip.h> 491ae08745Sheppo #include <sys/mdesc.h> 501ae08745Sheppo #include <sys/archsystm.h> 511ae08745Sheppo #include <sys/error.h> 521ae08745Sheppo #include <sys/mmu.h> 531ae08745Sheppo #include <sys/bitmap.h> 544bac2208Snarayan #include <sys/intreg.h> 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate int ncpunode; 577c478bd9Sstevel@tonic-gate struct cpu_node cpunodes[NCPU]; 587c478bd9Sstevel@tonic-gate 591ae08745Sheppo uint64_t cpu_q_entries; 601ae08745Sheppo uint64_t dev_q_entries; 611ae08745Sheppo uint64_t cpu_rq_entries; 621ae08745Sheppo uint64_t cpu_nrq_entries; 63aaa10e67Sha uint64_t ncpu_guest_max; 641ae08745Sheppo 651ae08745Sheppo void fill_cpu(md_t *, mde_cookie_t); 661ae08745Sheppo 671ae08745Sheppo static uint64_t get_mmu_ctx_bits(md_t *, mde_cookie_t); 68*05d3dc4bSpaulsan static uint64_t get_mmu_tsbs(md_t *, mde_cookie_t); 69*05d3dc4bSpaulsan static uint64_t get_mmu_shcontexts(md_t *, mde_cookie_t); 701ae08745Sheppo static uint64_t get_cpu_pagesizes(md_t *, mde_cookie_t); 711ae08745Sheppo static char *construct_isalist(md_t *, mde_cookie_t, char **); 721ae08745Sheppo static void set_at_flags(char *, int, char **); 734bac2208Snarayan static void init_md_broken(md_t *, mde_cookie_t *); 741ae08745Sheppo static int get_l2_cache_info(md_t *, mde_cookie_t, uint64_t *, uint64_t *, 751ae08745Sheppo uint64_t *); 761ae08745Sheppo static id_t get_exec_unit_mapping(md_t *, mde_cookie_t, mde_cookie_t *); 771ae08745Sheppo static int find_exec_unit_id(mde_cookie_t, mde_cookie_t *); 781ae08745Sheppo static void get_q_sizes(md_t *, mde_cookie_t); 791ae08745Sheppo static void get_va_bits(md_t *, mde_cookie_t); 801ae08745Sheppo static size_t get_ra_limit(md_t *); 817c478bd9Sstevel@tonic-gate 827c478bd9Sstevel@tonic-gate uint64_t system_clock_freq; 837c478bd9Sstevel@tonic-gate int niobus = 0; 847c478bd9Sstevel@tonic-gate uint_t niommu_tsbs = 0; 857c478bd9Sstevel@tonic-gate 86fedab560Sae /* prevent compilation with VAC defined */ 87fedab560Sae #ifdef VAC 88fedab560Sae #error "The sun4v architecture does not support VAC" 89fedab560Sae #endif 90fedab560Sae 91fedab560Sae #define S_VAC_SIZE MMU_PAGESIZE 92fedab560Sae #define S_VAC_SHIFT MMU_PAGESHIFT 93fedab560Sae 94fedab560Sae int vac_size = S_VAC_SIZE; 95fedab560Sae uint_t vac_mask = MMU_PAGEMASK & (S_VAC_SIZE - 1); 96fedab560Sae int vac_shift = S_VAC_SHIFT; 97fedab560Sae uintptr_t shm_alignment = S_VAC_SIZE; 98fedab560Sae 991ae08745Sheppo void 1001ae08745Sheppo map_wellknown_devices() 1011ae08745Sheppo { 1021ae08745Sheppo } 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate void 1051ae08745Sheppo fill_cpu(md_t *mdp, mde_cookie_t cpuc) 1067c478bd9Sstevel@tonic-gate { 1071ae08745Sheppo struct cpu_node *cpunode; 1081ae08745Sheppo uint64_t cpuid; 1091ae08745Sheppo uint64_t clk_freq; 1101ae08745Sheppo char *namebuf; 1111ae08745Sheppo char *namebufp; 1121ae08745Sheppo int namelen; 1131ae08745Sheppo uint64_t associativity = 0, linesize = 0, size = 0; 1141ae08745Sheppo 1151ae08745Sheppo if (md_get_prop_val(mdp, cpuc, "id", &cpuid)) { 1161ae08745Sheppo return; 1171ae08745Sheppo } 1187c478bd9Sstevel@tonic-gate 1194bac2208Snarayan /* All out-of-range cpus will be stopped later. */ 1201ae08745Sheppo if (cpuid >= NCPU) { 1211ae08745Sheppo cmn_err(CE_CONT, "fill_cpu: out of range cpuid %ld - " 1224bac2208Snarayan "cpu excluded from configuration\n", cpuid); 1231ae08745Sheppo 1241ae08745Sheppo return; 1251ae08745Sheppo } 1261ae08745Sheppo 1271ae08745Sheppo cpunode = &cpunodes[cpuid]; 1281ae08745Sheppo cpunode->cpuid = (int)cpuid; 1291ae08745Sheppo cpunode->device_id = cpuid; 1301ae08745Sheppo 1311ae08745Sheppo if (sizeof (cpunode->fru_fmri) > strlen(CPU_FRU_FMRI)) 1321ae08745Sheppo (void) strcpy(cpunode->fru_fmri, CPU_FRU_FMRI); 1331ae08745Sheppo 1341ae08745Sheppo if (md_get_prop_data(mdp, cpuc, 1351ae08745Sheppo "compatible", (uint8_t **)&namebuf, &namelen)) { 1361ae08745Sheppo cmn_err(CE_PANIC, "fill_cpu: Cannot read compatible " 1371ae08745Sheppo "property"); 1381ae08745Sheppo } 1391ae08745Sheppo namebufp = namebuf; 1401ae08745Sheppo if (strncmp(namebufp, "SUNW,", 5) == 0) 1411ae08745Sheppo namebufp += 5; 1421ae08745Sheppo if (strlen(namebufp) > sizeof (cpunode->name)) 1431ae08745Sheppo cmn_err(CE_PANIC, "Compatible property too big to " 1441ae08745Sheppo "fit into the cpunode name buffer"); 1451ae08745Sheppo (void) strcpy(cpunode->name, namebufp); 1461ae08745Sheppo 1471ae08745Sheppo if (md_get_prop_val(mdp, cpuc, 1481ae08745Sheppo "clock-frequency", &clk_freq)) { 1491ae08745Sheppo clk_freq = 0; 1501ae08745Sheppo } 1511ae08745Sheppo cpunode->clock_freq = clk_freq; 1521ae08745Sheppo 1531ae08745Sheppo ASSERT(cpunode->clock_freq != 0); 1547c478bd9Sstevel@tonic-gate /* 1551ae08745Sheppo * Compute scaling factor based on rate of %tick. This is used 1561ae08745Sheppo * to convert from ticks derived from %tick to nanoseconds. See 1571ae08745Sheppo * comment in sun4u/sys/clock.h for details. 1587c478bd9Sstevel@tonic-gate */ 1591ae08745Sheppo cpunode->tick_nsec_scale = (uint_t)(((uint64_t)NANOSEC << 1601ae08745Sheppo (32 - TICK_NSEC_SHIFT)) / cpunode->clock_freq); 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate /* 1631ae08745Sheppo * The nodeid is not used in sun4v at all. Setting it 1641ae08745Sheppo * to positive value to make starting of slave CPUs 1651ae08745Sheppo * code happy. 1667c478bd9Sstevel@tonic-gate */ 1671ae08745Sheppo cpunode->nodeid = cpuid + 1; 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate /* 1701ae08745Sheppo * Obtain the L2 cache information from MD. 1711ae08745Sheppo * If "Cache" node exists, then set L2 cache properties 1721ae08745Sheppo * as read from MD. 1731ae08745Sheppo * If node does not exists, then set the L2 cache properties 1741ae08745Sheppo * in individual CPU module. 1757c478bd9Sstevel@tonic-gate */ 1761ae08745Sheppo if ((!get_l2_cache_info(mdp, cpuc, 1771ae08745Sheppo &associativity, &size, &linesize)) || 1781ae08745Sheppo associativity == 0 || size == 0 || linesize == 0) { 1791ae08745Sheppo cpu_fiximp(cpunode); 1801ae08745Sheppo } else { 1811ae08745Sheppo /* 1821ae08745Sheppo * Do not expect L2 cache properties to be bigger 1831ae08745Sheppo * than 32-bit quantity. 1841ae08745Sheppo */ 1851ae08745Sheppo cpunode->ecache_associativity = (int)associativity; 1861ae08745Sheppo cpunode->ecache_size = (int)size; 1871ae08745Sheppo cpunode->ecache_linesize = (int)linesize; 1887c478bd9Sstevel@tonic-gate } 1891ae08745Sheppo 1901ae08745Sheppo cpunode->ecache_setsize = 1911ae08745Sheppo cpunode->ecache_size / cpunode->ecache_associativity; 1921ae08745Sheppo 1931ae08745Sheppo /* 1941ae08745Sheppo * Start off by assigning the cpu id as the default 1951ae08745Sheppo * mapping index. 1961ae08745Sheppo */ 1971ae08745Sheppo 1981ae08745Sheppo cpunode->exec_unit_mapping = NO_EU_MAPPING_FOUND; 1991ae08745Sheppo 2001ae08745Sheppo if (ecache_setsize == 0) 2011ae08745Sheppo ecache_setsize = cpunode->ecache_setsize; 2021ae08745Sheppo if (ecache_alignsize == 0) 2031ae08745Sheppo ecache_alignsize = cpunode->ecache_linesize; 2041ae08745Sheppo 2051ae08745Sheppo ncpunode++; 2067c478bd9Sstevel@tonic-gate } 2077c478bd9Sstevel@tonic-gate 2081ae08745Sheppo void 2091ae08745Sheppo empty_cpu(int cpuid) 2107c478bd9Sstevel@tonic-gate { 2111ae08745Sheppo bzero(&cpunodes[cpuid], sizeof (struct cpu_node)); 2121ae08745Sheppo ncpunode--; 2131ae08745Sheppo } 2147c478bd9Sstevel@tonic-gate 2151ae08745Sheppo void 2161ae08745Sheppo setup_exec_unit_mappings(md_t *mdp) 2171ae08745Sheppo { 2181ae08745Sheppo uint64_t num, num_eunits; 2191ae08745Sheppo mde_cookie_t cpus_node; 2201ae08745Sheppo mde_cookie_t *node, *eunit; 2211ae08745Sheppo int idx, i, j; 2221ae08745Sheppo processorid_t cpuid; 2231ae08745Sheppo char *eunit_name = broken_md_flag ? "exec_unit" : "exec-unit"; 224fb2f18f8Sesaxe enum eu_type { INTEGER, FPU } etype; 2257c478bd9Sstevel@tonic-gate 2261ae08745Sheppo /* 2271ae08745Sheppo * Find the cpu integer exec units - and 2281ae08745Sheppo * setup the mappings appropriately. 2291ae08745Sheppo */ 2301ae08745Sheppo num = md_alloc_scan_dag(mdp, md_root_node(mdp), "cpus", "fwd", &node); 2311ae08745Sheppo if (num < 1) 2324bac2208Snarayan cmn_err(CE_PANIC, "No cpus node in machine description"); 2331ae08745Sheppo if (num > 1) 2341ae08745Sheppo cmn_err(CE_PANIC, "More than 1 cpus node in machine" 2351ae08745Sheppo " description"); 2361ae08745Sheppo 2371ae08745Sheppo cpus_node = node[0]; 2381ae08745Sheppo md_free_scan_dag(mdp, &node); 2391ae08745Sheppo 2401ae08745Sheppo num_eunits = md_alloc_scan_dag(mdp, cpus_node, eunit_name, 2411ae08745Sheppo "fwd", &eunit); 2421ae08745Sheppo if (num_eunits > 0) { 243fb2f18f8Sesaxe char *int_str = broken_md_flag ? "int" : "integer"; 244fb2f18f8Sesaxe char *fpu_str = "fp"; 2451ae08745Sheppo 2461ae08745Sheppo /* Spin through and find all the integer exec units */ 2471ae08745Sheppo for (i = 0; i < num_eunits; i++) { 2481ae08745Sheppo char *p; 2491ae08745Sheppo char *val; 2501ae08745Sheppo int vallen; 2511ae08745Sheppo uint64_t lcpuid; 2521ae08745Sheppo 253fb2f18f8Sesaxe /* ignore nodes with no type */ 2541ae08745Sheppo if (md_get_prop_data(mdp, eunit[i], "type", 2551ae08745Sheppo (uint8_t **)&val, &vallen)) continue; 2561ae08745Sheppo 2571ae08745Sheppo for (p = val; *p != '\0'; p += strlen(p) + 1) { 258fb2f18f8Sesaxe if (strcmp(p, int_str) == 0) { 259fb2f18f8Sesaxe etype = INTEGER; 2601ae08745Sheppo goto found; 261fb2f18f8Sesaxe } 262fb2f18f8Sesaxe if (strcmp(p, fpu_str) == 0) { 263fb2f18f8Sesaxe etype = FPU; 264fb2f18f8Sesaxe goto found; 265fb2f18f8Sesaxe } 2667c478bd9Sstevel@tonic-gate } 2671ae08745Sheppo 2681ae08745Sheppo continue; 2691ae08745Sheppo found: 2701ae08745Sheppo idx = NCPU + i; 2717c478bd9Sstevel@tonic-gate /* 2721ae08745Sheppo * find the cpus attached to this EU and 2731ae08745Sheppo * update their mapping indices 2747c478bd9Sstevel@tonic-gate */ 2751ae08745Sheppo num = md_alloc_scan_dag(mdp, eunit[i], "cpu", 2761ae08745Sheppo "back", &node); 2771ae08745Sheppo 2781ae08745Sheppo if (num < 1) 2791ae08745Sheppo cmn_err(CE_PANIC, "exec-unit node in MD" 2801ae08745Sheppo " not attached to a cpu node"); 2811ae08745Sheppo 2821ae08745Sheppo for (j = 0; j < num; j++) { 2831ae08745Sheppo if (md_get_prop_val(mdp, node[j], "id", 2841ae08745Sheppo &lcpuid)) 2851ae08745Sheppo continue; 2861ae08745Sheppo if (lcpuid >= NCPU) 2871ae08745Sheppo continue; 2881ae08745Sheppo cpuid = (processorid_t)lcpuid; 289fb2f18f8Sesaxe switch (etype) { 290fb2f18f8Sesaxe case INTEGER: 291fb2f18f8Sesaxe cpunodes[cpuid].exec_unit_mapping = idx; 292fb2f18f8Sesaxe break; 293fb2f18f8Sesaxe case FPU: 294fb2f18f8Sesaxe cpunodes[cpuid].fpu_mapping = idx; 295fb2f18f8Sesaxe break; 296fb2f18f8Sesaxe } 2971ae08745Sheppo } 2981ae08745Sheppo md_free_scan_dag(mdp, &node); 2997c478bd9Sstevel@tonic-gate } 3007c478bd9Sstevel@tonic-gate 3011ae08745Sheppo 3021ae08745Sheppo md_free_scan_dag(mdp, &eunit); 3037c478bd9Sstevel@tonic-gate } 3047c478bd9Sstevel@tonic-gate } 3057c478bd9Sstevel@tonic-gate 3061ae08745Sheppo /* 3071ae08745Sheppo * All the common setup of sun4v CPU modules is done by this routine. 3081ae08745Sheppo */ 3091ae08745Sheppo void 3101ae08745Sheppo cpu_setup_common(char **cpu_module_isa_set) 3117c478bd9Sstevel@tonic-gate { 3121ae08745Sheppo extern int mmu_exported_pagesize_mask; 3131ae08745Sheppo int nocpus, i; 3141ae08745Sheppo size_t ra_limit; 3151ae08745Sheppo mde_cookie_t *cpulist; 3161ae08745Sheppo md_t *mdp; 3171ae08745Sheppo 3181ae08745Sheppo if ((mdp = md_get_handle()) == NULL) 3191ae08745Sheppo cmn_err(CE_PANIC, "Unable to initialize machine description"); 3201ae08745Sheppo 3211ae08745Sheppo nocpus = md_alloc_scan_dag(mdp, 3221ae08745Sheppo md_root_node(mdp), "cpu", "fwd", &cpulist); 3231ae08745Sheppo if (nocpus < 1) { 3241ae08745Sheppo cmn_err(CE_PANIC, "cpu_common_setup: cpulist allocation " 3251ae08745Sheppo "failed or incorrect number of CPUs in MD"); 3261ae08745Sheppo } 3277c478bd9Sstevel@tonic-gate 3284bac2208Snarayan init_md_broken(mdp, cpulist); 3294bac2208Snarayan 3301ae08745Sheppo if (use_page_coloring) { 3311ae08745Sheppo do_pg_coloring = 1; 3321ae08745Sheppo } 3331ae08745Sheppo 3341ae08745Sheppo /* 3351e2e7a75Shuah * Get the valid mmu page sizes mask, Q sizes and isalist/r 3361ae08745Sheppo * from the MD for the first available CPU in cpulist. 3371e2e7a75Shuah * 3381e2e7a75Shuah * Do not expect the MMU page sizes mask to be more than 32-bit. 3391ae08745Sheppo */ 3401ae08745Sheppo mmu_exported_pagesize_mask = (int)get_cpu_pagesizes(mdp, cpulist[0]); 3411ae08745Sheppo 342*05d3dc4bSpaulsan /* 343*05d3dc4bSpaulsan * Get the number of contexts and tsbs supported. 344*05d3dc4bSpaulsan */ 345*05d3dc4bSpaulsan if (get_mmu_shcontexts(mdp, cpulist[0]) >= MIN_NSHCONTEXTS && 346*05d3dc4bSpaulsan get_mmu_tsbs(mdp, cpulist[0]) >= MIN_NTSBS) { 347*05d3dc4bSpaulsan shctx_on = 1; 348*05d3dc4bSpaulsan } 349*05d3dc4bSpaulsan 3501ae08745Sheppo for (i = 0; i < nocpus; i++) 3511ae08745Sheppo fill_cpu(mdp, cpulist[i]); 3521ae08745Sheppo 3531ae08745Sheppo setup_exec_unit_mappings(mdp); 3541ae08745Sheppo 3551ae08745Sheppo /* 3561ae08745Sheppo * If MD is broken then append the passed ISA set, 3571ae08745Sheppo * otherwise trust the MD. 3581ae08745Sheppo */ 3591ae08745Sheppo 3601ae08745Sheppo if (broken_md_flag) 3611ae08745Sheppo isa_list = construct_isalist(mdp, cpulist[0], 3621ae08745Sheppo cpu_module_isa_set); 3631ae08745Sheppo else 3641ae08745Sheppo isa_list = construct_isalist(mdp, cpulist[0], NULL); 3651ae08745Sheppo 3661ae08745Sheppo get_q_sizes(mdp, cpulist[0]); 3671ae08745Sheppo 3681ae08745Sheppo get_va_bits(mdp, cpulist[0]); 3691ae08745Sheppo 3701ae08745Sheppo /* 3711ae08745Sheppo * ra_limit is the highest real address in the machine. 3721ae08745Sheppo */ 3731ae08745Sheppo ra_limit = get_ra_limit(mdp); 3741ae08745Sheppo 3751ae08745Sheppo md_free_scan_dag(mdp, &cpulist); 3761ae08745Sheppo 3771ae08745Sheppo (void) md_fini_handle(mdp); 3781ae08745Sheppo 3791ae08745Sheppo /* 3801ae08745Sheppo * Block stores invalidate all pages of the d$ so pagecopy 3811ae08745Sheppo * et. al. do not need virtual translations with virtual 3821ae08745Sheppo * coloring taken into consideration. 3831ae08745Sheppo */ 3841ae08745Sheppo pp_consistent_coloring = 0; 3851ae08745Sheppo 3861ae08745Sheppo /* 3871ae08745Sheppo * The kpm mapping window. 3881ae08745Sheppo * kpm_size: 3891ae08745Sheppo * The size of a single kpm range. 3901ae08745Sheppo * The overall size will be: kpm_size * vac_colors. 3911ae08745Sheppo * kpm_vbase: 3921ae08745Sheppo * The virtual start address of the kpm range within the kernel 3931ae08745Sheppo * virtual address space. kpm_vbase has to be kpm_size aligned. 3941ae08745Sheppo */ 3951ae08745Sheppo 3961ae08745Sheppo /* 3971ae08745Sheppo * Make kpm_vbase, kpm_size aligned to kpm_size_shift. 3981ae08745Sheppo * To do this find the nearest power of 2 size that the 3991ae08745Sheppo * actual ra_limit fits within. 4001ae08745Sheppo * If it is an even power of two use that, otherwise use the 4011ae08745Sheppo * next power of two larger than ra_limit. 4021ae08745Sheppo */ 4031ae08745Sheppo 4041ae08745Sheppo ASSERT(ra_limit != 0); 4051ae08745Sheppo 4061ae08745Sheppo kpm_size_shift = (ra_limit & (ra_limit - 1)) != 0 ? 4071ae08745Sheppo highbit(ra_limit) : highbit(ra_limit) - 1; 4081ae08745Sheppo 4091ae08745Sheppo /* 4101ae08745Sheppo * No virtual caches on sun4v so size matches size shift 4111ae08745Sheppo */ 4121ae08745Sheppo kpm_size = 1ul << kpm_size_shift; 4131ae08745Sheppo 4141ae08745Sheppo if (va_bits < VA_ADDRESS_SPACE_BITS) { 4157c478bd9Sstevel@tonic-gate /* 4161ae08745Sheppo * In case of VA hole 4171ae08745Sheppo * kpm_base = hole_end + 1TB 4181ae08745Sheppo * Starting 1TB beyond where VA hole ends because on Niagara 4191ae08745Sheppo * processor software must not use pages within 4GB of the 4201ae08745Sheppo * VA hole as instruction pages to avoid problems with 4211ae08745Sheppo * prefetching into the VA hole. 4227c478bd9Sstevel@tonic-gate */ 4231ae08745Sheppo kpm_vbase = (caddr_t)((0ull - (1ull << (va_bits - 1))) + 4241ae08745Sheppo (1ull << 40)); 4251ae08745Sheppo } else { /* Number of VA bits 64 ... no VA hole */ 4261ae08745Sheppo kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8 EB */ 4277c478bd9Sstevel@tonic-gate } 4281ae08745Sheppo 4291ae08745Sheppo /* 4301ae08745Sheppo * The traptrace code uses either %tick or %stick for 4311ae08745Sheppo * timestamping. The sun4v require use of %stick. 4321ae08745Sheppo */ 4331ae08745Sheppo traptrace_use_stick = 1; 4347c478bd9Sstevel@tonic-gate } 4357c478bd9Sstevel@tonic-gate 4361ae08745Sheppo /* 4371ae08745Sheppo * Get the nctxs from MD. If absent panic. 4381ae08745Sheppo */ 4391ae08745Sheppo static uint64_t 4401ae08745Sheppo get_mmu_ctx_bits(md_t *mdp, mde_cookie_t cpu_node_cookie) 4417c478bd9Sstevel@tonic-gate { 4421ae08745Sheppo uint64_t ctx_bits; 4437c478bd9Sstevel@tonic-gate 4441ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#context-bits", 4451ae08745Sheppo &ctx_bits)) 4461ae08745Sheppo ctx_bits = 0; 4477c478bd9Sstevel@tonic-gate 4481ae08745Sheppo if (ctx_bits < MIN_NCTXS_BITS || ctx_bits > MAX_NCTXS_BITS) 4491ae08745Sheppo cmn_err(CE_PANIC, "Incorrect %ld number of contexts bits " 4501ae08745Sheppo "returned by MD", ctx_bits); 4517c478bd9Sstevel@tonic-gate 4521ae08745Sheppo return (ctx_bits); 4531ae08745Sheppo } 4547c478bd9Sstevel@tonic-gate 455*05d3dc4bSpaulsan /* 456*05d3dc4bSpaulsan * Get the number of tsbs from MD. If absent the default value is 0. 457*05d3dc4bSpaulsan */ 458*05d3dc4bSpaulsan static uint64_t 459*05d3dc4bSpaulsan get_mmu_tsbs(md_t *mdp, mde_cookie_t cpu_node_cookie) 460*05d3dc4bSpaulsan { 461*05d3dc4bSpaulsan uint64_t number_tsbs; 462*05d3dc4bSpaulsan 463*05d3dc4bSpaulsan if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-max-#tsbs", 464*05d3dc4bSpaulsan &number_tsbs)) 465*05d3dc4bSpaulsan number_tsbs = 0; 466*05d3dc4bSpaulsan 467*05d3dc4bSpaulsan return (number_tsbs); 468*05d3dc4bSpaulsan } 469*05d3dc4bSpaulsan 470*05d3dc4bSpaulsan /* 471*05d3dc4bSpaulsan * Get the number of shared contexts from MD. This property more accurately 472*05d3dc4bSpaulsan * describes the total number of contexts available, not just "shared contexts". 473*05d3dc4bSpaulsan * If absent the default value is 1, 474*05d3dc4bSpaulsan * 475*05d3dc4bSpaulsan */ 476*05d3dc4bSpaulsan static uint64_t 477*05d3dc4bSpaulsan get_mmu_shcontexts(md_t *mdp, mde_cookie_t cpu_node_cookie) 478*05d3dc4bSpaulsan { 479*05d3dc4bSpaulsan uint64_t number_contexts; 480*05d3dc4bSpaulsan 481*05d3dc4bSpaulsan if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#shared-contexts", 482*05d3dc4bSpaulsan &number_contexts)) 483*05d3dc4bSpaulsan number_contexts = 0; 484*05d3dc4bSpaulsan 485*05d3dc4bSpaulsan return (number_contexts); 486*05d3dc4bSpaulsan } 487*05d3dc4bSpaulsan 4881ae08745Sheppo /* 4891ae08745Sheppo * Initalize supported page sizes information. 4901ae08745Sheppo * Set to 0, if the page sizes mask information is absent in MD. 4911ae08745Sheppo */ 4921ae08745Sheppo static uint64_t 4931ae08745Sheppo get_cpu_pagesizes(md_t *mdp, mde_cookie_t cpu_node_cookie) 4941ae08745Sheppo { 4951ae08745Sheppo uint64_t mmu_page_size_list; 4967c478bd9Sstevel@tonic-gate 4971ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-page-size-list", 4981ae08745Sheppo &mmu_page_size_list)) 4991ae08745Sheppo mmu_page_size_list = 0; 5001ae08745Sheppo 5011ae08745Sheppo if (mmu_page_size_list == 0 || mmu_page_size_list > MAX_PAGESIZE_MASK) 5021ae08745Sheppo cmn_err(CE_PANIC, "Incorrect 0x%lx pagesize mask returned" 5031ae08745Sheppo "by MD", mmu_page_size_list); 5041ae08745Sheppo 5051ae08745Sheppo return (mmu_page_size_list); 5061ae08745Sheppo } 5071ae08745Sheppo 5081ae08745Sheppo /* 5091ae08745Sheppo * This routine gets the isalist information from MD and appends 5101ae08745Sheppo * the CPU module ISA set if required. 5111ae08745Sheppo */ 5121ae08745Sheppo static char * 5131ae08745Sheppo construct_isalist(md_t *mdp, mde_cookie_t cpu_node_cookie, 5141ae08745Sheppo char **cpu_module_isa_set) 5151ae08745Sheppo { 5161ae08745Sheppo extern int at_flags; 5171ae08745Sheppo char *md_isalist; 5181ae08745Sheppo int md_isalen; 5191ae08745Sheppo char *isabuf; 5201ae08745Sheppo int isalen; 5211ae08745Sheppo char **isa_set; 5221ae08745Sheppo char *p, *q; 5231ae08745Sheppo int cpu_module_isalen = 0, found = 0; 5241ae08745Sheppo 5251ae08745Sheppo (void) md_get_prop_data(mdp, cpu_node_cookie, 5261ae08745Sheppo "isalist", (uint8_t **)&isabuf, &isalen); 5277c478bd9Sstevel@tonic-gate 5287c478bd9Sstevel@tonic-gate /* 5291ae08745Sheppo * We support binaries for all the cpus that have shipped so far. 5301ae08745Sheppo * The kernel emulates instructions that are not supported by hardware. 5317c478bd9Sstevel@tonic-gate */ 5321ae08745Sheppo at_flags = EF_SPARC_SUN_US3 | EF_SPARC_32PLUS | EF_SPARC_SUN_US1; 5337c478bd9Sstevel@tonic-gate 5341ae08745Sheppo /* 5351ae08745Sheppo * Construct the space separated isa_list. 5361ae08745Sheppo */ 5371ae08745Sheppo if (cpu_module_isa_set != NULL) { 5381ae08745Sheppo for (isa_set = cpu_module_isa_set; *isa_set != NULL; 5391ae08745Sheppo isa_set++) { 5401ae08745Sheppo cpu_module_isalen += strlen(*isa_set); 5411ae08745Sheppo cpu_module_isalen++; /* for space character */ 5421ae08745Sheppo } 5431ae08745Sheppo } 5447c478bd9Sstevel@tonic-gate 5451ae08745Sheppo /* 5461ae08745Sheppo * Allocate the buffer of MD isa buffer length + CPU module 5471ae08745Sheppo * isa buffer length. 5481ae08745Sheppo */ 5491ae08745Sheppo md_isalen = isalen + cpu_module_isalen + 2; 5501ae08745Sheppo md_isalist = (char *)prom_alloc((caddr_t)0, md_isalen, 0); 5511ae08745Sheppo if (md_isalist == NULL) 5521ae08745Sheppo cmn_err(CE_PANIC, "construct_isalist: Allocation failed for " 5531ae08745Sheppo "md_isalist"); 5541ae08745Sheppo 5551ae08745Sheppo md_isalist[0] = '\0'; /* create an empty string to start */ 5561ae08745Sheppo for (p = isabuf, q = p + isalen; p < q; p += strlen(p) + 1) { 5571ae08745Sheppo (void) strlcat(md_isalist, p, md_isalen); 5581ae08745Sheppo (void) strcat(md_isalist, " "); 5591ae08745Sheppo } 5607c478bd9Sstevel@tonic-gate 5617c478bd9Sstevel@tonic-gate /* 5621ae08745Sheppo * Check if the isa_set is present in isalist returned by MD. 5631ae08745Sheppo * If yes, then no need to append it, if no then append it to 5641ae08745Sheppo * isalist returned by MD. 5657c478bd9Sstevel@tonic-gate */ 5661ae08745Sheppo if (cpu_module_isa_set != NULL) { 5671ae08745Sheppo for (isa_set = cpu_module_isa_set; *isa_set != NULL; 5681ae08745Sheppo isa_set++) { 5691ae08745Sheppo found = 0; 5701ae08745Sheppo for (p = isabuf, q = p + isalen; p < q; 5711ae08745Sheppo p += strlen(p) + 1) { 5721ae08745Sheppo if (strcmp(p, *isa_set) == 0) { 5731ae08745Sheppo found = 1; 5741ae08745Sheppo break; 5751ae08745Sheppo } 5761ae08745Sheppo } 5771ae08745Sheppo if (!found) { 5781ae08745Sheppo (void) strlcat(md_isalist, *isa_set, md_isalen); 5791ae08745Sheppo (void) strcat(md_isalist, " "); 5801ae08745Sheppo } 5811ae08745Sheppo } 5821ae08745Sheppo } 5831ae08745Sheppo 5841ae08745Sheppo /* Get rid of any trailing white spaces */ 5851ae08745Sheppo md_isalist[strlen(md_isalist) - 1] = '\0'; 5861ae08745Sheppo 5871ae08745Sheppo return (md_isalist); 5887c478bd9Sstevel@tonic-gate } 5897c478bd9Sstevel@tonic-gate 5901ae08745Sheppo uint64_t 5911ae08745Sheppo get_ra_limit(md_t *mdp) 5921ae08745Sheppo { 5931ae08745Sheppo mde_cookie_t *mem_list; 5941ae08745Sheppo mde_cookie_t *mblock_list; 5951ae08745Sheppo int i; 5961ae08745Sheppo int memnodes; 5971ae08745Sheppo int nmblock; 5981ae08745Sheppo uint64_t base; 5991ae08745Sheppo uint64_t size; 6001ae08745Sheppo uint64_t ra_limit = 0, new_limit = 0; 6011ae08745Sheppo 6021ae08745Sheppo memnodes = md_alloc_scan_dag(mdp, 6031ae08745Sheppo md_root_node(mdp), "memory", "fwd", &mem_list); 6041ae08745Sheppo 6051ae08745Sheppo ASSERT(memnodes == 1); 6061ae08745Sheppo 6071ae08745Sheppo nmblock = md_alloc_scan_dag(mdp, 6081ae08745Sheppo mem_list[0], "mblock", "fwd", &mblock_list); 6091ae08745Sheppo if (nmblock < 1) 6101ae08745Sheppo cmn_err(CE_PANIC, "cannot find mblock nodes in MD"); 6111ae08745Sheppo 6121ae08745Sheppo for (i = 0; i < nmblock; i++) { 6131ae08745Sheppo if (md_get_prop_val(mdp, mblock_list[i], "base", &base)) 6141ae08745Sheppo cmn_err(CE_PANIC, "base property missing from MD" 6151ae08745Sheppo " mblock node"); 6161ae08745Sheppo if (md_get_prop_val(mdp, mblock_list[i], "size", &size)) 6171ae08745Sheppo cmn_err(CE_PANIC, "size property missing from MD" 6181ae08745Sheppo " mblock node"); 6191ae08745Sheppo 6201ae08745Sheppo ASSERT(size != 0); 6211ae08745Sheppo 6221ae08745Sheppo new_limit = base + size; 6231ae08745Sheppo 6241ae08745Sheppo if (base > new_limit) 6251ae08745Sheppo cmn_err(CE_PANIC, "mblock in MD wrapped around"); 6261ae08745Sheppo 6271ae08745Sheppo if (new_limit > ra_limit) 6281ae08745Sheppo ra_limit = new_limit; 6291ae08745Sheppo } 6301ae08745Sheppo 6311ae08745Sheppo ASSERT(ra_limit != 0); 6321ae08745Sheppo 6331ae08745Sheppo if (ra_limit > MAX_REAL_ADDRESS) { 6341ae08745Sheppo cmn_err(CE_WARN, "Highest real address in MD too large" 6351ae08745Sheppo " clipping to %llx\n", MAX_REAL_ADDRESS); 6361ae08745Sheppo ra_limit = MAX_REAL_ADDRESS; 6371ae08745Sheppo } 6381ae08745Sheppo 6391ae08745Sheppo md_free_scan_dag(mdp, &mblock_list); 6401ae08745Sheppo 6411ae08745Sheppo md_free_scan_dag(mdp, &mem_list); 6421ae08745Sheppo 6431ae08745Sheppo return (ra_limit); 6441ae08745Sheppo } 6457c478bd9Sstevel@tonic-gate 6467c478bd9Sstevel@tonic-gate /* 6471ae08745Sheppo * This routine sets the globals for CPU and DEV mondo queue entries and 6481ae08745Sheppo * resumable and non-resumable error queue entries. 6494bac2208Snarayan * 6504bac2208Snarayan * First, look up the number of bits available to pass an entry number. 6514bac2208Snarayan * This can vary by platform and may result in allocating an unreasonably 6524bac2208Snarayan * (or impossibly) large amount of memory for the corresponding table, 6534bac2208Snarayan * so we clamp it by 'max_entries'. If the prop is missing, use 6544bac2208Snarayan * 'default_entries'. 6557c478bd9Sstevel@tonic-gate */ 6561ae08745Sheppo static uint64_t 6571ae08745Sheppo get_single_q_size(md_t *mdp, mde_cookie_t cpu_node_cookie, 6584bac2208Snarayan char *qnamep, uint64_t default_entries, uint64_t max_entries) 6591ae08745Sheppo { 6601ae08745Sheppo uint64_t entries; 6611ae08745Sheppo 6624bac2208Snarayan if (default_entries > max_entries) 6634bac2208Snarayan cmn_err(CE_CONT, "!get_single_q_size: dflt %ld > " 6644bac2208Snarayan "max %ld for %s\n", default_entries, max_entries, qnamep); 6654bac2208Snarayan 6661ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, qnamep, &entries)) { 6671ae08745Sheppo if (!broken_md_flag) 6681ae08745Sheppo cmn_err(CE_PANIC, "Missing %s property in MD cpu node", 6691ae08745Sheppo qnamep); 6701ae08745Sheppo entries = default_entries; 6711ae08745Sheppo } else { 6721ae08745Sheppo entries = 1 << entries; 6731ae08745Sheppo } 6744bac2208Snarayan 6754bac2208Snarayan entries = MIN(entries, max_entries); 6764bac2208Snarayan 6771ae08745Sheppo return (entries); 6781ae08745Sheppo } 6791ae08745Sheppo 6804bac2208Snarayan /* Scaling constant used to compute size of cpu mondo queue */ 6814bac2208Snarayan #define CPU_MONDO_Q_MULTIPLIER 8 6821ae08745Sheppo 6837c478bd9Sstevel@tonic-gate static void 6841ae08745Sheppo get_q_sizes(md_t *mdp, mde_cookie_t cpu_node_cookie) 6857c478bd9Sstevel@tonic-gate { 6864bac2208Snarayan uint64_t max_qsize; 6874bac2208Snarayan mde_cookie_t *platlist; 6884bac2208Snarayan int nrnode; 6894bac2208Snarayan 6904bac2208Snarayan /* 6914bac2208Snarayan * Compute the maximum number of entries for the cpu mondo queue. 6924bac2208Snarayan * Use the appropriate property in the platform node, if it is 6934bac2208Snarayan * available. Else, base it on NCPU. 6944bac2208Snarayan */ 6954bac2208Snarayan nrnode = md_alloc_scan_dag(mdp, 6964bac2208Snarayan md_root_node(mdp), "platform", "fwd", &platlist); 6974bac2208Snarayan 6984bac2208Snarayan ASSERT(nrnode == 1); 6994bac2208Snarayan 700aaa10e67Sha ncpu_guest_max = NCPU; 701aaa10e67Sha (void) md_get_prop_val(mdp, platlist[0], "max-cpus", &ncpu_guest_max); 702aaa10e67Sha max_qsize = ncpu_guest_max * CPU_MONDO_Q_MULTIPLIER; 7034bac2208Snarayan 7044bac2208Snarayan md_free_scan_dag(mdp, &platlist); 7054bac2208Snarayan 7061ae08745Sheppo cpu_q_entries = get_single_q_size(mdp, cpu_node_cookie, 7074bac2208Snarayan "q-cpu-mondo-#bits", DEFAULT_CPU_Q_ENTRIES, max_qsize); 7081ae08745Sheppo 7091ae08745Sheppo dev_q_entries = get_single_q_size(mdp, cpu_node_cookie, 710b0fc0e77Sgovinda "q-dev-mondo-#bits", DEFAULT_DEV_Q_ENTRIES, MAXIVNUM); 7111ae08745Sheppo 7121ae08745Sheppo cpu_rq_entries = get_single_q_size(mdp, cpu_node_cookie, 7134bac2208Snarayan "q-resumable-#bits", CPU_RQ_ENTRIES, MAX_CPU_RQ_ENTRIES); 7141ae08745Sheppo 7151ae08745Sheppo cpu_nrq_entries = get_single_q_size(mdp, cpu_node_cookie, 7164bac2208Snarayan "q-nonresumable-#bits", CPU_NRQ_ENTRIES, MAX_CPU_NRQ_ENTRIES); 7171ae08745Sheppo } 7181ae08745Sheppo 7191ae08745Sheppo 7201ae08745Sheppo static void 7211ae08745Sheppo get_va_bits(md_t *mdp, mde_cookie_t cpu_node_cookie) 7221ae08745Sheppo { 7231ae08745Sheppo uint64_t value = VA_ADDRESS_SPACE_BITS; 7241ae08745Sheppo 7251ae08745Sheppo if (md_get_prop_val(mdp, cpu_node_cookie, "mmu-#va-bits", &value)) 7261ae08745Sheppo cmn_err(CE_PANIC, "mmu-#va-bits property not found in MD"); 7277c478bd9Sstevel@tonic-gate 7287c478bd9Sstevel@tonic-gate 7291ae08745Sheppo if (value == 0 || value > VA_ADDRESS_SPACE_BITS) 7301ae08745Sheppo cmn_err(CE_PANIC, "Incorrect number of va bits in MD"); 7317c478bd9Sstevel@tonic-gate 7321ae08745Sheppo /* Do not expect number of VA bits to be more than 32-bit quantity */ 7337c478bd9Sstevel@tonic-gate 7341ae08745Sheppo va_bits = (int)value; 7357c478bd9Sstevel@tonic-gate 7367c478bd9Sstevel@tonic-gate /* 7371ae08745Sheppo * Correct the value for VA bits on UltraSPARC-T1 based systems 7381ae08745Sheppo * in case of broken MD. 7397c478bd9Sstevel@tonic-gate */ 7401ae08745Sheppo if (broken_md_flag) 7411ae08745Sheppo va_bits = DEFAULT_VA_ADDRESS_SPACE_BITS; 7427c478bd9Sstevel@tonic-gate } 7437c478bd9Sstevel@tonic-gate 7441ae08745Sheppo /* 7451ae08745Sheppo * This routine returns the L2 cache information such as -- associativity, 7461ae08745Sheppo * size and linesize. 7471ae08745Sheppo */ 7481ae08745Sheppo static int 7491ae08745Sheppo get_l2_cache_info(md_t *mdp, mde_cookie_t cpu_node_cookie, 7501ae08745Sheppo uint64_t *associativity, uint64_t *size, uint64_t *linesize) 7511ae08745Sheppo { 7521ae08745Sheppo mde_cookie_t *cachelist; 7531ae08745Sheppo int ncaches, i; 7541ae08745Sheppo uint64_t max_level; 7551ae08745Sheppo 7561ae08745Sheppo ncaches = md_alloc_scan_dag(mdp, cpu_node_cookie, "cache", 7571ae08745Sheppo "fwd", &cachelist); 7581ae08745Sheppo /* 7591ae08745Sheppo * The "cache" node is optional in MD, therefore ncaches can be 0. 7601ae08745Sheppo */ 7611ae08745Sheppo if (ncaches < 1) { 7621ae08745Sheppo return (0); 7631ae08745Sheppo } 7641ae08745Sheppo 7651ae08745Sheppo max_level = 0; 7661ae08745Sheppo for (i = 0; i < ncaches; i++) { 7671ae08745Sheppo uint64_t cache_level; 7681ae08745Sheppo uint64_t local_assoc; 7691ae08745Sheppo uint64_t local_size; 7701ae08745Sheppo uint64_t local_lsize; 7711ae08745Sheppo 7721ae08745Sheppo if (md_get_prop_val(mdp, cachelist[i], "level", &cache_level)) 7731ae08745Sheppo continue; 7741ae08745Sheppo 7751ae08745Sheppo if (cache_level <= max_level) continue; 7761ae08745Sheppo 7771ae08745Sheppo /* If properties are missing from this cache ignore it */ 7781ae08745Sheppo 7791ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 7801ae08745Sheppo "associativity", &local_assoc))) { 7811ae08745Sheppo continue; 7821ae08745Sheppo } 7831ae08745Sheppo 7841ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 7851ae08745Sheppo "size", &local_size))) { 7861ae08745Sheppo continue; 7871ae08745Sheppo } 7881ae08745Sheppo 7891ae08745Sheppo if ((md_get_prop_val(mdp, cachelist[i], 7901ae08745Sheppo "line-size", &local_lsize))) { 7911ae08745Sheppo continue; 7921ae08745Sheppo } 7931ae08745Sheppo 7941ae08745Sheppo max_level = cache_level; 7951ae08745Sheppo *associativity = local_assoc; 7961ae08745Sheppo *size = local_size; 7971ae08745Sheppo *linesize = local_lsize; 7981ae08745Sheppo } 7997c478bd9Sstevel@tonic-gate 8001ae08745Sheppo md_free_scan_dag(mdp, &cachelist); 8011ae08745Sheppo 8021ae08745Sheppo return ((max_level > 0) ? 1 : 0); 8031ae08745Sheppo } 8041ae08745Sheppo 8054bac2208Snarayan 8061ae08745Sheppo /* 8074bac2208Snarayan * Set the broken_md_flag to 1 if the MD doesn't have 8084bac2208Snarayan * the domaining-enabled property in the platform node and the 8094bac2208Snarayan * platform uses the UltraSPARC-T1 cpu. This flag is used to 8104bac2208Snarayan * workaround some of the incorrect MD properties. 8111ae08745Sheppo */ 8121ae08745Sheppo static void 8134bac2208Snarayan init_md_broken(md_t *mdp, mde_cookie_t *cpulist) 8147c478bd9Sstevel@tonic-gate { 8151ae08745Sheppo int nrnode; 8161ae08745Sheppo mde_cookie_t *platlist, rootnode; 8171ae08745Sheppo uint64_t val = 0; 8184bac2208Snarayan char *namebuf; 8194bac2208Snarayan int namelen; 8201ae08745Sheppo 8211ae08745Sheppo rootnode = md_root_node(mdp); 8221ae08745Sheppo ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE); 8234bac2208Snarayan ASSERT(cpulist); 8241ae08745Sheppo 8254bac2208Snarayan nrnode = md_alloc_scan_dag(mdp, rootnode, "platform", "fwd", 8261ae08745Sheppo &platlist); 8271ae08745Sheppo 828f273041fSjm if (nrnode < 1) 829f273041fSjm cmn_err(CE_PANIC, "init_md_broken: platform node missing"); 8301ae08745Sheppo 8314bac2208Snarayan if (md_get_prop_data(mdp, cpulist[0], 8324bac2208Snarayan "compatible", (uint8_t **)&namebuf, &namelen)) { 8334bac2208Snarayan cmn_err(CE_PANIC, "init_md_broken: " 8344bac2208Snarayan "Cannot read 'compatible' property of 'cpu' node"); 8354bac2208Snarayan } 8367c478bd9Sstevel@tonic-gate 8374bac2208Snarayan if (md_get_prop_val(mdp, platlist[0], 8384bac2208Snarayan "domaining-enabled", &val) == -1 && 8394bac2208Snarayan strcmp(namebuf, "SUNW,UltraSPARC-T1") == 0) 8401ae08745Sheppo broken_md_flag = 1; 8411ae08745Sheppo 8421ae08745Sheppo md_free_scan_dag(mdp, &platlist); 8437c478bd9Sstevel@tonic-gate } 844