xref: /illumos-gate/usr/src/uts/sun4v/io/niumx/niumx_var.h (revision 500b1e78)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
22*500b1e78SAlan Adamson, SD OSSD  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
268fca0570Sjf #ifndef	_SYS_NIUMX_VAR_H
278fca0570Sjf #define	_SYS_NIUMX_VAR_H
2944961713Sgirish #ifdef	__cplusplus
3044961713Sgirish extern "C" {
3144961713Sgirish #endif
3344961713Sgirish typedef enum {	/* same sequence as niumx_debug_sym[] */
34*500b1e78SAlan Adamson, SD OSSD 	/*  0 */ NIUMX_DBG_ATTACH,
35*500b1e78SAlan Adamson, SD OSSD 	/*  1 */ NIUMX_DBG_MAP,
36*500b1e78SAlan Adamson, SD OSSD 	/*  2 */ NIUMX_DBG_CTLOPS,
37*500b1e78SAlan Adamson, SD OSSD 	/*  3 */ NIUMX_DBG_INTROPS,
38*500b1e78SAlan Adamson, SD OSSD 	/*  4 */ NIUMX_DBG_A_INTX,
39*500b1e78SAlan Adamson, SD OSSD 	/*  5 */ NIUMX_DBG_R_INTX,
40*500b1e78SAlan Adamson, SD OSSD 	/*  6 */ NIUMX_DBG_INTR,
41*500b1e78SAlan Adamson, SD OSSD 	/*  7 */ NIUMX_DBG_DMA_ALLOCH,
42*500b1e78SAlan Adamson, SD OSSD 	/*  8 */ NIUMX_DBG_DMA_BINDH,
43*500b1e78SAlan Adamson, SD OSSD 	/*  9 */ NIUMX_DBG_DMA_UNBINDH,
44*500b1e78SAlan Adamson, SD OSSD 	/* 10 */ NIUMX_DBG_CHK_MOD
4544961713Sgirish } niumx_debug_bit_t;
4744961713Sgirish #if defined(DEBUG)
4844961713Sgirish #define	DBG niumx_dbg
4944961713Sgirish extern void niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...);
5044961713Sgirish #else
5144961713Sgirish #define	DBG 0 &&
5244961713Sgirish #endif	/* DEBUG */
54*500b1e78SAlan Adamson, SD OSSD typedef uint64_t niudevhandle_t;
5544961713Sgirish #define	NIUMX_DEVHDLE_MASK	0xFFFFFFF
56*500b1e78SAlan Adamson, SD OSSD typedef uint32_t niucpuid_t;
57*500b1e78SAlan Adamson, SD OSSD typedef uint32_t niudevino_t;
58*500b1e78SAlan Adamson, SD OSSD typedef	uint64_t niusysino_t;
6044961713Sgirish /*
6144961713Sgirish  * The following structure represents an interrupt handler control block for
6244961713Sgirish  * each interrupt added via ddi_intr_add_handler().
6344961713Sgirish  */
6444961713Sgirish typedef struct niumx_ih {
6544961713Sgirish 	dev_info_t	*ih_dip;	/* devinfo structure */
6644961713Sgirish 	uint32_t	ih_inum;	/* interrupt index, from leaf */
67*500b1e78SAlan Adamson, SD OSSD 	niusysino_t	ih_sysino;	/* System virtual inumber, from HV */
68*500b1e78SAlan Adamson, SD OSSD 	niucpuid_t	ih_cpuid;	/* cpu that ino is targeting */
69*500b1e78SAlan Adamson, SD OSSD 	int		ih_state;	/* interrupt valid state */
70*500b1e78SAlan Adamson, SD OSSD 	int		ih_pri;		/* interrupt priority */
7144961713Sgirish 	uint_t		(*ih_hdlr)();	/* interrupt handler */
7244961713Sgirish 	caddr_t		ih_arg1;	/* interrupt handler argument #1 */
7344961713Sgirish 	caddr_t		ih_arg2;	/* interrupt handler argument #2 */
7444961713Sgirish 	struct niumx_ih	*ih_next;	/* next in the chain */
7544961713Sgirish } niumx_ih_t;
77*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_MAX_INTRS			64
78*500b1e78SAlan Adamson, SD OSSD 
79*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_SOFT_STATE_OPEN		1
80*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_SOFT_STATE_OPEN_EXCL	2
81*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_SOFT_STATE_CLOSED		4
82*500b1e78SAlan Adamson, SD OSSD 
834df55fdeSJanie Lu 
8444961713Sgirish typedef struct niumx_devstate {
8544961713Sgirish 	dev_info_t *dip;
86*500b1e78SAlan Adamson, SD OSSD 	int niumx_soft_state;
87*500b1e78SAlan Adamson, SD OSSD 	int niumx_open_count;
88*500b1e78SAlan Adamson, SD OSSD 	niudevhandle_t	niumx_dev_hdl;	/* device handle */
8944961713Sgirish 	kmutex_t niumx_mutex;
9014ea4bb7Ssd 	int niumx_fm_cap;
9114ea4bb7Ssd 	ddi_iblock_cookie_t niumx_fm_ibc;
924df55fdeSJanie Lu 	niumx_ih_t niumx_ihtable[NIUMX_MAX_INTRS];
9344961713Sgirish } niumx_devstate_t;
9544961713Sgirish /*
9644961713Sgirish  * flags for overloading dmai_inuse field of the dma request structure:
9744961713Sgirish  */
9844961713Sgirish #define	dmai_pfnlst		dmai_iopte
9944961713Sgirish #define	dmai_pfn0		dmai_sbi
10044961713Sgirish #define	dmai_roffset		dmai_pool
10244961713Sgirish #define	NIUMX_PAGE_SHIFT		13
10344961713Sgirish #define	NIUMX_PAGE_SIZE		(1 << NIUMX_PAGE_SHIFT)
10444961713Sgirish #define	NIUMX_PAGE_MASK		~(NIUMX_PAGE_SIZE - 1)
10544961713Sgirish #define	NIUMX_PAGE_OFFSET		(NIUMX_PAGE_SIZE - 1)
10644961713Sgirish #define	NIUMX_PTOB(x)		(((uint64_t)(x)) << NIUMX_PAGE_SHIFT)
10844961713Sgirish /* for "ranges" property */
10944961713Sgirish typedef struct niumx_ranges {
11044961713Sgirish 	uint32_t child_hi;
11144961713Sgirish 	uint32_t child_lo;
11244961713Sgirish 	uint32_t parent_hi;
11344961713Sgirish 	uint32_t parent_lo;
11444961713Sgirish 	uint32_t size_hi;
11544961713Sgirish 	uint32_t size_lo;
11644961713Sgirish } niumx_ranges_t;
11844961713Sgirish /* IPL of 6 for networking devices */
11944961713Sgirish #define	NIUMX_DEFAULT_PIL	6
12144961713Sgirish typedef struct {
12244961713Sgirish 	uint32_t addr_high;
12344961713Sgirish 	uint32_t addr_low;
12444961713Sgirish 	uint32_t size_high;
12544961713Sgirish 	uint32_t size_low;
12644961713Sgirish } niu_regspec_t;
12844961713Sgirish /*
1293266dff7Sjf  * HV INTR  API versioning.
13044961713Sgirish  *
1313266dff7Sjf  * Currently NIU nexus driver supports version 1.0
13244961713Sgirish  */
13344961713Sgirish #define	NIUMX_INTR_MAJOR_VER_1	0x1ull
13444961713Sgirish #define	NIUMX_INTR_MAJOR_VER	NIUMX_INTR_MAJOR_VER_1
13644961713Sgirish #define	NIUMX_INTR_MINOR_VER_0	0x0ull
13744961713Sgirish #define	NIUMX_INTR_MINOR_VER	NIUMX_INTR_MINOR_VER_0
139*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_NAMEINST(dip)   ddi_driver_name(dip), ddi_get_instance(dip)
140*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_DIP_TO_HANDLE(dip) \
141*500b1e78SAlan Adamson, SD OSSD 		((niumx_devstate_t *)NIUMX_DIP_TO_STATE(dip))->niumx_dev_hdl
142*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_DIP_TO_INST(dip)	ddi_get_instance(dip)
143*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_INST_TO_STATE(inst)	ddi_get_soft_state(niumx_state, inst)
144*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_DIP_TO_STATE(dip)	NIUMX_INST_TO_STATE(NIUMX_DIP_TO_INST(dip))
145*500b1e78SAlan Adamson, SD OSSD #define	NIUMX_DEV_TO_SOFTSTATE(dev) \
146*500b1e78SAlan Adamson, SD OSSD 	((pci_t *)ddi_get_soft_state(niumx_state, \
147*500b1e78SAlan Adamson, SD OSSD 	PCI_MINOR_NUM_TO_INSTANCE(getminor(dev))))
14944961713Sgirish #ifdef	__cplusplus
15044961713Sgirish }
15144961713Sgirish #endif
1538fca0570Sjf #endif	/* _SYS_NIUMX_VAR_H */