xref: /illumos-gate/usr/src/uts/sun4v/io/niumx/niumx_var.h (revision 44961713)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NMX_H
27 #define	_SYS_NMX_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 typedef enum {	/* same sequence as niumx_debug_sym[] */
36 	/*  0 */ DBG_ATTACH,
37 	/*  1 */ DBG_MAP,
38 	/*  2 */ DBG_CTLOPS,
39 	/*  3 */ DBG_INTROPS,
40 	/*  4 */ DBG_A_INTX,
41 	/*  5 */ DBG_R_INTX,
42 	/*  6 */ DBG_INTR,
43 	/*  7 */ DBG_DMA_ALLOCH,
44 	/*  8 */ DBG_DMA_BINDH,
45 	/*  9 */ DBG_DMA_UNBINDH,
46 	/* 10 */ DBG_CHK_MOD
47 } niumx_debug_bit_t;
48 
49 #if defined(DEBUG)
50 #define	DBG niumx_dbg
51 extern void niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...);
52 #else
53 #define	DBG 0 &&
54 #endif	/* DEBUG */
55 
56 typedef uint64_t devhandle_t;
57 #define	NIUMX_DEVHDLE_MASK	0xFFFFFFF
58 typedef uint32_t cpuid_t;
59 typedef uint32_t devino_t;
60 typedef	uint64_t sysino_t;
61 
62 /*
63  * The following structure represents an interrupt handler control block for
64  * each interrupt added via ddi_intr_add_handler().
65  */
66 typedef struct niumx_ih {
67 	dev_info_t	*ih_dip;	/* devinfo structure */
68 	uint32_t	ih_inum;	/* interrupt index, from leaf */
69 	devino_t	ih_ino;		/* INO number, from "interrupts" prop */
70 	sysino_t	ih_sysino;	/* System virtual inumber, from HV */
71 	cpuid_t		ih_cpuid;	/* cpu that ino is targeting */
72 	uint_t		(*ih_hdlr)();	/* interrupt handler */
73 	caddr_t		ih_arg1;	/* interrupt handler argument #1 */
74 	caddr_t		ih_arg2;	/* interrupt handler argument #2 */
75 	struct niumx_ih	*ih_next;	/* next in the chain */
76 } niumx_ih_t;
77 
78 typedef struct niumx_devstate {
79 	dev_info_t *dip;
80 	devhandle_t	niumx_dev_hdl;	/* device handle */
81 	kmutex_t niumx_mutex;
82 } niumx_devstate_t;
83 
84 #define	NIUMX_FUNC_NUM_MASK	1
85 #define	NIUMX_MAX_INTRS	64
86 
87 /* currently Error Interrupt handler slot is hardcoded */
88 #define	NIUMX_EI_IH 52
89 
90 /*
91  * flags for overloading dmai_inuse field of the dma request structure:
92  */
93 #define	dmai_pfnlst		dmai_iopte
94 #define	dmai_pfn0		dmai_sbi
95 #define	dmai_roffset		dmai_pool
96 
97 #define	NIUMX_PAGE_SHIFT		13
98 #define	NIUMX_PAGE_SIZE		(1 << NIUMX_PAGE_SHIFT)
99 #define	NIUMX_PAGE_MASK		~(NIUMX_PAGE_SIZE - 1)
100 #define	NIUMX_PAGE_OFFSET		(NIUMX_PAGE_SIZE - 1)
101 #define	NIUMX_PTOB(x)		(((uint64_t)(x)) << NIUMX_PAGE_SHIFT)
102 
103 /* for "ranges" property */
104 typedef struct niumx_ranges {
105 	uint32_t child_hi;
106 	uint32_t child_lo;
107 	uint32_t parent_hi;
108 	uint32_t parent_lo;
109 	uint32_t size_hi;
110 	uint32_t size_lo;
111 } niumx_ranges_t;
112 
113 /* IPL of 6 for networking devices */
114 #define	NIUMX_DEFAULT_PIL	6
115 
116 typedef struct {
117 	uint32_t addr_high;
118 	uint32_t addr_low;
119 	uint32_t size_high;
120 	uint32_t size_low;
121 } niu_regspec_t;
122 
123 /*
124  * HV VPCI & INTR  API versioning.
125  *
126  * Currently NIU nexus driver supports VPCI API version 1.0
127  */
128 #define	NIUMX_VPCI_MAJOR_VER_1	0x1ull
129 #define	NIUMX_VPCI_MAJOR_VER	NIUMX_VPCI_MAJOR_VER_1
130 
131 #define	NIUMX_VPCI_MINOR_VER_0	0x0ull
132 #define	NIUMX_VPCI_MINOR_VER	NIUMX_VPCI_MINOR_VER_0
133 
134 #define	NIUMX_INTR_MAJOR_VER_1	0x1ull
135 #define	NIUMX_INTR_MAJOR_VER	NIUMX_INTR_MAJOR_VER_1
136 
137 #define	NIUMX_INTR_MINOR_VER_0	0x0ull
138 #define	NIUMX_INTR_MINOR_VER	NIUMX_INTR_MINOR_VER_0
139 
140 #define	NAMEINST(dip)   ddi_driver_name(dip), ddi_get_instance(dip)
141 #define	DIP_TO_HANDLE(dip) \
142 		((niumx_devstate_t *)DIP_TO_STATE(dip))->niumx_dev_hdl
143 #define	DIP_TO_INST(dip)	ddi_get_instance(dip)
144 #define	INST_TO_STATE(inst)	ddi_get_soft_state(niumx_state, inst)
145 #define	DIP_TO_STATE(dip)	INST_TO_STATE(DIP_TO_INST(dip))
146 
147 #ifdef	__cplusplus
148 }
149 #endif
150 
151 #endif	/* _SYS_NMX_H */
152