xref: /illumos-gate/usr/src/uts/sun4v/io/niumx/niumx_var.h (revision 14ea4bb7)
144961713Sgirish /*
244961713Sgirish  * CDDL HEADER START
344961713Sgirish  *
444961713Sgirish  * The contents of this file are subject to the terms of the
544961713Sgirish  * Common Development and Distribution License (the "License").
644961713Sgirish  * You may not use this file except in compliance with the License.
744961713Sgirish  *
844961713Sgirish  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
944961713Sgirish  * or http://www.opensolaris.org/os/licensing.
1044961713Sgirish  * See the License for the specific language governing permissions
1144961713Sgirish  * and limitations under the License.
1244961713Sgirish  *
1344961713Sgirish  * When distributing Covered Code, include this CDDL HEADER in each
1444961713Sgirish  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1544961713Sgirish  * If applicable, add the following below this CDDL HEADER, with the
1644961713Sgirish  * fields enclosed by brackets "[]" replaced with your own identifying
1744961713Sgirish  * information: Portions Copyright [yyyy] [name of copyright owner]
1844961713Sgirish  *
1944961713Sgirish  * CDDL HEADER END
2044961713Sgirish  */
2144961713Sgirish /*
2244961713Sgirish  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
2344961713Sgirish  * Use is subject to license terms.
2444961713Sgirish  */
2544961713Sgirish 
2644961713Sgirish #ifndef	_SYS_NMX_H
2744961713Sgirish #define	_SYS_NMX_H
2844961713Sgirish 
2944961713Sgirish #pragma ident	"%Z%%M%	%I%	%E% SMI"
3044961713Sgirish 
3144961713Sgirish #ifdef	__cplusplus
3244961713Sgirish extern "C" {
3344961713Sgirish #endif
3444961713Sgirish 
3544961713Sgirish typedef enum {	/* same sequence as niumx_debug_sym[] */
3644961713Sgirish 	/*  0 */ DBG_ATTACH,
3744961713Sgirish 	/*  1 */ DBG_MAP,
3844961713Sgirish 	/*  2 */ DBG_CTLOPS,
3944961713Sgirish 	/*  3 */ DBG_INTROPS,
4044961713Sgirish 	/*  4 */ DBG_A_INTX,
4144961713Sgirish 	/*  5 */ DBG_R_INTX,
4244961713Sgirish 	/*  6 */ DBG_INTR,
4344961713Sgirish 	/*  7 */ DBG_DMA_ALLOCH,
4444961713Sgirish 	/*  8 */ DBG_DMA_BINDH,
4544961713Sgirish 	/*  9 */ DBG_DMA_UNBINDH,
4644961713Sgirish 	/* 10 */ DBG_CHK_MOD
4744961713Sgirish } niumx_debug_bit_t;
4844961713Sgirish 
4944961713Sgirish #if defined(DEBUG)
5044961713Sgirish #define	DBG niumx_dbg
5144961713Sgirish extern void niumx_dbg(niumx_debug_bit_t bit, dev_info_t *dip, char *fmt, ...);
5244961713Sgirish #else
5344961713Sgirish #define	DBG 0 &&
5444961713Sgirish #endif	/* DEBUG */
5544961713Sgirish 
5644961713Sgirish typedef uint64_t devhandle_t;
5744961713Sgirish #define	NIUMX_DEVHDLE_MASK	0xFFFFFFF
5844961713Sgirish typedef uint32_t cpuid_t;
5944961713Sgirish typedef uint32_t devino_t;
6044961713Sgirish typedef	uint64_t sysino_t;
6144961713Sgirish 
6244961713Sgirish /*
6344961713Sgirish  * The following structure represents an interrupt handler control block for
6444961713Sgirish  * each interrupt added via ddi_intr_add_handler().
6544961713Sgirish  */
6644961713Sgirish typedef struct niumx_ih {
6744961713Sgirish 	dev_info_t	*ih_dip;	/* devinfo structure */
6844961713Sgirish 	uint32_t	ih_inum;	/* interrupt index, from leaf */
6944961713Sgirish 	devino_t	ih_ino;		/* INO number, from "interrupts" prop */
7044961713Sgirish 	sysino_t	ih_sysino;	/* System virtual inumber, from HV */
7144961713Sgirish 	cpuid_t		ih_cpuid;	/* cpu that ino is targeting */
7244961713Sgirish 	uint_t		(*ih_hdlr)();	/* interrupt handler */
7344961713Sgirish 	caddr_t		ih_arg1;	/* interrupt handler argument #1 */
7444961713Sgirish 	caddr_t		ih_arg2;	/* interrupt handler argument #2 */
7544961713Sgirish 	struct niumx_ih	*ih_next;	/* next in the chain */
7644961713Sgirish } niumx_ih_t;
7744961713Sgirish 
7844961713Sgirish typedef struct niumx_devstate {
7944961713Sgirish 	dev_info_t *dip;
8044961713Sgirish 	devhandle_t	niumx_dev_hdl;	/* device handle */
8144961713Sgirish 	kmutex_t niumx_mutex;
82*14ea4bb7Ssd 	int niumx_fm_cap;
83*14ea4bb7Ssd 	ddi_iblock_cookie_t niumx_fm_ibc;
8444961713Sgirish } niumx_devstate_t;
8544961713Sgirish 
8644961713Sgirish #define	NIUMX_FUNC_NUM_MASK	1
8744961713Sgirish #define	NIUMX_MAX_INTRS	64
883266dff7Sjf #define	NIUMX_RSVD_INTRS	16
8944961713Sgirish 
9044961713Sgirish /* currently Error Interrupt handler slot is hardcoded */
9144961713Sgirish #define	NIUMX_EI_IH 52
9244961713Sgirish 
9344961713Sgirish /*
9444961713Sgirish  * flags for overloading dmai_inuse field of the dma request structure:
9544961713Sgirish  */
9644961713Sgirish #define	dmai_pfnlst		dmai_iopte
9744961713Sgirish #define	dmai_pfn0		dmai_sbi
9844961713Sgirish #define	dmai_roffset		dmai_pool
9944961713Sgirish 
10044961713Sgirish #define	NIUMX_PAGE_SHIFT		13
10144961713Sgirish #define	NIUMX_PAGE_SIZE		(1 << NIUMX_PAGE_SHIFT)
10244961713Sgirish #define	NIUMX_PAGE_MASK		~(NIUMX_PAGE_SIZE - 1)
10344961713Sgirish #define	NIUMX_PAGE_OFFSET		(NIUMX_PAGE_SIZE - 1)
10444961713Sgirish #define	NIUMX_PTOB(x)		(((uint64_t)(x)) << NIUMX_PAGE_SHIFT)
10544961713Sgirish 
10644961713Sgirish /* for "ranges" property */
10744961713Sgirish typedef struct niumx_ranges {
10844961713Sgirish 	uint32_t child_hi;
10944961713Sgirish 	uint32_t child_lo;
11044961713Sgirish 	uint32_t parent_hi;
11144961713Sgirish 	uint32_t parent_lo;
11244961713Sgirish 	uint32_t size_hi;
11344961713Sgirish 	uint32_t size_lo;
11444961713Sgirish } niumx_ranges_t;
11544961713Sgirish 
11644961713Sgirish /* IPL of 6 for networking devices */
11744961713Sgirish #define	NIUMX_DEFAULT_PIL	6
11844961713Sgirish 
11944961713Sgirish typedef struct {
12044961713Sgirish 	uint32_t addr_high;
12144961713Sgirish 	uint32_t addr_low;
12244961713Sgirish 	uint32_t size_high;
12344961713Sgirish 	uint32_t size_low;
12444961713Sgirish } niu_regspec_t;
12544961713Sgirish 
12644961713Sgirish /*
1273266dff7Sjf  * HV INTR  API versioning.
12844961713Sgirish  *
1293266dff7Sjf  * Currently NIU nexus driver supports version 1.0
13044961713Sgirish  */
13144961713Sgirish #define	NIUMX_INTR_MAJOR_VER_1	0x1ull
13244961713Sgirish #define	NIUMX_INTR_MAJOR_VER	NIUMX_INTR_MAJOR_VER_1
13344961713Sgirish 
13444961713Sgirish #define	NIUMX_INTR_MINOR_VER_0	0x0ull
13544961713Sgirish #define	NIUMX_INTR_MINOR_VER	NIUMX_INTR_MINOR_VER_0
13644961713Sgirish 
13744961713Sgirish #define	NAMEINST(dip)   ddi_driver_name(dip), ddi_get_instance(dip)
13844961713Sgirish #define	DIP_TO_HANDLE(dip) \
13944961713Sgirish 		((niumx_devstate_t *)DIP_TO_STATE(dip))->niumx_dev_hdl
14044961713Sgirish #define	DIP_TO_INST(dip)	ddi_get_instance(dip)
14144961713Sgirish #define	INST_TO_STATE(inst)	ddi_get_soft_state(niumx_state, inst)
14244961713Sgirish #define	DIP_TO_STATE(dip)	INST_TO_STATE(DIP_TO_INST(dip))
14344961713Sgirish 
14444961713Sgirish #ifdef	__cplusplus
14544961713Sgirish }
14644961713Sgirish #endif
14744961713Sgirish 
14844961713Sgirish #endif	/* _SYS_NMX_H */
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