1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <vm/vm_dep.h> 39 #include <sys/cpuvar.h> 40 #include <sys/async.h> 41 #include <sys/cmn_err.h> 42 #include <sys/debug.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/cpu_module.h> 46 #include <sys/prom_debug.h> 47 #include <sys/vmsystm.h> 48 #include <sys/prom_plat.h> 49 #include <sys/sysmacros.h> 50 #include <sys/intreg.h> 51 #include <sys/machtrap.h> 52 #include <sys/ontrap.h> 53 #include <sys/ivintr.h> 54 #include <sys/atomic.h> 55 #include <sys/panic.h> 56 #include <sys/dtrace.h> 57 #include <sys/simulate.h> 58 #include <sys/fault.h> 59 #include <sys/niagara2regs.h> 60 #include <sys/hsvc.h> 61 #include <sys/trapstat.h> 62 63 uint_t root_phys_addr_lo_mask = 0xffffffffU; 64 char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 65 66 /* 67 * Hypervisor services information for the NIAGARA2 CPU module 68 */ 69 static boolean_t niagara2_hsvc_available = B_TRUE; 70 static uint64_t niagara2_sup_minor; /* Supported minor number */ 71 static hsvc_info_t niagara2_hsvc = { 72 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 73 NIAGARA2_HSVC_MINOR, cpu_module_name 74 }; 75 76 void 77 cpu_setup(void) 78 { 79 extern int mmu_exported_pagesize_mask; 80 extern int cpc_has_overflow_intr; 81 extern size_t contig_mem_prealloc_base; 82 int status; 83 84 /* 85 * Negotiate the API version for Niagara2 specific hypervisor 86 * services. 87 */ 88 status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor); 89 if (status != 0) { 90 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 91 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 92 niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group, 93 niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status); 94 niagara2_hsvc_available = B_FALSE; 95 } 96 97 /* 98 * The setup common to all CPU modules is done in cpu_setup_common 99 * routine. 100 */ 101 cpu_setup_common(NULL); 102 103 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 104 105 if ((mmu_exported_pagesize_mask & 106 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 107 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 108 cmn_err(CE_PANIC, "machine description" 109 " does not have required sun4v page sizes" 110 " 8K, 64K and 4M: MD mask is 0x%x", 111 mmu_exported_pagesize_mask); 112 113 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 114 115 /* 116 * Niagara2 supports a 48-bit subset of the full 64-bit virtual 117 * address space. Virtual addresses between 0x0000800000000000 118 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 119 * and must never be mapped. In addition, software must not use 120 * pages within 4GB of the VA hole as instruction pages to 121 * avoid problems with prefetching into the VA hole. 122 */ 123 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 124 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 125 126 /* 127 * Niagara2 has a performance counter overflow interrupt 128 */ 129 cpc_has_overflow_intr = 1; 130 131 /* 132 * Enable 4M pages for OOB. 133 */ 134 max_uheap_lpsize = MMU_PAGESIZE4M; 135 max_ustack_lpsize = MMU_PAGESIZE4M; 136 max_privmap_lpsize = MMU_PAGESIZE4M; 137 138 contig_mem_prealloc_base = NIAGARA2_PREALLOC_BASE; 139 } 140 141 /* 142 * Set the magic constants of the implementation. 143 */ 144 void 145 cpu_fiximp(struct cpu_node *cpunode) 146 { 147 /* 148 * The Cache node is optional in MD. Therefore in case "Cache" 149 * node does not exists in MD, set the default L2 cache associativity, 150 * size, linesize. 151 */ 152 if (cpunode->ecache_size == 0) 153 cpunode->ecache_size = L2CACHE_SIZE; 154 if (cpunode->ecache_linesize == 0) 155 cpunode->ecache_linesize = L2CACHE_LINESIZE; 156 if (cpunode->ecache_associativity == 0) 157 cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 158 } 159 160 void 161 cpu_map_exec_units(struct cpu *cp) 162 { 163 ASSERT(MUTEX_HELD(&cpu_lock)); 164 165 /* 166 * The cpu_ipipe and cpu_fpu fields are initialized based on 167 * the execution unit sharing information from the MD. They 168 * default to the CPU id in the absence of such information. 169 */ 170 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 171 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 172 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 173 174 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 175 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 176 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 177 178 /* 179 * Niagara 2 defines the core to be at the FPU level 180 */ 181 cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu; 182 } 183 184 static int niagara2_cpucnt; 185 186 void 187 cpu_init_private(struct cpu *cp) 188 { 189 extern void niagara_kstat_init(void); 190 191 ASSERT(MUTEX_HELD(&cpu_lock)); 192 193 cpu_map_exec_units(cp); 194 195 if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE)) 196 niagara_kstat_init(); 197 } 198 199 /*ARGSUSED*/ 200 void 201 cpu_uninit_private(struct cpu *cp) 202 { 203 extern void niagara_kstat_fini(void); 204 205 ASSERT(MUTEX_HELD(&cpu_lock)); 206 207 if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE)) 208 niagara_kstat_fini(); 209 } 210 211 /* 212 * On Niagara2, any flush will cause all preceding stores to be 213 * synchronized wrt the i$, regardless of address or ASI. In fact, 214 * the address is ignored, so we always flush address 0. 215 */ 216 /*ARGSUSED*/ 217 void 218 dtrace_flush_sec(uintptr_t addr) 219 { 220 doflush(0); 221 } 222 223 /* 224 * Trapstat support for Niagara2 processor 225 * The Niagara2 provides HWTW support for TSB lookup and with HWTW 226 * enabled no TSB hit information will be available. Therefore setting 227 * the time spent in TLB miss handler for TSB hits to 0. 228 */ 229 int 230 cpu_trapstat_conf(int cmd) 231 { 232 int status = 0; 233 234 switch (cmd) { 235 case CPU_TSTATCONF_INIT: 236 case CPU_TSTATCONF_FINI: 237 case CPU_TSTATCONF_ENABLE: 238 case CPU_TSTATCONF_DISABLE: 239 break; 240 default: 241 status = EINVAL; 242 break; 243 } 244 return (status); 245 } 246 247 void 248 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 249 { 250 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 251 int i; 252 253 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 254 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 255 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 256 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 257 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 258 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 259 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 260 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 261 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 262 } 263 } 264 265 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */ 266 uint_t 267 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc) 268 { 269 uint_t color; 270 271 ASSERT(szc <= TTE256M); 272 273 pfn = PFN_BASE(pfn, szc); 274 color = ((pfn >> 15) ^ pfn) & 0x1f; 275 if (szc >= TTE4M) 276 return (color); 277 278 color = (color << 2) | ((pfn >> 5) & 0x3); 279 280 return (szc <= TTE64K ? color : (color >> 1)); 281 } 282 283 #if TTE256M != 5 284 #error TTE256M is not 5 285 #endif 286 287 uint_t 288 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask) 289 { 290 static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f}; 291 ASSERT(szc < TTE256M); 292 293 mask &= ni2_color_masks[szc]; 294 return ((szc == TTE64K || szc == TTE512K) ? (mask >> 1) : mask); 295 } 296 297 uint_t 298 page_get_nsz_color_cpu(uchar_t szc, uint_t color) 299 { 300 ASSERT(szc < TTE256M); 301 return ((szc == TTE64K || szc == TTE512K) ? (color >> 1) : color); 302 } 303 304 uint_t 305 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc) 306 { 307 ASSERT(nszc > szc); 308 ASSERT(nszc <= TTE256M); 309 310 if (szc <= TTE64K) 311 return ((nszc >= TTE4M) ? 2 : ((nszc >= TTE512K) ? 1 : 0)); 312 if (szc == TTE512K) 313 return (1); 314 315 return (0); 316 } 317 318 /*ARGSUSED*/ 319 pfn_t 320 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color, 321 uint_t ceq_mask, uint_t color_mask) 322 { 323 pfn_t pstep = PNUM_SIZE(szc); 324 pfn_t npfn, pfn_ceq_mask, pfn_color; 325 pfn_t tmpmask, mask = (pfn_t)-1; 326 327 ASSERT((color & ~ceq_mask) == 0); 328 329 if (((page_pfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) { 330 331 /* we start from the page with correct color */ 332 if (szc >= TTE512K) { 333 if (szc >= TTE4M) { 334 /* page color is PA[32:28] */ 335 pfn_ceq_mask = ceq_mask << 15; 336 } else { 337 /* page color is PA[32:28].PA[19:19] */ 338 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 339 ((ceq_mask >> 1) << 15); 340 } 341 pfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 342 return (pfn); 343 } else { 344 /* 345 * We deal 64K or 8K page. Check if we could the 346 * satisfy the request without changing PA[32:28] 347 */ 348 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 349 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 350 351 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 352 return (npfn); 353 354 /* 355 * for next pfn we have to change bits PA[32:28] 356 * set PA[63:28] and PA[19:18] of the next pfn 357 */ 358 npfn = (pfn >> 15) << 15; 359 npfn |= (ceq_mask & color & 3) << 5; 360 pfn_ceq_mask = (szc == TTE8K) ? 0 : 361 (ceq_mask & 0x1c) << 13; 362 npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask); 363 364 /* 365 * set bits PA[17:13] to match the color 366 */ 367 ceq_mask >>= 2; 368 color = (color >> 2) & ceq_mask; 369 npfn |= ((npfn >> 15) ^ color) & ceq_mask; 370 return (npfn); 371 } 372 } 373 374 /* 375 * we start from the page with incorrect color - rare case 376 */ 377 if (szc >= TTE512K) { 378 if (szc >= TTE4M) { 379 /* page color is in bits PA[32:28] */ 380 npfn = ((pfn >> 20) << 20) | (color << 15); 381 pfn_ceq_mask = (ceq_mask << 15) | 0x7fff; 382 } else { 383 /* try get the right color by changing bit PA[19:19] */ 384 npfn = pfn + pstep; 385 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & 386 ceq_mask) == 0) 387 return (npfn); 388 389 /* page color is PA[32:28].PA[19:19] */ 390 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 391 ((ceq_mask >> 1) << 15) | (0xff << 7); 392 pfn_color = ((color & 1) << 6) | ((color >> 1) << 15); 393 npfn = ((pfn >> 20) << 20) | pfn_color; 394 } 395 396 while (npfn <= pfn) { 397 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 398 } 399 return (npfn); 400 } 401 402 /* 403 * We deal 64K or 8K page of incorrect color. 404 * Try correcting color without changing PA[32:28] 405 */ 406 407 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 408 pfn_color = ((color & 3) << 5) | (color >> 2); 409 npfn = (pfn & ~(pfn_t)0x7f); 410 npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 411 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 412 413 if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0) { 414 415 /* the color is fixed - find the next page */ 416 while (npfn <= pfn) { 417 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 418 } 419 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 420 return (npfn); 421 } 422 423 /* to fix the color need to touch PA[32:28] */ 424 npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) : 425 (((pfn >> 18) << 18) | ((color & 0x1c) << 13)); 426 tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13; 427 428 while (npfn <= pfn) { 429 npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask); 430 } 431 432 /* set bits PA[19:13] to match the color */ 433 npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 434 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 435 436 ASSERT(((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0); 437 438 return (npfn); 439 } 440 441 /* 442 * init page coloring 443 */ 444 void 445 page_coloring_init_cpu() 446 { 447 int i; 448 449 hw_page_array[0].hp_colors = 1 << 7; 450 hw_page_array[1].hp_colors = 1 << 7; 451 hw_page_array[2].hp_colors = 1 << 6; 452 453 for (i = 3; i < mmu_page_sizes; i++) { 454 hw_page_array[i].hp_colors = 1 << 5; 455 } 456 } 457 458 /* 459 * group colorequiv colors on N2 by low order bits of the color first 460 */ 461 void 462 page_set_colorequiv_arr_cpu(void) 463 { 464 static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0}; 465 466 if (colorequiv > 1) { 467 int i; 468 uint_t sv_a = lowbit(colorequiv) - 1; 469 470 if (sv_a > 15) 471 sv_a = 15; 472 473 for (i = 0; i < MMU_PAGE_SIZES; i++) { 474 uint_t colors; 475 uint_t a = sv_a; 476 477 if ((colors = hw_page_array[i].hp_colors) <= 1) 478 continue; 479 while ((colors >> a) == 0) 480 a--; 481 if (a > (colorequivszc[i] & 0xf) + 482 (colorequivszc[i] >> 4)) { 483 if (a <= nequiv_shades_log2[i]) { 484 colorequivszc[i] = a; 485 } else { 486 colorequivszc[i] = 487 ((a - nequiv_shades_log2[i]) << 4) | 488 nequiv_shades_log2[i]; 489 } 490 } 491 } 492 } 493 } 494