xref: /illumos-gate/usr/src/uts/sun4v/cpu/niagara2.c (revision 932dc8e59b0d8971fdc9b56f1eb7ecd30fea5eb4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/types.h>
29 #include <sys/systm.h>
30 #include <sys/archsystm.h>
31 #include <sys/machparam.h>
32 #include <sys/machsystm.h>
33 #include <sys/cpu.h>
34 #include <sys/elf_SPARC.h>
35 #include <vm/hat_sfmmu.h>
36 #include <vm/page.h>
37 #include <vm/vm_dep.h>
38 #include <sys/cpuvar.h>
39 #include <sys/async.h>
40 #include <sys/cmn_err.h>
41 #include <sys/debug.h>
42 #include <sys/dditypes.h>
43 #include <sys/sunddi.h>
44 #include <sys/cpu_module.h>
45 #include <sys/prom_debug.h>
46 #include <sys/vmsystm.h>
47 #include <sys/prom_plat.h>
48 #include <sys/sysmacros.h>
49 #include <sys/intreg.h>
50 #include <sys/machtrap.h>
51 #include <sys/ontrap.h>
52 #include <sys/ivintr.h>
53 #include <sys/atomic.h>
54 #include <sys/panic.h>
55 #include <sys/dtrace.h>
56 #include <sys/simulate.h>
57 #include <sys/fault.h>
58 #include <sys/niagara2regs.h>
59 #include <sys/hsvc.h>
60 #include <sys/trapstat.h>
61 
62 uint_t root_phys_addr_lo_mask = 0xffffffffU;
63 char cpu_module_name[] = "SUNW,UltraSPARC-T2";
64 
65 /*
66  * Hypervisor services information for the NIAGARA2 CPU module
67  */
68 static boolean_t niagara2_hsvc_available = B_TRUE;
69 static uint64_t niagara2_sup_minor;		/* Supported minor number */
70 static hsvc_info_t niagara2_hsvc = {
71 	HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR,
72 	NIAGARA2_HSVC_MINOR, cpu_module_name
73 };
74 
75 void
76 cpu_setup(void)
77 {
78 	extern int mmu_exported_pagesize_mask;
79 	extern int cpc_has_overflow_intr;
80 	int status;
81 
82 	/*
83 	 * Negotiate the API version for Niagara2 specific hypervisor
84 	 * services.
85 	 */
86 	status = hsvc_register(&niagara2_hsvc, &niagara2_sup_minor);
87 	if (status != 0) {
88 		cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services "
89 		    "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d",
90 		    niagara2_hsvc.hsvc_modname, niagara2_hsvc.hsvc_group,
91 		    niagara2_hsvc.hsvc_major, niagara2_hsvc.hsvc_minor, status);
92 		niagara2_hsvc_available = B_FALSE;
93 	}
94 
95 	/*
96 	 * The setup common to all CPU modules is done in cpu_setup_common
97 	 * routine.
98 	 */
99 	cpu_setup_common(NULL);
100 
101 	cache |= (CACHE_PTAG | CACHE_IOCOHERENT);
102 
103 	if ((mmu_exported_pagesize_mask &
104 	    DEFAULT_SUN4V_MMU_PAGESIZE_MASK) !=
105 	    DEFAULT_SUN4V_MMU_PAGESIZE_MASK)
106 		cmn_err(CE_PANIC, "machine description"
107 		    " does not have required sun4v page sizes"
108 		    " 8K, 64K and 4M: MD mask is 0x%x",
109 		    mmu_exported_pagesize_mask);
110 
111 	cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT;
112 
113 	/*
114 	 * Niagara2 supports a 48-bit subset of the full 64-bit virtual
115 	 * address space. Virtual addresses between 0x0000800000000000
116 	 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole"
117 	 * and must never be mapped. In addition, software must not use
118 	 * pages within 4GB of the VA hole as instruction pages to
119 	 * avoid problems with prefetching into the VA hole.
120 	 */
121 	hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32));
122 	hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32));
123 
124 	/*
125 	 * Niagara2 has a performance counter overflow interrupt
126 	 */
127 	cpc_has_overflow_intr = 1;
128 
129 	/*
130 	 * Enable 4M pages for OOB.
131 	 */
132 	max_uheap_lpsize = MMU_PAGESIZE4M;
133 	max_ustack_lpsize = MMU_PAGESIZE4M;
134 	max_privmap_lpsize = MMU_PAGESIZE4M;
135 }
136 
137 /*
138  * Set the magic constants of the implementation.
139  */
140 void
141 cpu_fiximp(struct cpu_node *cpunode)
142 {
143 	/*
144 	 * The Cache node is optional in MD. Therefore in case "Cache"
145 	 * node does not exists in MD, set the default L2 cache associativity,
146 	 * size, linesize.
147 	 */
148 	if (cpunode->ecache_size == 0)
149 		cpunode->ecache_size = L2CACHE_SIZE;
150 	if (cpunode->ecache_linesize == 0)
151 		cpunode->ecache_linesize = L2CACHE_LINESIZE;
152 	if (cpunode->ecache_associativity == 0)
153 		cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY;
154 }
155 
156 static int niagara2_cpucnt;
157 
158 void
159 cpu_init_private(struct cpu *cp)
160 {
161 	extern int niagara_kstat_init(void);
162 
163 	/*
164 	 * The cpu_ipipe and cpu_fpu fields are initialized based on
165 	 * the execution unit sharing information from the MD. They default
166 	 * to the virtual CPU id in the absence of such information.
167 	 */
168 	cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping;
169 	if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND)
170 		cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
171 
172 	cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping;
173 	if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND)
174 		cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id);
175 
176 	/*
177 	 * Niagara 2 defines the core to be at the FPU level
178 	 */
179 	cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu;
180 
181 	ASSERT(MUTEX_HELD(&cpu_lock));
182 	if ((niagara2_cpucnt++ == 0) && (niagara2_hsvc_available == B_TRUE))
183 		(void) niagara_kstat_init();
184 }
185 
186 /*ARGSUSED*/
187 void
188 cpu_uninit_private(struct cpu *cp)
189 {
190 	extern int niagara_kstat_fini(void);
191 
192 	ASSERT(MUTEX_HELD(&cpu_lock));
193 	if ((--niagara2_cpucnt == 0) && (niagara2_hsvc_available == B_TRUE))
194 		(void) niagara_kstat_fini();
195 }
196 
197 /*
198  * On Niagara2, any flush will cause all preceding stores to be
199  * synchronized wrt the i$, regardless of address or ASI.  In fact,
200  * the address is ignored, so we always flush address 0.
201  */
202 /*ARGSUSED*/
203 void
204 dtrace_flush_sec(uintptr_t addr)
205 {
206 	doflush(0);
207 }
208 
209 /*
210  * Trapstat support for Niagara2 processor
211  * The Niagara2 provides HWTW support for TSB lookup and with HWTW
212  * enabled no TSB hit information will be available. Therefore setting
213  * the time spent in TLB miss handler for TSB hits to 0.
214  */
215 int
216 cpu_trapstat_conf(int cmd)
217 {
218 	int status = 0;
219 
220 	switch (cmd) {
221 	case CPU_TSTATCONF_INIT:
222 	case CPU_TSTATCONF_FINI:
223 	case CPU_TSTATCONF_ENABLE:
224 	case CPU_TSTATCONF_DISABLE:
225 		break;
226 	default:
227 		status = EINVAL;
228 		break;
229 	}
230 	return (status);
231 }
232 
233 void
234 cpu_trapstat_data(void *buf, uint_t tstat_pgszs)
235 {
236 	tstat_pgszdata_t	*tstatp = (tstat_pgszdata_t *)buf;
237 	int	i;
238 
239 	for (i = 0; i < tstat_pgszs; i++, tstatp++) {
240 		tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0;
241 		tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0;
242 		tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0;
243 		tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0;
244 		tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
245 		tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
246 		tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0;
247 		tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0;
248 	}
249 }
250 
251 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */
252 uint_t
253 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc)
254 {
255 	uint_t color;
256 
257 	ASSERT(szc <= TTE256M);
258 
259 	pfn = PFN_BASE(pfn, szc);
260 	color = ((pfn >> 15) ^ pfn) & 0x1f;
261 	if (szc >= TTE4M)
262 		return (color);
263 
264 	color = (color << 2) | ((pfn >> 5) & 0x3);
265 
266 	return (szc <= TTE64K ? color : (color >> 1));
267 }
268 
269 #if TTE256M != 5
270 #error TTE256M is not 5
271 #endif
272 
273 uint_t
274 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask)
275 {
276 	static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f};
277 	ASSERT(szc < TTE256M);
278 
279 	mask &= ni2_color_masks[szc];
280 	return ((szc == TTE64K || szc == TTE512K) ? (mask >> 1) : mask);
281 }
282 
283 uint_t
284 page_get_nsz_color_cpu(uchar_t szc, uint_t color)
285 {
286 	ASSERT(szc < TTE256M);
287 	return ((szc == TTE64K || szc == TTE512K) ? (color >> 1) : color);
288 }
289 
290 uint_t
291 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc)
292 {
293 	ASSERT(nszc > szc);
294 	ASSERT(nszc <= TTE256M);
295 
296 	if (szc <= TTE64K)
297 		return ((nszc >= TTE4M) ? 2 : ((nszc >= TTE512K) ? 1 : 0));
298 	if (szc == TTE512K)
299 		return (1);
300 
301 	return (0);
302 }
303 
304 /*ARGSUSED*/
305 pfn_t
306 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color,
307     uint_t ceq_mask, uint_t color_mask)
308 {
309 	pfn_t pstep = PNUM_SIZE(szc);
310 	pfn_t npfn, pfn_ceq_mask, pfn_color;
311 	pfn_t tmpmask, mask = (pfn_t)-1;
312 
313 	ASSERT((color & ~ceq_mask) == 0);
314 
315 	if (((page_pfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0) {
316 
317 		/* we start from the page with correct color */
318 		if (szc >= TTE512K) {
319 			if (szc >= TTE4M) {
320 				/* page color is PA[32:28] */
321 				pfn_ceq_mask = ceq_mask << 15;
322 			} else {
323 				/* page color is PA[32:28].PA[19:19] */
324 				pfn_ceq_mask = ((ceq_mask & 1) << 6) |
325 				    ((ceq_mask >> 1) << 15);
326 			}
327 			pfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
328 			return (pfn);
329 		} else {
330 			/*
331 			 * We deal 64K or 8K page. Check if we could the
332 			 * satisfy the request without changing PA[32:28]
333 			 */
334 			pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2);
335 			npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask);
336 
337 			if ((((npfn ^ pfn) >> 15) & 0x1f) == 0)
338 				return (npfn);
339 
340 			/*
341 			 * for next pfn we have to change bits PA[32:28]
342 			 * set PA[63:28] and PA[19:18] of the next pfn
343 			 */
344 			npfn = (pfn >> 15) << 15;
345 			npfn |= (ceq_mask & color & 3) << 5;
346 			pfn_ceq_mask = (szc == TTE8K) ? 0 :
347 			    (ceq_mask & 0x1c) << 13;
348 			npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask);
349 
350 			/*
351 			 * set bits PA[17:13] to match the color
352 			 */
353 			ceq_mask >>= 2;
354 			color = (color >> 2) & ceq_mask;
355 			npfn |= ((npfn >> 15) ^ color) & ceq_mask;
356 			return (npfn);
357 		}
358 	}
359 
360 	/*
361 	 * we start from the page with incorrect color - rare case
362 	 */
363 	if (szc >= TTE512K) {
364 		if (szc >= TTE4M) {
365 			/* page color is in bits PA[32:28] */
366 			npfn = ((pfn >> 20) << 20) | (color << 15);
367 			pfn_ceq_mask = (ceq_mask << 15) | 0x7fff;
368 		} else {
369 			/* try get the right color by changing bit PA[19:19] */
370 			npfn = pfn + pstep;
371 			if (((page_pfn_2_color_cpu(npfn, szc) ^ color) &
372 			    ceq_mask) == 0)
373 				return (npfn);
374 
375 			/* page color is PA[32:28].PA[19:19] */
376 			pfn_ceq_mask = ((ceq_mask & 1) << 6) |
377 			    ((ceq_mask >> 1) << 15) | (0xff << 7);
378 			pfn_color = ((color & 1) << 6) | ((color >> 1) << 15);
379 			npfn = ((pfn >> 20) << 20) | pfn_color;
380 		}
381 
382 		while (npfn <= pfn) {
383 			npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask);
384 		}
385 		return (npfn);
386 	}
387 
388 	/*
389 	 * We deal 64K or 8K page of incorrect color.
390 	 * Try correcting color without changing PA[32:28]
391 	 */
392 
393 	pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2);
394 	pfn_color = ((color & 3) << 5) | (color >> 2);
395 	npfn = (pfn & ~(pfn_t)0x7f);
396 	npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask;
397 	npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn;
398 
399 	if (((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0) {
400 
401 		/* the color is fixed - find the next page */
402 		while (npfn <= pfn) {
403 			npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask);
404 		}
405 		if ((((npfn ^ pfn) >> 15) & 0x1f) == 0)
406 			return (npfn);
407 	}
408 
409 	/* to fix the color need to touch PA[32:28] */
410 	npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) :
411 	    (((pfn >> 18) << 18) | ((color & 0x1c) << 13));
412 	tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13;
413 
414 	while (npfn <= pfn) {
415 		npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask);
416 	}
417 
418 	/* set bits PA[19:13] to match the color */
419 	npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask;
420 	npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn;
421 
422 	ASSERT(((page_pfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0);
423 
424 	return (npfn);
425 }
426 
427 /*
428  * init page coloring
429  */
430 void
431 page_coloring_init_cpu()
432 {
433 	int i;
434 
435 	hw_page_array[0].hp_colors = 1 << 7;
436 	hw_page_array[1].hp_colors = 1 << 7;
437 	hw_page_array[2].hp_colors = 1 << 6;
438 
439 	for (i = 3; i < mmu_page_sizes; i++) {
440 		hw_page_array[i].hp_colors = 1 << 5;
441 	}
442 }
443