1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <sys/cpuvar.h> 39 #include <sys/async.h> 40 #include <sys/cmn_err.h> 41 #include <sys/debug.h> 42 #include <sys/dditypes.h> 43 #include <sys/sunddi.h> 44 #include <sys/cpu_module.h> 45 #include <sys/prom_debug.h> 46 #include <sys/vmsystm.h> 47 #include <sys/prom_plat.h> 48 #include <sys/sysmacros.h> 49 #include <sys/intreg.h> 50 #include <sys/machtrap.h> 51 #include <sys/ontrap.h> 52 #include <sys/ivintr.h> 53 #include <sys/atomic.h> 54 #include <sys/panic.h> 55 #include <sys/dtrace.h> 56 #include <vm/seg_spt.h> 57 #include <sys/simulate.h> 58 #include <sys/fault.h> 59 60 61 uint_t root_phys_addr_lo_mask = 0xffffffffU; 62 63 void 64 cpu_setup(void) 65 { 66 extern int mmu_exported_pagesize_mask; 67 char *generic_isa_set[] = { 68 "sparcv9+vis", 69 "sparcv8plus+vis", 70 NULL 71 }; 72 73 /* 74 * The setup common to all CPU modules is done in cpu_setup_common 75 * routine. 76 */ 77 cpu_setup_common(generic_isa_set); 78 79 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 80 81 if (broken_md_flag) { 82 /* 83 * Turn on the missing bits supported by sun4v architecture in 84 * MMU pagesize mask returned by MD. 85 */ 86 mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK; 87 } else { 88 /* 89 * According to sun4v architecture each processor must 90 * support 8K, 64K and 4M page sizes. If any of the page 91 * size is missing from page size mask, then panic. 92 */ 93 if ((mmu_exported_pagesize_mask & 94 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 95 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 96 cmn_err(CE_PANIC, "machine description" 97 " does not have required sun4v page sizes" 98 " 8K, 64K and 4M: MD mask is 0x%x", 99 mmu_exported_pagesize_mask); 100 } 101 102 /* 103 * If processor supports the subset of full 64-bit virtual 104 * address space, then set VA hole accordingly. 105 */ 106 if (va_bits < VA_ADDRESS_SPACE_BITS) { 107 hole_start = (caddr_t)(1ull << (va_bits - 1)); 108 hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1))); 109 } else { 110 hole_start = hole_end = 0; 111 } 112 } 113 114 void 115 cpu_fiximp(struct cpu_node *cpunode) 116 { 117 /* 118 * The Cache node is optional in MD. Therefore in case "Cache" 119 * does not exists in MD, set the default L2 cache associativity, 120 * size, linesize for generic CPU module. 121 */ 122 if (cpunode->ecache_size == 0) 123 cpunode->ecache_size = 0x100000; 124 if (cpunode->ecache_linesize == 0) 125 cpunode->ecache_linesize = 64; 126 if (cpunode->ecache_associativity == 0) 127 cpunode->ecache_associativity = 1; 128 } 129 130 void 131 dtrace_flush_sec(uintptr_t addr) 132 { 133 pfn_t pfn; 134 proc_t *procp = ttoproc(curthread); 135 page_t *pp; 136 caddr_t va; 137 138 pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr); 139 if (pfn != -1) { 140 ASSERT(pf_is_memory(pfn)); 141 pp = page_numtopp_noreclaim(pfn, SE_SHARED); 142 if (pp != NULL) { 143 va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr); 144 /* sparc needs 8-byte align */ 145 doflush((caddr_t)((uintptr_t)va & -8l)); 146 ppmapout(va); 147 page_unlock(pp); 148 } 149 } 150 } 151 152 void 153 cpu_map_exec_units(struct cpu *cp) 154 { 155 ASSERT(MUTEX_HELD(&cpu_lock)); 156 157 /* 158 * The cpu_ipipe and cpu_fpu fields are initialized based on 159 * the execution unit sharing information from the MD. They 160 * default to the CPU id in the absence of such information. 161 */ 162 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 163 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 164 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 165 166 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 167 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 168 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 169 170 cp->cpu_m.cpu_core = (id_t)(cp->cpu_id); 171 172 /* 173 * The cpu_chip field is set to invalid(unknown) for generic cpu. 174 */ 175 cp->cpu_m.cpu_chip = CPU_CHIPID_INVALID; 176 } 177 178 void 179 cpu_init_private(struct cpu *cp) 180 { 181 cpu_map_exec_units(cp); 182 } 183 184 /*ARGSUSED*/ 185 void 186 cpu_uninit_private(struct cpu *cp) 187 {} 188 189 /* 190 * Invalidate a TSB. Since this needs to work on all sun4v 191 * architecture compliant processors, we use the old method of 192 * walking the TSB, setting each tag to TSBTAG_INVALID. 193 */ 194 void 195 cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 196 { 197 struct tsbe *tsbaddr; 198 199 for (tsbaddr = (struct tsbe *)tsb_base; 200 (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes); 201 tsbaddr++) { 202 tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID; 203 } 204 } 205 206 /* 207 * Sun4v kernel must emulate code a generic sun4v processor may not support 208 * i.e. VIS1 and VIS2. 209 */ 210 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 211 #define IS_IBIT_SET(x) (x & 0x2000) 212 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 213 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 214 (op == 3 && (op3 == IOP_V8_LDDFA || \ 215 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 216 int 217 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 218 { 219 char *badaddr; 220 int instr; 221 uint_t optype, op3, asi; 222 uint_t rd, ignor; 223 224 if (!USERMODE(rp->r_tstate)) 225 return (-1); 226 227 instr = fetch_user_instr((caddr_t)rp->r_pc); 228 229 rd = (instr >> 25) & 0x1f; 230 optype = (instr >> 30) & 0x3; 231 op3 = (instr >> 19) & 0x3f; 232 ignor = (instr >> 5) & 0xff; 233 if (IS_IBIT_SET(instr)) { 234 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 235 TSTATE_ASI_MASK); 236 } else { 237 asi = ignor; 238 } 239 240 if (!IS_VIS1(optype, op3) && 241 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 242 return (-1); 243 } 244 switch (simulate_unimp(rp, &badaddr)) { 245 case SIMU_RETRY: 246 break; /* regs are already set up */ 247 /*NOTREACHED*/ 248 249 case SIMU_SUCCESS: 250 /* 251 * skip the successfully 252 * simulated instruction 253 */ 254 rp->r_pc = rp->r_npc; 255 rp->r_npc += 4; 256 break; 257 /*NOTREACHED*/ 258 259 case SIMU_FAULT: 260 siginfo->si_signo = SIGSEGV; 261 siginfo->si_code = SEGV_MAPERR; 262 siginfo->si_addr = badaddr; 263 *fault = FLTBOUNDS; 264 break; 265 266 case SIMU_DZERO: 267 siginfo->si_signo = SIGFPE; 268 siginfo->si_code = FPE_INTDIV; 269 siginfo->si_addr = (caddr_t)rp->r_pc; 270 *fault = FLTIZDIV; 271 break; 272 273 case SIMU_UNALIGN: 274 siginfo->si_signo = SIGBUS; 275 siginfo->si_code = BUS_ADRALN; 276 siginfo->si_addr = badaddr; 277 *fault = FLTACCESS; 278 break; 279 280 case SIMU_ILLEGAL: 281 default: 282 siginfo->si_signo = SIGILL; 283 op3 = (instr >> 19) & 0x3F; 284 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 285 (op3 == IOP_V8_STDFA))) 286 siginfo->si_code = ILL_ILLADR; 287 else 288 siginfo->si_code = ILL_ILLOPC; 289 siginfo->si_addr = (caddr_t)rp->r_pc; 290 *fault = FLTILL; 291 break; 292 } 293 return (0); 294 } 295 296 /* 297 * Trapstat support for generic sun4v processor 298 */ 299 int 300 cpu_trapstat_conf(int cmd) 301 { 302 int status; 303 304 switch (cmd) { 305 case CPU_TSTATCONF_INIT: 306 case CPU_TSTATCONF_FINI: 307 case CPU_TSTATCONF_ENABLE: 308 case CPU_TSTATCONF_DISABLE: 309 status = ENOTSUP; 310 break; 311 312 default: 313 status = EINVAL; 314 break; 315 } 316 return (status); 317 } 318 319 /*ARGSUSED*/ 320 void 321 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 322 { 323 } 324