17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
57c478bdstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
67c478bdstevel@tonic-gate * (the "License").  You may not use this file except in compliance
77c478bdstevel@tonic-gate * with the License.
87c478bdstevel@tonic-gate *
97c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
117c478bdstevel@tonic-gate * See the License for the specific language governing permissions
127c478bdstevel@tonic-gate * and limitations under the License.
137c478bdstevel@tonic-gate *
147c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
157c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
177c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
187c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
197c478bdstevel@tonic-gate *
207c478bdstevel@tonic-gate * CDDL HEADER END
217c478bdstevel@tonic-gate */
227c478bdstevel@tonic-gate/*
237c478bdstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
247c478bdstevel@tonic-gate * Use is subject to license terms.
257c478bdstevel@tonic-gate */
262a1fd0fPeter Tribble/*
272a1fd0fPeter Tribble * Copyright 2019 Peter Tribble.
282a1fd0fPeter Tribble */
297c478bdstevel@tonic-gate
307c478bdstevel@tonic-gate#ifndef _SYS_SPITREGS_H
317c478bdstevel@tonic-gate#define	_SYS_SPITREGS_H
327c478bdstevel@tonic-gate
337c478bdstevel@tonic-gate#ifdef	__cplusplus
347c478bdstevel@tonic-gateextern "C" {
357c478bdstevel@tonic-gate#endif
367c478bdstevel@tonic-gate
377c478bdstevel@tonic-gate/*
387c478bdstevel@tonic-gate * This file is cpu dependent.
397c478bdstevel@tonic-gate */
407c478bdstevel@tonic-gate
417c478bdstevel@tonic-gate/*
427c478bdstevel@tonic-gate * The mid is the same as the cpu id.
437c478bdstevel@tonic-gate * We might want to change this later
447c478bdstevel@tonic-gate */
457c478bdstevel@tonic-gate#define	CPUID_TO_UPAID(cpuid)	(cpuid)
467c478bdstevel@tonic-gate
477c478bdstevel@tonic-gate/*
487c478bdstevel@tonic-gate * LSU Control Register
497c478bdstevel@tonic-gate *
507c478bdstevel@tonic-gate * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
517c478bdstevel@tonic-gate * | Resv | PM | VM | PR | PW | VR | VW | Rsv |  FM  | DM | IM | DC | IC|
527c478bdstevel@tonic-gate * +------+----+----+----+----+----+----+-----+------+----+----+----+---+
537c478bdstevel@tonic-gate *  63  41   33   25   24   23	 22   21   20  19   4	3    2	  1   0
547c478bdstevel@tonic-gate *
557c478bdstevel@tonic-gate */
567c478bdstevel@tonic-gate
577c478bdstevel@tonic-gate#define	LSU_IC		0x00000000001	/* icache enable */
587c478bdstevel@tonic-gate#define	LSU_DC		0x00000000002	/* dcache enable */
597c478bdstevel@tonic-gate#define	LSU_IM		0x00000000004	/* immu enable */
607c478bdstevel@tonic-gate#define	LSU_DM		0x00000000008	/* dmmu enable */
617c478bdstevel@tonic-gate#define	LSU_FM		0x000000FFFF0	/* parity mask */
627c478bdstevel@tonic-gate#define	LSU_VW		0x00000200000	/* virtual watchpoint write enable */
637c478bdstevel@tonic-gate#define	LSU_VR		0x00000400000	/* virtual watchpoint read enable */
647c478bdstevel@tonic-gate#define	LSU_PW		0x00000800000	/* physical watchpoint write enable */
657c478bdstevel@tonic-gate#define	LSU_PR		0x00001000000	/* physical watchpoint read enable */
667c478bdstevel@tonic-gate#define	LSU_VM		0x001fe000000	/* virtual watchpoint byte mask */
677c478bdstevel@tonic-gate#define	LSU_PM		0x1fe00000000	/* physical watch point byte mask */
687c478bdstevel@tonic-gate
697c478bdstevel@tonic-gate#define	LSU_VM_SHIFT	25
707c478bdstevel@tonic-gate#define	LSU_PM_SHIFT	33
717c478bdstevel@tonic-gate
727c478bdstevel@tonic-gate/*
737c478bdstevel@tonic-gate * Defines for the different types of dcache_flush
747c478bdstevel@tonic-gate * it is stored in dflush_type
757c478bdstevel@tonic-gate */
767c478bdstevel@tonic-gate#define	FLUSHALL_TYPE	0x0		/* blasts all cache lines */
777c478bdstevel@tonic-gate#define	FLUSHMATCH_TYPE	0x1		/* flush entire cache but check each */
787c478bdstevel@tonic-gate					/* each line for a match */
797c478bdstevel@tonic-gate#define	FLUSHPAGE_TYPE	0x2		/* flush only one page and check */
807c478bdstevel@tonic-gate					/* each line for a match */
817c478bdstevel@tonic-gate
827c478bdstevel@tonic-gate/*
837c478bdstevel@tonic-gate * D-Cache Tag Data Register
847c478bdstevel@tonic-gate *
857c478bdstevel@tonic-gate * +----------+--------+----------+
867c478bdstevel@tonic-gate * | Reserved | DC_Tag | DC_Valid |
877c478bdstevel@tonic-gate * +----------+--------+----------+
887c478bdstevel@tonic-gate *  63	    30 29    2	1	 0
897c478bdstevel@tonic-gate *
907c478bdstevel@tonic-gate */
917c478bdstevel@tonic-gate#define	ICACHE_FLUSHSZ	0x20	/* one line in i$ */
927c478bdstevel@tonic-gate#define	DC_PTAG_SHIFT	34
937c478bdstevel@tonic-gate#define	DC_LINE_SHIFT	30
947c478bdstevel@tonic-gate#define	SF_DC_VBIT_SHIFT 2
957c478bdstevel@tonic-gate#define	SF_DC_VBIT_MASK	0x3
967c478bdstevel@tonic-gate#define	IC_LINE_SHIFT	3
977c478bdstevel@tonic-gate#define	IC_LINE		512
987c478bdstevel@tonic-gate#define	INDEX_BIT_SHIFT	13
997c478bdstevel@tonic-gate
1007c478bdstevel@tonic-gate/*
1017c478bdstevel@tonic-gate * Definitions of sun4u cpu implementations as specified in version register
1027c478bdstevel@tonic-gate */
1037c478bdstevel@tonic-gate#define	SPITFIRE_IMPL	0x10
1047c478bdstevel@tonic-gate#define	IS_SPITFIRE(impl)	((impl) == SPITFIRE_IMPL)
1057c478bdstevel@tonic-gate#define	SPITFIRE_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
1067c478bdstevel@tonic-gate#define	SPITFIRE_MINOR_VERSION(rev)	((rev) & 0xf)
1077c478bdstevel@tonic-gate
1087c478bdstevel@tonic-gate#define	BLACKBIRD_IMPL	0x11
1097c478bdstevel@tonic-gate#define	IS_BLACKBIRD(impl)	((impl) == BLACKBIRD_IMPL)
1107c478bdstevel@tonic-gate#define	BLACKBIRD_MAJOR_VERSION(rev)	(((rev) >> 4) & 0xf)
1117c478bdstevel@tonic-gate#define	BLACKBIRD_MINOR_VERSION(rev)	((rev) & 0xf)
1127c478bdstevel@tonic-gate
1137c478bdstevel@tonic-gate#define	SABRE_IMPL	0x12
1147c478bdstevel@tonic-gate#define	HUMMBRD_IMPL	0x13
1157c478bdstevel@tonic-gate
1167c478bdstevel@tonic-gate/*
1177c478bdstevel@tonic-gate * Bits of Spitfire Asynchronous Fault Status Register
1187c478bdstevel@tonic-gate */
1197c478bdstevel@tonic-gate#define	P_AFSR_STICKY	0x00000001FFF00000ULL /* mask for all sticky bits */
1207c478bdstevel@tonic-gate#define	P_AFSR_ERRS	0x000000001EE00000ULL /* mask for remaining errors */
1217c478bdstevel@tonic-gate#define	P_AFSR_ME	0x0000000100000000ULL /* errors > 1, same type!=CE */
1227c478bdstevel@tonic-gate#define	P_AFSR_PRIV	0x0000000080000000ULL /* priv/supervisor access */
1237c478bdstevel@tonic-gate#define	P_AFSR_ISAP	0x0000000040000000ULL /* incoming system addr. parity */
1247c478bdstevel@tonic-gate#define	P_AFSR_ETP	0x0000000020000000ULL /* ecache tag parity */
1257c478bdstevel@tonic-gate#define	P_AFSR_IVUE	0x0000000010000000ULL /* interrupt vector with UE */
1267c478bdstevel@tonic-gate#define	P_AFSR_TO	0x0000000008000000ULL /* bus timeout */
1277c478bdstevel@tonic-gate#define	P_AFSR_BERR	0x0000000004000000ULL /* bus error */
1287c478bdstevel@tonic-gate#define	P_AFSR_LDP	0x0000000002000000ULL /* data parity error from SDB */
1297c478bdstevel@tonic-gate#define	P_AFSR_CP	0x0000000001000000ULL /* copyout parity error */
1307c478bdstevel@tonic-gate#define	P_AFSR_WP	0x0000000000800000ULL /* writeback ecache data parity */
1317c478bdstevel@tonic-gate#define	P_AFSR_EDP	0x0000000000400000ULL /* ecache data parity */
1327c478bdstevel@tonic-gate#define	P_AFSR_UE	0x0000000000200000ULL /* uncorrectable ECC error */
1337c478bdstevel@tonic-gate#define	P_AFSR_CE	0x0000000000100000ULL /* correctable ECC error */
1347c478bdstevel@tonic-gate#define	P_AFSR_ETS	0x00000000000F0000ULL /* cache tag parity syndrome */
1357c478bdstevel@tonic-gate#define	P_AFSR_P_SYND	0x000000000000FFFFULL /* data parity syndrome */
1367c478bdstevel@tonic-gate
1377c478bdstevel@tonic-gate/*
1387c478bdstevel@tonic-gate * All error types
1397c478bdstevel@tonic-gate */
1407c478bdstevel@tonic-gate#define	S_AFSR_ALL_ERRS	(P_AFSR_STICKY & ~P_AFSR_PRIV)
1417c478bdstevel@tonic-gate
1427c478bdstevel@tonic-gate/*
1437c478bdstevel@tonic-gate * Shifts for Spitfire Asynchronous Fault Status Register
1447c478bdstevel@tonic-gate */
1457c478bdstevel@tonic-gate#define	P_AFSR_D_SIZE_SHIFT	(57)
1467c478bdstevel@tonic-gate#define	P_AFSR_CP_SHIFT		(24)
1477c478bdstevel@tonic-gate#define	P_AFSR_ETS_SHIFT	(16)
1487c478bdstevel@tonic-gate
1497c478bdstevel@tonic-gate/*
1507c478bdstevel@tonic-gate * AFSR error bits for AFT Level 1 messages (uncorrected + parity + BERR + TO)
1517c478bdstevel@tonic-gate */
1527c478bdstevel@tonic-gate#define	P_AFSR_LEVEL1   (P_AFSR_UE | P_AFSR_EDP | P_AFSR_WP | P_AFSR_CP |\
1537c478bdstevel@tonic-gate			P_AFSR_LDP | P_AFSR_BERR | P_AFSR_TO)
1547c478bdstevel@tonic-gate
1557c478bdstevel@tonic-gate/*
1567c478bdstevel@tonic-gate * Bits of Spitfire Asynchronous Fault Status Register
1577c478bdstevel@tonic-gate */
1587c478bdstevel@tonic-gate#define	S_AFSR_MASK	0x00000001FFFFFFFFULL /* <33:0>: valid AFSR bits */
1597c478bdstevel@tonic-gate
1607c478bdstevel@tonic-gate/*
1617c478bdstevel@tonic-gate * Bits of Spitfire Asynchronous Fault Address Register
1627c478bdstevel@tonic-gate * The Sabre AFAR includes more bits since it only has a UDBH, no UDBL
1637c478bdstevel@tonic-gate */
1647c478bdstevel@tonic-gate#define	S_AFAR_PA	0x000001FFFFFFFFF0ULL /* PA<40:4>: physical address */
1657c478bdstevel@tonic-gate#define	SABRE_AFAR_PA	0x000001FFFFFFFFF8ULL /* PA<40:3>: physical address */
1667c478bdstevel@tonic-gate
1677c478bdstevel@tonic-gate/*
1687c478bdstevel@tonic-gate * Bits of Spitfire/Sabre/Hummingbird Error Enable Registers
1697c478bdstevel@tonic-gate */
1707c478bdstevel@tonic-gate#define	EER_EPEN	0x00000000000000010ULL /* enable ETP, EDP, WP, CP */
1717c478bdstevel@tonic-gate#define	EER_UEEN	0x00000000000000008ULL /* enable UE */
1727c478bdstevel@tonic-gate#define	EER_ISAPEN	0x00000000000000004ULL /* enable ISAP */
1737c478bdstevel@tonic-gate#define	EER_NCEEN	0x00000000000000002ULL /* enable the other errors */
1747c478bdstevel@tonic-gate#define	EER_CEEN	0x00000000000000001ULL /* enable CE */
1757c478bdstevel@tonic-gate#define	EER_DISABLE	0x00000000000000000ULL /* no errors enabled */
1767c478bdstevel@tonic-gate#define	EER_ECC_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN)
1777c478bdstevel@tonic-gate#define	EER_CE_DISABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN)
1787c478bdstevel@tonic-gate#define	EER_ENABLE	(EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN|EER_CEEN)
1797c478bdstevel@tonic-gate
1807c478bdstevel@tonic-gate/*
1817c478bdstevel@tonic-gate * Bits and vaddrs of Spitfire Datapath Error Registers
1827c478bdstevel@tonic-gate */
1837c478bdstevel@tonic-gate#define	P_DER_UE	0x00000000000000200ULL	/* UE has occurred */
1847c478bdstevel@tonic-gate#define	P_DER_CE	0x00000000000000100ULL	/* CE has occurred */
1857c478bdstevel@tonic-gate#define	P_DER_E_SYND	0x000000000000000FFULL	/* SYND<7:0>: ECC syndrome */
1867c478bdstevel@tonic-gate#define	P_DER_H		0x0			/* datapath error reg upper */
1877c478bdstevel@tonic-gate#define	P_DER_L		0x18			/* datapath error reg upper */
1887c478bdstevel@tonic-gate
1897c478bdstevel@tonic-gate/*
1907c478bdstevel@tonic-gate * Bits of Spitfire Datapath Control Register
1917c478bdstevel@tonic-gate */
1927c478bdstevel@tonic-gate#define	P_DCR_VER	0x000001E00		/* datapath version */
1937c478bdstevel@tonic-gate#define	P_DCR_F_MODE	0x000000100		/* send FCB<7:0> */
1947c478bdstevel@tonic-gate#define	P_DCR_FCB	0x0000000FF		/* ECC check bits to force */
1957c478bdstevel@tonic-gate#define	P_DCR_H		0x20			/* datapath control reg upper */
1967c478bdstevel@tonic-gate#define	P_DCR_L		0x38			/* datapath control reg lower */
1977c478bdstevel@tonic-gate
1987c478bdstevel@tonic-gate/*
1997c478bdstevel@tonic-gate * Bits and shifts for the Spitfire (S), Sabre (SB) and Hummingbird (HB)
2007c478bdstevel@tonic-gate * Ecache tag data
2017c478bdstevel@tonic-gate */
2027c478bdstevel@tonic-gate#define	S_ECTAG_MASK	0x000000000003FFFFFULL	/* spitfire ecache tag mask */
2037c478bdstevel@tonic-gate#define	SB_ECTAG_MASK	0x00000000000000FFFULL	/* sabre ecache tag mask */
2047c478bdstevel@tonic-gate#define	HB_ECTAG_MASK	0x0000000000000FFFFULL	/* hbird ecache tag mask */
2057c478bdstevel@tonic-gate#define	S_ECSTATE_MASK	0x00000000001C00000ULL	/* spitfire tag state mask */
2067c478bdstevel@tonic-gate#define	SB_ECSTATE_MASK 0x0000000000000C000ULL	/* sabre tag state mask */
2077c478bdstevel@tonic-gate#define	HB_ECSTATE_MASK 0x00000000000030000ULL	/* hbird tag state mask */
2087c478bdstevel@tonic-gate#define	S_ECPAR_MASK	0x0000000001E000000ULL	/* spitfire tag parity mask */
2097c478bdstevel@tonic-gate#define	SB_ECPAR_MASK	0x00000000000030000ULL	/* sabre tag parity mask */
2107c478bdstevel@tonic-gate#define	HB_ECPAR_MASK	0x00000000000300000ULL	/* hbird tag parity mask */
2117c478bdstevel@tonic-gate#define	S_ECTAG_SHIFT		19		/* spitfire ecache tag shift */
2127c478bdstevel@tonic-gate#define	SB_ECTAG_SHIFT		18		/* sabre ecache tag shift */
2137c478bdstevel@tonic-gate#define	HB_ECTAG_SHIFT		16		/* hbird ecache tag shift */
2147c478bdstevel@tonic-gate#define	S_ECSTATE_SHIFT		22		/* spitfire tag state shift */
2157c478bdstevel@tonic-gate#define	SB_ECSTATE_SHIFT	14		/* sabre tag state shift */
2167c478bdstevel@tonic-gate#define	HB_ECSTATE_SHIFT	16		/* hbird tag state shift */
2177c478bdstevel@tonic-gate#define	S_ECPAR_SHIFT		25		/* spitfire tag parity shift */
2187c478bdstevel@tonic-gate#define	SB_ECPAR_SHIFT		16		/* sabre tag parity shift */
2197c478bdstevel@tonic-gate#define	HB_ECPAR_SHIFT		20		/* hbird tag parity shift */
2207c478bdstevel@tonic-gate#define	S_ECACHE_MAX_LSIZE	64		/* E$ line size */
2217c478bdstevel@tonic-gate
2227c478bdstevel@tonic-gate/*
2237c478bdstevel@tonic-gate * Constants representing the complete Spitfire (S), Sabre (SB) and Hummingbird
2247c478bdstevel@tonic-gate * (HB) tag state:
2257c478bdstevel@tonic-gate */
2267c478bdstevel@tonic-gate#define	S_ECSTATE_SHR		0x1		/* shared */
2277c478bdstevel@tonic-gate#define	S_ECSTATE_EXL		0x3		/* exclusive */
2287c478bdstevel@tonic-gate#define	S_ECSTATE_OWN		0x5		/* owner */
2297c478bdstevel@tonic-gate#define	S_ECSTATE_MOD		0x7		/* modified */
2307c478bdstevel@tonic-gate#define	SB_ECSTATE_EXL		0x2		/* exclusive */
2317c478bdstevel@tonic-gate#define	SB_ECSTATE_MOD		0x3		/* modified */
2327c478bdstevel@tonic-gate#define	HB_ECSTATE_EXL		0x2		/* exclusive */
2337c478bdstevel@tonic-gate#define	HB_ECSTATE_MOD		0x3		/* modified */
2347c478bdstevel@tonic-gate
2357c478bdstevel@tonic-gate/*
2367c478bdstevel@tonic-gate * Constants representing the individual Spitfire (S), Sabre (SB) and
2377c478bdstevel@tonic-gate * Hummingbird (HB) state bits:
2387c478bdstevel@tonic-gate */
2397c478bdstevel@tonic-gate#define	S_ECSTATE_VALID		0x1		/* line is valid */
2407c478bdstevel@tonic-gate#define	S_ECSTATE_DIRTY		0x4		/* line is dirty */
2417c478bdstevel@tonic-gate#define	SB_ECSTATE_VALID	0x2		/* line is valid */
2427c478bdstevel@tonic-gate#define	SB_ECSTATE_DIRTY	0x1		/* line is dirty */
2437c478bdstevel@tonic-gate#define	HB_ECSTATE_VALID	0x2		/* line is valid */
2447c478bdstevel@tonic-gate#define	HB_ECSTATE_DIRTY	0x1		/* line is dirty */
2457c478bdstevel@tonic-gate
2467c478bdstevel@tonic-gate/*
2477c478bdstevel@tonic-gate * Constants representing the individual Spitfire (S), Sabre (SB) and
2487c478bdstevel@tonic-gate * Hummingbird (HB) state parity and address parity bits:
2497c478bdstevel@tonic-gate */
2507c478bdstevel@tonic-gate#define	S_ECSTATE_PARITY	0x8		/* tag state parity bit */
2517c478bdstevel@tonic-gate#define	S_EC_PARITY		0xF		/* all parity bits */
2527c478bdstevel@tonic-gate#define	SB_ECSTATE_PARITY	0x2		/* tag state parity bit */
2537c478bdstevel@tonic-gate#define	SB_EC_PARITY		0x3		/* all parity bits */
2547c478bdstevel@tonic-gate#define	HB_ECSTATE_PARITY	0x2		/* tag state parity bit */
2557c478bdstevel@tonic-gate#define	HB_EC_PARITY		0x3		/* all parity bits */
2567c478bdstevel@tonic-gate
2577c478bdstevel@tonic-gate#ifdef HUMMINGBIRD
2587c478bdstevel@tonic-gate
2597c478bdstevel@tonic-gate#define	HB_ESTAR_MODE		INT64_C(0x1FE0000F080)	/* estar mode reg */
2607c478bdstevel@tonic-gate#define	HB_MEM_CNTRL0		INT64_C(0x1FE0000F010)	/* mem control0 reg */
2617c478bdstevel@tonic-gate#define	HB_REFRESH_COUNT_MASK	0x7F00			/* mc0<14:8>: ref cnt */
2627c478bdstevel@tonic-gate#define	HB_REFRESH_COUNT_SHIFT	8			/* bits to shift */
2637c478bdstevel@tonic-gate#define	HB_REFRESH_INTERVAL	INT64_C(7800)		/* 7800 nsecs memory */
2647c478bdstevel@tonic-gate							/* refresh interval */
2657c478bdstevel@tonic-gate							/* works for all DIMM */
2667c478bdstevel@tonic-gate							/* same value as OBP */
2677c478bdstevel@tonic-gate#define	HB_REFRESH_CLOCKS_PER_COUNT	INT64_C(64)	/* cpu clks per count */
2687c478bdstevel@tonic-gate#define	HB_SELF_REFRESH_MASK	0x10000			/* mc0<16>: self ref */
2697c478bdstevel@tonic-gate#define	HB_SELF_REFRESH_SHIFT	16			/* bits to shift */
2707c478bdstevel@tonic-gate#define	HB_SELF_REFRESH_DISABLE	0			/* disable self ref */
2717c478bdstevel@tonic-gate#define	HB_SELF_REFRESH_ENABLE	1			/* enable self ref */
2727c478bdstevel@tonic-gate
2737c478bdstevel@tonic-gate#define	HB_ECLK_1	INT64_C(0x0000000000000000) 	/* 1/1 clock */
2747c478bdstevel@tonic-gate#define	HB_ECLK_2	INT64_C(0x0000000000000001) 	/* 1/2 clock */
2757c478bdstevel@tonic-gate#define	HB_ECLK_4	INT64_C(0x0000000000000003) 	/* 1/4 clock */
2767c478bdstevel@tonic-gate#define	HB_ECLK_6	INT64_C(0x0000000000000002) 	/* 1/6 clock */
2777c478bdstevel@tonic-gate#define	HB_ECLK_8	INT64_C(0x0000000000000004) 	/* 1/8 clock */
2787c478bdstevel@tonic-gate#define	HB_ECLK_MASK	(HB_ECLK_1|HB_ECLK_2|HB_ECLK_4|HB_ECLK_6|HB_ECLK_8)
2797c478bdstevel@tonic-gate
2807c478bdstevel@tonic-gate
2817c478bdstevel@tonic-gate/*
2827c478bdstevel@tonic-gate * UPA Configuration Register
2837c478bdstevel@tonic-gate *
2847c478bdstevel@tonic-gate * +--------------+----+------+------+----------+------+-------------+
2857c478bdstevel@tonic-gate * |     Resv     | RR |  DM  | ELIM |   PCON   | MID  |     PCAP    |
2867c478bdstevel@tonic-gate * +--------------+----+------+------+----------+------+-------------+
2877c478bdstevel@tonic-gate *  63          39  38  37..36 35..33 32......22 21..17 16..........0
2887c478bdstevel@tonic-gate *
2897c478bdstevel@tonic-gate */
2907c478bdstevel@tonic-gate
2917c478bdstevel@tonic-gate#define	HB_UPA_DMAP_DATA_BIT	36	/* loads and stores direct mapped */
2927c478bdstevel@tonic-gate#define	HB_UPA_DMAP_INSTR_BIT	37	/* instruction misses direct mapped */
2937c478bdstevel@tonic-gate#define	HB_UPA_RR_BIT		38	/* reset rand generator */
2947c478bdstevel@tonic-gate
2957c478bdstevel@tonic-gate#endif /* HUMMINGBIRD */
2967c478bdstevel@tonic-gate
2977c478bdstevel@tonic-gate/*
2987c478bdstevel@tonic-gate * The minimum size needed to ensure consistency on a virtually address
2997c478bdstevel@tonic-gate * cache.  Computed by taking the largest virtually indexed cache and dividing
3007c478bdstevel@tonic-gate * by its associativity.
3017c478bdstevel@tonic-gate */
3027c478bdstevel@tonic-gate#define	S_VAC_SIZE	0x4000
3037c478bdstevel@tonic-gate
3047c478bdstevel@tonic-gate#ifdef _KERNEL
3057c478bdstevel@tonic-gate
3067c478bdstevel@tonic-gate#ifndef _ASM
3077c478bdstevel@tonic-gate#include <sys/kstat.h>
3087c478bdstevel@tonic-gate
3097c478bdstevel@tonic-gatevoid	get_udb_errors(uint64_t *udbh, uint64_t *udbl);
3107c478bdstevel@tonic-gate
3117c478bdstevel@tonic-gate/*
3127c478bdstevel@tonic-gate * The scrub_misc structure contains miscellaneous bookeepping items for
3137c478bdstevel@tonic-gate * scrubbing the E$.
3147c478bdstevel@tonic-gate *
3157c478bdstevel@tonic-gate * Counter of outstanding E$ scrub requests. The counter for a given CPU id
3167c478bdstevel@tonic-gate * is atomically incremented and decremented _only_  on that CPU,
3177c478bdstevel@tonic-gate * to avoid cacheline ownership bouncing.
3187c478bdstevel@tonic-gate */
3197c478bdstevel@tonic-gate
3207c478bdstevel@tonic-gatetypedef struct spitfire_scrub_misc {
3217c478bdstevel@tonic-gate	uint32_t	ec_scrub_outstanding;	/* outstanding reqs */
3227c478bdstevel@tonic-gate	int		ecache_flush_index;	/* offset into E$ for flush */
3237c478bdstevel@tonic-gate	int		ecache_busy;		/* keeps track if cpu busy */
3247c478bdstevel@tonic-gate	int		ecache_nlines;		/* no. of E$ lines */
3257c478bdstevel@tonic-gate	int		ecache_mirror;		/* E$ is mirrored */
3267c478bdstevel@tonic-gate	kstat_t		*ecache_ksp;		/* ptr to the kstat */
3277c478bdstevel@tonic-gate} spitfire_scrub_misc_t;
3287c478bdstevel@tonic-gate
3297c478bdstevel@tonic-gate/*
3307c478bdstevel@tonic-gate * Spitfire module private data structure. One of these is allocated for each
3317c478bdstevel@tonic-gate * valid cpu at setup time and is pointed to by the machcpu "cpu_private"
3327c478bdstevel@tonic-gate * pointer.
3337c478bdstevel@tonic-gate */
3347c478bdstevel@tonic-gatetypedef struct spitfire_private {
3357c478bdstevel@tonic-gate	spitfire_scrub_misc_t	sfpr_scrub_misc;
3367c478bdstevel@tonic-gate	uint64_t		sfpr_scrub_afsr;
3377c478bdstevel@tonic-gate} spitfire_private_t;
3387c478bdstevel@tonic-gate
3397c478bdstevel@tonic-gate#endif /* !_ASM */
3407c478bdstevel@tonic-gate
3417c478bdstevel@tonic-gate#endif /* _KERNEL */
3427c478bdstevel@tonic-gate
3437c478bdstevel@tonic-gate#ifdef	__cplusplus
3447c478bdstevel@tonic-gate}
3457c478bdstevel@tonic-gate#endif
3467c478bdstevel@tonic-gate
3477c478bdstevel@tonic-gate#endif	/* _SYS_SPITREGS_H */
348