xref: /illumos-gate/usr/src/uts/sun4u/sys/sbbcreg.h (revision b8dc8477)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*b8dc8477Sarutz  * Common Development and Distribution License (the "License").
6*b8dc8477Sarutz  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22*b8dc8477Sarutz  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23*b8dc8477Sarutz  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef	_SYS_SBBCREG_H
277c478bd9Sstevel@tonic-gate #define	_SYS_SBBCREG_H
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
307c478bd9Sstevel@tonic-gate 
317c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
327c478bd9Sstevel@tonic-gate extern "C" {
337c478bd9Sstevel@tonic-gate #endif
347c478bd9Sstevel@tonic-gate 
357c478bd9Sstevel@tonic-gate /*
367c478bd9Sstevel@tonic-gate  * Register definitions for SBBC, a PCI device.
377c478bd9Sstevel@tonic-gate  */
387c478bd9Sstevel@tonic-gate #define	SBBC_SC_MODE	0x00000020
397c478bd9Sstevel@tonic-gate 
407c478bd9Sstevel@tonic-gate typedef struct pad12 {
417c478bd9Sstevel@tonic-gate 	uint32_t pad[3];
427c478bd9Sstevel@tonic-gate }pad12_t;
437c478bd9Sstevel@tonic-gate 
447c478bd9Sstevel@tonic-gate /*
457c478bd9Sstevel@tonic-gate  * SBBC registers.
467c478bd9Sstevel@tonic-gate  */
477c478bd9Sstevel@tonic-gate struct sbbc_regs_map {
487c478bd9Sstevel@tonic-gate 	uint32_t devid;			/* 0x0.0000 All, device ID */
497c478bd9Sstevel@tonic-gate 	pad12_t  pada;
507c478bd9Sstevel@tonic-gate 	uint32_t devtemp;		/* 0x0.0010 All */
517c478bd9Sstevel@tonic-gate 	pad12_t  padb;
527c478bd9Sstevel@tonic-gate 	uint32_t incon_scratch;		/* 0x0.0020 All */
537c478bd9Sstevel@tonic-gate 	pad12_t  padc;
547c478bd9Sstevel@tonic-gate 	uint32_t incon_tstl1;		/* 0x0.0030 AR and SDC */
557c478bd9Sstevel@tonic-gate 	pad12_t  padd;
567c478bd9Sstevel@tonic-gate 	uint32_t incon_tsterr;		/* 0x0.0040 AR and SDC */
577c478bd9Sstevel@tonic-gate 	pad12_t  pade;
587c478bd9Sstevel@tonic-gate 	uint32_t device_conf;		/* 0x0.0050 All, device configuration */
597c478bd9Sstevel@tonic-gate 	pad12_t  padf;
607c478bd9Sstevel@tonic-gate 	uint32_t device_rstcntl;	/* 0x0.0060 SBBC,AR,dev reset control */
617c478bd9Sstevel@tonic-gate 	pad12_t  padg;
627c478bd9Sstevel@tonic-gate 	uint32_t device_rststat;	/* 0x0.0070 All, device reset status */
637c478bd9Sstevel@tonic-gate 	pad12_t  padh;
647c478bd9Sstevel@tonic-gate 	uint32_t device_errstat;	/* 0x0.0080 SBBC, device reset */
657c478bd9Sstevel@tonic-gate 	pad12_t  padi;
667c478bd9Sstevel@tonic-gate 	uint32_t device_errcntl;	/* 0x0.0090 SBBC,device error control */
677c478bd9Sstevel@tonic-gate 	pad12_t  padj;
687c478bd9Sstevel@tonic-gate 	uint32_t jtag_cntl;		/* 0x0.00a0 SBBC and SDC,JTAG control */
697c478bd9Sstevel@tonic-gate 	pad12_t  padk;
707c478bd9Sstevel@tonic-gate 	uint32_t jtag_cmd;		/* 0x0.00b0 SBBC and SDC,JTAG command */
717c478bd9Sstevel@tonic-gate 	pad12_t  padl;
727c478bd9Sstevel@tonic-gate 	uint32_t i2c_addrcmd;		/* 0x0.00c0 SBBC,I2C addr and command */
737c478bd9Sstevel@tonic-gate 	pad12_t  padm;
747c478bd9Sstevel@tonic-gate 	uint32_t i2c_data;		/* 0x0.00d0 SBBC, I2C data */
757c478bd9Sstevel@tonic-gate 	pad12_t  padn;
767c478bd9Sstevel@tonic-gate 	uint32_t pci_errstat;		/* 0x0.00e0 SBBC, PCI error status */
777c478bd9Sstevel@tonic-gate 	pad12_t  pad2[45];
787c478bd9Sstevel@tonic-gate 	uint32_t consbus_conf;		/* 0x0.0300 All */
797c478bd9Sstevel@tonic-gate 	pad12_t  pado;
807c478bd9Sstevel@tonic-gate 	uint32_t consbus_erraddr;	/* 0x0.0310 SBBC */
817c478bd9Sstevel@tonic-gate 	pad12_t  padp;
827c478bd9Sstevel@tonic-gate 	uint32_t consbus_errack;	/* 0x0.0320 SBBC */
837c478bd9Sstevel@tonic-gate 	pad12_t  pad4[18];
847c478bd9Sstevel@tonic-gate 	uint32_t pad5;
857c478bd9Sstevel@tonic-gate 	uint32_t consbus_port0_err;	/* 0x0.0400 All */
867c478bd9Sstevel@tonic-gate 	pad12_t  pad6[19];
877c478bd9Sstevel@tonic-gate 	uint32_t pad7[2];
887c478bd9Sstevel@tonic-gate 	uint32_t consbus_part_dom_err;	/* 0x0.04f0 SBBC and CBH */
897c478bd9Sstevel@tonic-gate 	pad12_t  pad8[235];
907c478bd9Sstevel@tonic-gate 	uint32_t pad8a[2];
917c478bd9Sstevel@tonic-gate 	uint32_t sbbc_synch;		/* 0x0.1000 SBBC */
927c478bd9Sstevel@tonic-gate 	pad12_t  padq[20];
937c478bd9Sstevel@tonic-gate 	uint32_t padqa[3];
947c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim0;	/* 0x0.1100 SBBC */
957c478bd9Sstevel@tonic-gate 	pad12_t  padr;
967c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim1;	/* 0x0.1110 SBBC */
977c478bd9Sstevel@tonic-gate 	pad12_t  pads;
987c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim2;	/* 0x0.1120 SBBC */
997c478bd9Sstevel@tonic-gate 	pad12_t  padt;
1007c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim3;	/* 0x0.1130 SBBC */
1017c478bd9Sstevel@tonic-gate 	pad12_t  padu;
1027c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim4;	/* 0x0.1140 SBBC */
1037c478bd9Sstevel@tonic-gate 	pad12_t  padv;
1047c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim5;	/* 0x0.1150 SBBC */
1057c478bd9Sstevel@tonic-gate 	pad12_t  pad9[14];
1067c478bd9Sstevel@tonic-gate 	uint32_t pad9a[1];
1077c478bd9Sstevel@tonic-gate 	uint32_t spare_in_out;		/* 0x0.1200 SBBC */
1087c478bd9Sstevel@tonic-gate 	pad12_t  pad10[127];
1097c478bd9Sstevel@tonic-gate 	uint32_t pad10a[2];
1107c478bd9Sstevel@tonic-gate 	uint32_t monitor_cntl;		/* 0x0.1800 SBBC */
1117c478bd9Sstevel@tonic-gate 	pad12_t  pad11[170];
1127c478bd9Sstevel@tonic-gate 	uint32_t pad11a[1];
1137c478bd9Sstevel@tonic-gate 	uint32_t port_intr_gen0;	/* 0x0.2000 SBBC */
1147c478bd9Sstevel@tonic-gate 	pad12_t  padw;
1157c478bd9Sstevel@tonic-gate 	uint32_t port_intr_gen1;	/* 0x0.2010 SBBC */
1167c478bd9Sstevel@tonic-gate 	pad12_t  padx;
1177c478bd9Sstevel@tonic-gate 	uint32_t syscntlr_intr_gen;	/* 0x0.2020 SBBC */
1187c478bd9Sstevel@tonic-gate 	pad12_t  pad12[61];
1197c478bd9Sstevel@tonic-gate 	uint32_t sys_intr_status;	/* 0x0.2300 SBBC */
1207c478bd9Sstevel@tonic-gate 	pad12_t  pady;
1217c478bd9Sstevel@tonic-gate 	uint32_t sys_intr_enable;	/* 0x0.2310 SBBC */
1227c478bd9Sstevel@tonic-gate 	pad12_t  padz;
1237c478bd9Sstevel@tonic-gate 	uint32_t pci_intr_status;	/* 0x0.2320 SBBC */
1247c478bd9Sstevel@tonic-gate 	pad12_t  padaa;
1257c478bd9Sstevel@tonic-gate 	uint32_t pci_intr_enable;	/* 0x0.2330 SBBC */
1267c478bd9Sstevel@tonic-gate 	pad12_t  pad13[614];
1277c478bd9Sstevel@tonic-gate 	uint32_t pad13a[1];
1287c478bd9Sstevel@tonic-gate 	uint32_t pci_to_consbus_map;	/* 0x0.4000 SBBC */
1297c478bd9Sstevel@tonic-gate 	pad12_t  padab;
1307c478bd9Sstevel@tonic-gate 	uint32_t consbus_to_pci_map;	/* 0x0.4010 SBBC */
131*b8dc8477Sarutz 	uint32_t pad14[2247];
132*b8dc8477Sarutz 					/* 0x0.6330 SBBC */
1337c478bd9Sstevel@tonic-gate };
1347c478bd9Sstevel@tonic-gate 
1357c478bd9Sstevel@tonic-gate 
1367c478bd9Sstevel@tonic-gate /*
1377c478bd9Sstevel@tonic-gate  * SSC DEV presence registers
1387c478bd9Sstevel@tonic-gate  */
1397c478bd9Sstevel@tonic-gate struct ssc_devpresence_regs_map {
1407c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg0;
1417c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg1;
1427c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg2;
1437c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg3;
1447c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg4;
1457c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg5;
1467c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg6;
1477c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg7;
1487c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg8;
1497c478bd9Sstevel@tonic-gate 	uint8_t devpres_reg9;
1507c478bd9Sstevel@tonic-gate 	uint8_t devpres_rega;
1517c478bd9Sstevel@tonic-gate 	uint8_t devpres_regb;
1527c478bd9Sstevel@tonic-gate };
1537c478bd9Sstevel@tonic-gate 
1547c478bd9Sstevel@tonic-gate /*
1557c478bd9Sstevel@tonic-gate  * EChip
1567c478bd9Sstevel@tonic-gate  * 0088.0000 - 0089.FFFF
1577c478bd9Sstevel@tonic-gate  */
1587c478bd9Sstevel@tonic-gate struct ssc_echip_regs {
1597c478bd9Sstevel@tonic-gate 	uint8_t offset[0x20000];
1607c478bd9Sstevel@tonic-gate };
1617c478bd9Sstevel@tonic-gate 
1627c478bd9Sstevel@tonic-gate /*
1637c478bd9Sstevel@tonic-gate  * Device Presence
1647c478bd9Sstevel@tonic-gate  * 008A.0000 - 008B.FFFF
1657c478bd9Sstevel@tonic-gate  */
1667c478bd9Sstevel@tonic-gate struct ssc_devpresence_regs {
1677c478bd9Sstevel@tonic-gate 	uint8_t offset[0x20000];
1687c478bd9Sstevel@tonic-gate };
1697c478bd9Sstevel@tonic-gate 
1707c478bd9Sstevel@tonic-gate /*
1717c478bd9Sstevel@tonic-gate  * I2C Mux
1727c478bd9Sstevel@tonic-gate  * 008C.0000 - 008D.FFFF
1737c478bd9Sstevel@tonic-gate  */
1747c478bd9Sstevel@tonic-gate struct ssc_i2cmux_regs {
1757c478bd9Sstevel@tonic-gate 	uint8_t offset[0x20000];
1767c478bd9Sstevel@tonic-gate };
1777c478bd9Sstevel@tonic-gate 
1787c478bd9Sstevel@tonic-gate /*
1797c478bd9Sstevel@tonic-gate  * Error Interrupts Status and Control
1807c478bd9Sstevel@tonic-gate  * 008E.0000 - 008F.FFFF
1817c478bd9Sstevel@tonic-gate  */
1827c478bd9Sstevel@tonic-gate struct ssc_errintr_statcntl_regs {
1837c478bd9Sstevel@tonic-gate 	uint8_t offset[0x20000];
1847c478bd9Sstevel@tonic-gate };
1857c478bd9Sstevel@tonic-gate 
1867c478bd9Sstevel@tonic-gate /*
1877c478bd9Sstevel@tonic-gate  * Console Bus Window
1887c478bd9Sstevel@tonic-gate  * 0400.0000 - 07FF.FFFF
1897c478bd9Sstevel@tonic-gate  */
1907c478bd9Sstevel@tonic-gate struct ssc_console_bus {
1917c478bd9Sstevel@tonic-gate 	uint8_t offset[0x4000000];
1927c478bd9Sstevel@tonic-gate };
1937c478bd9Sstevel@tonic-gate 
1947c478bd9Sstevel@tonic-gate /*
1957c478bd9Sstevel@tonic-gate  * SSC EILD registers
1967c478bd9Sstevel@tonic-gate  */
1977c478bd9Sstevel@tonic-gate struct ssc_eild_reg_map {
1987c478bd9Sstevel@tonic-gate 	uint8_t darb_intr;
1997c478bd9Sstevel@tonic-gate 	uint8_t darb_intr_mask;
2007c478bd9Sstevel@tonic-gate 	uint8_t sbbc_cons_err;
2017c478bd9Sstevel@tonic-gate 	uint8_t sbbc_cons_err_mask;
2027c478bd9Sstevel@tonic-gate 	uint8_t pwr_supply;
2037c478bd9Sstevel@tonic-gate };
2047c478bd9Sstevel@tonic-gate 
2057c478bd9Sstevel@tonic-gate /*
2067c478bd9Sstevel@tonic-gate  * PCI SBBC slave mapping
2077c478bd9Sstevel@tonic-gate  */
2087c478bd9Sstevel@tonic-gate struct pci_sbbc {
2097c478bd9Sstevel@tonic-gate 	uint8_t fprom[0x800000];	/* FPROM */
2107c478bd9Sstevel@tonic-gate 	struct sbbc_regs_map sbbc_internal_regs;	/* sbbc registers */
211*b8dc8477Sarutz 	uint8_t dontcare[0x79CD0];	/* reserved sbbc registers */
2127c478bd9Sstevel@tonic-gate 	struct ssc_echip_regs echip_regs;
2137c478bd9Sstevel@tonic-gate 	struct ssc_devpresence_regs devpres_regs;
2147c478bd9Sstevel@tonic-gate 	struct ssc_i2cmux_regs i2cmux_regs;
2157c478bd9Sstevel@tonic-gate 	struct ssc_errintr_statcntl_regs errintr_scntl_regs;
2167c478bd9Sstevel@tonic-gate 	uint8_t sram[0x100000];
2177c478bd9Sstevel@tonic-gate 	uint8_t reserved[0x3600000];
2187c478bd9Sstevel@tonic-gate 	struct ssc_console_bus consbus;
2197c478bd9Sstevel@tonic-gate };
2207c478bd9Sstevel@tonic-gate 
2217c478bd9Sstevel@tonic-gate 
2227c478bd9Sstevel@tonic-gate /*
2237c478bd9Sstevel@tonic-gate  * SBBC registers.
2247c478bd9Sstevel@tonic-gate  */
2257c478bd9Sstevel@tonic-gate struct sbbc_common_devregs {
2267c478bd9Sstevel@tonic-gate 	uint32_t devid;			/* All, device ID */
2277c478bd9Sstevel@tonic-gate 	uint32_t devtemp;		/* All */
2287c478bd9Sstevel@tonic-gate 	uint32_t incon_scratch;		/* All */
2297c478bd9Sstevel@tonic-gate 	uint32_t incon_tstl1;		/* AR and SDC */
2307c478bd9Sstevel@tonic-gate 	uint32_t incon_tsterr;		/* AR and SDC */
2317c478bd9Sstevel@tonic-gate 	uint32_t device_conf;		/* All, device configuration */
2327c478bd9Sstevel@tonic-gate 	uint32_t device_rstcntl;	/* SBBC and AR, dev reset control */
2337c478bd9Sstevel@tonic-gate 	uint32_t device_rststat;	/* All, device reset status */
2347c478bd9Sstevel@tonic-gate 	uint32_t device_errstat;	/* SBBC, device reset */
2357c478bd9Sstevel@tonic-gate 	uint32_t device_errcntl;	/* SBBC, device error control */
2367c478bd9Sstevel@tonic-gate 	uint32_t jtag_cntl;		/* SBBC and SDC, JTAG control */
2377c478bd9Sstevel@tonic-gate 	uint32_t jtag_cmd;		/* SBBC and SDC, JTAG command */
2387c478bd9Sstevel@tonic-gate 	uint32_t i2c_addrcmd;		/* SBBC, I2C address and command */
2397c478bd9Sstevel@tonic-gate 	uint32_t i2c_data;		/* SBBC, I2C data */
2407c478bd9Sstevel@tonic-gate 	uint32_t pci_errstat;		/* SBBC, PCI error status */
2417c478bd9Sstevel@tonic-gate 	uint32_t domain_conf;		/* CBH */
2427c478bd9Sstevel@tonic-gate 	uint32_t safari_port0_conf;	/* AR and SDC */
2437c478bd9Sstevel@tonic-gate 	uint32_t safari_port1_conf;	/* AR and SDC */
2447c478bd9Sstevel@tonic-gate 	uint32_t safari_port2_conf;	/* AR and SDC */
2457c478bd9Sstevel@tonic-gate 	uint32_t safari_port3_conf;	/* AR and SDC */
2467c478bd9Sstevel@tonic-gate 	uint32_t safari_port4_conf;	/* AR and SDC */
2477c478bd9Sstevel@tonic-gate 	uint32_t safari_port5_conf;	/* AR and SDC */
2487c478bd9Sstevel@tonic-gate 	uint32_t safari_port6_conf;	/* AR and SDC */
2497c478bd9Sstevel@tonic-gate 	uint32_t safari_port7_conf;	/* AR and SDC */
2507c478bd9Sstevel@tonic-gate 	uint32_t safari_port8_conf;	/* AR and SDC */
2517c478bd9Sstevel@tonic-gate 	uint32_t safari_port9_conf;	/* AR and SDC */
2527c478bd9Sstevel@tonic-gate 	uint32_t safari_port0_err;	/* AR and SDC */
2537c478bd9Sstevel@tonic-gate 	uint32_t safari_port1_err;	/* AR and SDC */
2547c478bd9Sstevel@tonic-gate 	uint32_t safari_port2_err;	/* AR and SDC */
2557c478bd9Sstevel@tonic-gate 	uint32_t safari_port3_err;	/* AR and SDC */
2567c478bd9Sstevel@tonic-gate 	uint32_t safari_port4_err;	/* AR and SDC */
2577c478bd9Sstevel@tonic-gate 	uint32_t safari_port5_err;	/* AR and SDC */
2587c478bd9Sstevel@tonic-gate 	uint32_t safari_port6_err;	/* AR and SDC */
2597c478bd9Sstevel@tonic-gate 	uint32_t safari_port7_err;	/* AR and SDC */
2607c478bd9Sstevel@tonic-gate 	uint32_t safari_port8_err;	/* AR and SDC */
2617c478bd9Sstevel@tonic-gate 	uint32_t safari_port9_err;	/* AR and SDC */
2627c478bd9Sstevel@tonic-gate 	uint32_t consbus_conf;		/* All */
2637c478bd9Sstevel@tonic-gate 	uint32_t consbus_erraddr;	/* SBBC */
2647c478bd9Sstevel@tonic-gate 	uint32_t consbus_errack;	/* SBBC */
2657c478bd9Sstevel@tonic-gate 	uint32_t consbus_errinj0;	/* CBH */
2667c478bd9Sstevel@tonic-gate 	uint32_t consbus_errinj1;	/* CBH */
2677c478bd9Sstevel@tonic-gate 	uint32_t consbus_port0_err;	/* All */
2687c478bd9Sstevel@tonic-gate 	uint32_t consbus_port1_err;	/* SDC and CBH */
2697c478bd9Sstevel@tonic-gate 	uint32_t consbus_port2_err;	/* SDC and CBH */
2707c478bd9Sstevel@tonic-gate 	uint32_t consbus_port3_err;	/* SDC and CBH */
2717c478bd9Sstevel@tonic-gate 	uint32_t consbus_port4_err;	/* SDC and CBH */
2727c478bd9Sstevel@tonic-gate 	uint32_t consbus_port5_err;	/* CBH */
2737c478bd9Sstevel@tonic-gate 	uint32_t consbus_port6_err;	/* CBH */
2747c478bd9Sstevel@tonic-gate 	uint32_t consbus_port7_err;	/* CBH */
2757c478bd9Sstevel@tonic-gate 	uint32_t consbus_port8_err;	/* CBH */
2767c478bd9Sstevel@tonic-gate 	uint32_t consbus_port9_err;	/* CBH */
2777c478bd9Sstevel@tonic-gate 	uint32_t consbus_porta_err;	/* CBH */
2787c478bd9Sstevel@tonic-gate 	uint32_t consbus_portb_err;	/* CBH */
2797c478bd9Sstevel@tonic-gate 	uint32_t consbus_portc_err;	/* CBH */
2807c478bd9Sstevel@tonic-gate 	uint32_t consbus_portd_err;	/* CBH */
2817c478bd9Sstevel@tonic-gate 	uint32_t consbus_porte_err;	/* CBH */
2827c478bd9Sstevel@tonic-gate 	uint32_t consbus_part_dom_err;	/* SBBC and CBH */
2837c478bd9Sstevel@tonic-gate 	uint32_t sbbc_synch;		/* SBBC */
2847c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim0;	/* SBBC */
2857c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim1;	/* SBBC */
2867c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim2;	/* SBBC */
2877c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim3;	/* SBBC */
2887c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim4;	/* SBBC */
2897c478bd9Sstevel@tonic-gate 	uint32_t dev_access_tim5;	/* SBBC */
2907c478bd9Sstevel@tonic-gate 	uint32_t spare_in_out;		/* SBBC */
2917c478bd9Sstevel@tonic-gate 	uint32_t monitor_cntl;		/* SBBC */
2927c478bd9Sstevel@tonic-gate 	uint32_t port_intr_gen0;	/* SBBC */
2937c478bd9Sstevel@tonic-gate 	uint32_t port_intr_gen1;	/* SBBC */
2947c478bd9Sstevel@tonic-gate 	uint32_t syscntlr_intr_gen;	/* SBBC */
2957c478bd9Sstevel@tonic-gate 	uint32_t sys_intr_status;	/* SBBC */
2967c478bd9Sstevel@tonic-gate 	uint32_t sys_intr_enable;	/* SBBC */
2977c478bd9Sstevel@tonic-gate 	uint32_t pci_intr_status;	/* SBBC */
2987c478bd9Sstevel@tonic-gate 	uint32_t pci_intr_enable;	/* SBBC */
2997c478bd9Sstevel@tonic-gate 	uint32_t pci_to_consbus_map;	/* SBBC */
3007c478bd9Sstevel@tonic-gate 	uint32_t consbus_to_pci_map;	/* SBBC */
3017c478bd9Sstevel@tonic-gate 	uint32_t scm_consbus_addrmap;	/* CBH */
3027c478bd9Sstevel@tonic-gate 	uint32_t ar_slot0_trans_cnt;	/* AR */
3037c478bd9Sstevel@tonic-gate 	uint32_t ar_slot1_trans_cnt;	/* AR */
3047c478bd9Sstevel@tonic-gate 	uint32_t ar_slot2_trans_cnt;	/* AR */
3057c478bd9Sstevel@tonic-gate 	uint32_t ar_slot3_trans_cnt;	/* AR */
3067c478bd9Sstevel@tonic-gate 	uint32_t ar_slot4_trans_cnt;	/* AR */
3077c478bd9Sstevel@tonic-gate 	uint32_t ar_slot5_trans_cnt;	/* AR */
3087c478bd9Sstevel@tonic-gate 	uint32_t ar_slot6_trans_cnt;	/* AR */
3097c478bd9Sstevel@tonic-gate 	uint32_t ar_slot7_trans_cnt;	/* AR */
3107c478bd9Sstevel@tonic-gate 	uint32_t ar_slot8_trans_cnt;	/* AR */
3117c478bd9Sstevel@tonic-gate 	uint32_t ar_slot9_trans_cnt;	/* AR */
3127c478bd9Sstevel@tonic-gate 	uint32_t ar_trans_cnt_oflow;	/* AR */
3137c478bd9Sstevel@tonic-gate 	uint32_t ar_trans_cnt_uflow;	/* AR */
3147c478bd9Sstevel@tonic-gate 	uint32_t ar_l1l1_conf;		/* AR */
3157c478bd9Sstevel@tonic-gate 	uint32_t lock_step_err;		/* AR and SDC */
3167c478bd9Sstevel@tonic-gate 	uint32_t l2_check_err;		/* AR and SDC */
3177c478bd9Sstevel@tonic-gate 	uint32_t incon_tstl1_slave;	/* AR */
3187c478bd9Sstevel@tonic-gate 	uint32_t incon_tstl2_slave;	/* AR and SDC */
3197c478bd9Sstevel@tonic-gate 	uint32_t ecc_status;		/* SDC */
3207c478bd9Sstevel@tonic-gate 	uint32_t event_counter0;	/* SDC */
3217c478bd9Sstevel@tonic-gate 	uint32_t event_counter1;	/* SDC */
3227c478bd9Sstevel@tonic-gate 	uint32_t event_counter2;	/* SDC */
3237c478bd9Sstevel@tonic-gate 	uint32_t monitor_counter_cntl;	/* AR and SDC */
3247c478bd9Sstevel@tonic-gate 	uint32_t ar_transid_match;	/* AR */
3257c478bd9Sstevel@tonic-gate };
3267c478bd9Sstevel@tonic-gate 
3277c478bd9Sstevel@tonic-gate 
3287c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
3297c478bd9Sstevel@tonic-gate }
3307c478bd9Sstevel@tonic-gate #endif
3317c478bd9Sstevel@tonic-gate 
3327c478bd9Sstevel@tonic-gate #endif	/* _SYS_SBBCREG_H */
333