xref: /illumos-gate/usr/src/uts/sun4u/sys/pci/pci_ib.h (revision 2a1fd0ff)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright 2019 Peter Tribble.
27  */
28 
29 #ifndef	_SYS_PCI_IB_H
30 #define	_SYS_PCI_IB_H
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/ddi_subrdefs.h>
37 #include <sys/pci_tools.h>
38 
39 typedef uint8_t ib_ino_t;
40 typedef uint16_t ib_mondo_t;
41 typedef struct ib_ino_info ib_ino_info_t;
42 typedef struct ib_ino_pil ib_ino_pil_t;
43 typedef uint8_t device_num_t;
44 typedef uint8_t interrupt_t;
45 
46 /*
47  * interrupt block soft state structure:
48  *
49  * Each pci node may share an interrupt block structure with its peer
50  * node or have its own private interrupt block structure.
51  */
52 typedef struct ib ib_t;
53 struct ib {
54 
55 	pci_t *ib_pci_p;	/* link back to pci soft state */
56 	pci_ign_t ib_ign;	/* interrupt group # */
57 
58 	/*
59 	 * PCI slot and onboard I/O interrupt mapping register blocks addresses:
60 	 */
61 	uintptr_t ib_slot_intr_map_regs;
62 #define	ib_intr_map_regs	ib_slot_intr_map_regs
63 	uintptr_t ib_obio_intr_map_regs;
64 
65 	/*
66 	 * PCI slot and onboard I/O clear interrupt register block addresses:
67 	 */
68 	uintptr_t ib_slot_clear_intr_regs;
69 	uintptr_t ib_obio_clear_intr_regs;
70 
71 	/*
72 	 * UPA expansion slot interrupt mapping register addresses:
73 	 */
74 	volatile uint64_t *ib_upa_imr[2];
75 	uint64_t ib_upa_imr_state[2];
76 
77 	/*
78 	 * Interrupt retry register address:
79 	 */
80 	volatile uint64_t *ib_intr_retry_timer_reg;
81 
82 	/*
83 	 * PCI slot and onboard I/O interrupt state diag register addresses:
84 	 */
85 	volatile uint64_t *ib_slot_intr_state_diag_reg;
86 	volatile uint64_t *ib_obio_intr_state_diag_reg;
87 
88 	uint_t ib_max_ino;			/* largest supported INO */
89 	ib_ino_info_t *ib_ino_lst;		/* ino link list */
90 	kmutex_t ib_ino_lst_mutex;		/* mutex for ino link list */
91 	kmutex_t ib_intr_lock;			/* lock for internal intr  */
92 	uint16_t ib_map_reg_counters[8];	/* counters for shared map */
93 						/* registers */
94 };
95 
96 #define	PCI_PULSE_INO	0x80000000
97 #define	PSYCHO_MAX_INO	0x3f
98 #define	SCHIZO_MAX_INO	0x37
99 #define	PCI_INO_BITS	6			/* INO#s are 6 bits long */
100 #define	PCI_IGN_BITS	5			/* IGN#s are 5 bits long */
101 
102 /*
103  * ih structure: one per every consumer of each ino and pil pair with interrupt
104  * registered.
105  */
106 typedef struct ih {
107 	dev_info_t *ih_dip;		/* devinfo structure */
108 	uint32_t ih_inum;		/* interrupt number for this device */
109 	uint_t	ih_intr_state;		/* Only used for fixed interrupts */
110 	uint_t (*ih_handler)();		/* interrupt handler */
111 	caddr_t ih_handler_arg1;	/* interrupt handler argument #1 */
112 	caddr_t ih_handler_arg2;	/* interrupt handler argument #2 */
113 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
114 	struct ih *ih_next;		/* next entry in list */
115 	uint64_t ih_ticks;		/* ticks spent in this handler */
116 	uint64_t ih_nsec;		/* nsec spent in this handler */
117 	kstat_t *ih_ksp;		/* pointer to kstat information */
118 	ib_ino_pil_t *ih_ipil_p;	/* only for use by kstat */
119 } ih_t;
120 
121 /* Only used for fixed or legacy interrupts */
122 #define	PCI_INTR_STATE_DISABLE	0	/* disabled */
123 #define	PCI_INTR_STATE_ENABLE	1	/* enabled */
124 
125 /*
126  * ino_pil structure: one per each ino and pil pair with interrupt registered
127  */
128 struct ib_ino_pil {
129 	ushort_t ipil_pil;		/* PIL for this ino */
130 	ushort_t ipil_ih_size;		/* size of ih_t list */
131 	ih_t *ipil_ih_head;		/* ih_t list head */
132 	ih_t *ipil_ih_tail;		/* ih_t list tail */
133 	ih_t *ipil_ih_start;		/* starting point in ih_t list  */
134 	ib_ino_info_t *ipil_ino_p;	/* pointer to ib_ino_info_t */
135 	ib_ino_pil_t *ipil_next_p;	/* pointer to next ib_ino_pil_t */
136 };
137 
138 /*
139  * ino structure: one per each ino with interrupt registered
140  */
141 struct ib_ino_info {
142 	ib_ino_t ino_ino;		/* INO number - 8 bit */
143 	uint64_t ino_mondo;		/* store mondo number */
144 	uint8_t ino_slot_no;		/* PCI slot number 0-8 */
145 	ib_t *ino_ib_p;			/* link back to interrupt block state */
146 	volatile uint64_t *ino_clr_reg;	/* ino interrupt clear register */
147 	volatile uint64_t *ino_map_reg;	/* ino interrupt mapping register */
148 	uint64_t ino_map_reg_save;	/* = *ino_map_reg if saved */
149 	volatile uint_t ino_unclaimed_intrs; /* number of unclaimed intrs */
150 	clock_t ino_spurintr_begin;	/* begin time of spurious intr series */
151 	int ino_established;		/* ino has been associated with a cpu */
152 	uint32_t ino_cpuid;		/* cpu that ino is targeting */
153 	int32_t ino_intr_weight;	/* intr weight of devices sharing ino */
154 	ushort_t ino_ipil_size;		/* number of ib_ino_pil_t sharing ino */
155 	ushort_t ino_lopil;		/* lowest PIL sharing ino */
156 	ushort_t ino_claimed;		/* pil bit masks, who claimed intr */
157 	ib_ino_pil_t *ino_ipil_p;	/* pointer to first ib_ino_pil_t */
158 	ib_ino_info_t *ino_next_p;	/* pointer to next ib_ino_info_t */
159 };
160 
161 #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
162 #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
163 
164 #define	IB2CB(ib_p)	((ib_p)->ib_pci_p->pci_cb_p)
165 
166 #define	IB_MONDO_TO_INO(mondo)		((ib_ino_t)((mondo) & 0x3f))
167 #define	IB_INO_INTR_ON(reg_p)		*(reg_p) |= COMMON_INTR_MAP_REG_VALID
168 #define	IB_INO_INTR_OFF(reg_p)		*(reg_p) &= ~COMMON_INTR_MAP_REG_VALID
169 #define	IB_INO_INTR_RESET(reg_p)	*(reg_p) = 0ull
170 #define	IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \
171 	ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg)
172 #define	IB_INO_INTR_PENDING(reg_p, ino) \
173 	(((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \
174 	COMMON_CLEAR_INTR_REG_PENDING)
175 #define	IB_INO_INTR_CLEAR(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_IDLE
176 #define	IB_INO_INTR_TRIG(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED
177 #define	IB_INO_INTR_PEND(reg_p)		*(reg_p) = COMMON_CLEAR_INTR_REG_PENDING
178 #define	IB_INO_INTR_ISON(imr)		((imr) >> 31)
179 #define	IB_IMR2MONDO(imr) \
180 	((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO))
181 
182 #define	IB_IS_OBIO_INO(ino) (ino & 0x20)
183 
184 #define	IB_IGN_TO_MONDO(ign, ino)	(((ign) << PCI_INO_BITS) | (ino))
185 #define	IB_INO_TO_MONDO(ib_p, ino)	IB_IGN_TO_MONDO((ib_p)->ib_ign, ino)
186 
187 extern void ib_create(pci_t *pci_p);
188 extern void ib_destroy(pci_t *pci_p);
189 extern void ib_configure(ib_t *ib_p);
190 extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id);
191 extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino);
192 extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait);
193 extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino);
194 extern void ib_suspend(ib_t *ib_p);
195 extern void ib_resume(ib_t *ib_p);
196 
197 extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num);
198 extern ib_ino_pil_t *ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil,
199     ih_t *ih_p);
200 extern void ib_delete_ino_pil(ib_t *ib_p, ib_ino_pil_t *ipil_p);
201 extern void ib_free_ino_all(ib_t *ib_p);
202 extern ib_ino_pil_t *ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil);
203 extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
204 extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
205 extern ih_t *ib_intr_locate_ih(ib_ino_pil_t *ipil_p, dev_info_t *dip,
206     uint32_t inum);
207 extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum,
208     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
209     caddr_t int_handler_arg1, caddr_t int_handler_arg2);
210 extern void ib_free_ih(ih_t *ih_p);
211 extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino,
212     ib_ino_info_t *ino_p);
213 extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino,
214     ib_ino_info_t *ino_p);
215 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
216     uint_t (*handler)(caddr_t arg), caddr_t arg);
217 extern void ib_unregister_intr(ib_mondo_t mondo);
218 extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino,
219     volatile uint64_t *imr_p);
220 extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight);
221 extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id);
222 extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip,
223     ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state);
224 extern int ib_get_intr_target(pci_t *pci_p, ib_ino_t ino, int *cpu_id_p);
225 extern int ib_set_intr_target(pci_t *pci_p, ib_ino_t ino, int cpu_id);
226 extern uint8_t ib_get_ino_devs(ib_t *ib_p, uint32_t ino, uint8_t *devs_ret,
227     pcitool_intr_dev_t *devs);
228 extern void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id,
229     uint32_t ino);
230 
231 extern int pci_pil[];
232 
233 #ifdef	__cplusplus
234 }
235 #endif
236 
237 #endif	/* _SYS_PCI_IB_H */
238