17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_PCI_IB_H 287c478bd9Sstevel@tonic-gate #define _SYS_PCI_IB_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifdef __cplusplus 337c478bd9Sstevel@tonic-gate extern "C" { 347c478bd9Sstevel@tonic-gate #endif 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 37*7851eb82Sschwartz #include <sys/pci_tools.h> 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate typedef uint8_t ib_ino_t; 407c478bd9Sstevel@tonic-gate typedef uint16_t ib_mondo_t; 417c478bd9Sstevel@tonic-gate typedef struct ib_ino_info ib_ino_info_t; 427c478bd9Sstevel@tonic-gate typedef uint8_t device_num_t; 437c478bd9Sstevel@tonic-gate typedef uint8_t interrupt_t; 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate /* 467c478bd9Sstevel@tonic-gate * interrupt block soft state structure: 477c478bd9Sstevel@tonic-gate * 487c478bd9Sstevel@tonic-gate * Each pci node may share an interrupt block structure with its peer 497c478bd9Sstevel@tonic-gate * node or have its own private interrupt block structure. 507c478bd9Sstevel@tonic-gate */ 517c478bd9Sstevel@tonic-gate typedef struct ib ib_t; 527c478bd9Sstevel@tonic-gate struct ib { 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate pci_t *ib_pci_p; /* link back to pci soft state */ 557c478bd9Sstevel@tonic-gate pci_ign_t ib_ign; /* interrupt group # */ 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate /* 587c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O interrupt mapping register blocks addresses: 597c478bd9Sstevel@tonic-gate */ 607c478bd9Sstevel@tonic-gate uintptr_t ib_slot_intr_map_regs; 617c478bd9Sstevel@tonic-gate #define ib_intr_map_regs ib_slot_intr_map_regs 627c478bd9Sstevel@tonic-gate uintptr_t ib_obio_intr_map_regs; 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /* 657c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O clear interrupt register block addresses: 667c478bd9Sstevel@tonic-gate */ 677c478bd9Sstevel@tonic-gate uintptr_t ib_slot_clear_intr_regs; 687c478bd9Sstevel@tonic-gate uintptr_t ib_obio_clear_intr_regs; 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate /* 717c478bd9Sstevel@tonic-gate * UPA expansion slot interrupt mapping register addresses: 727c478bd9Sstevel@tonic-gate */ 737c478bd9Sstevel@tonic-gate volatile uint64_t *ib_upa_imr[2]; 747c478bd9Sstevel@tonic-gate uint64_t ib_upa_imr_state[2]; 757c478bd9Sstevel@tonic-gate 767c478bd9Sstevel@tonic-gate /* 777c478bd9Sstevel@tonic-gate * Interrupt retry register address: 787c478bd9Sstevel@tonic-gate */ 797c478bd9Sstevel@tonic-gate volatile uint64_t *ib_intr_retry_timer_reg; 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate /* 827c478bd9Sstevel@tonic-gate * PCI slot and onboard I/O interrupt state diag register addresses: 837c478bd9Sstevel@tonic-gate */ 847c478bd9Sstevel@tonic-gate volatile uint64_t *ib_slot_intr_state_diag_reg; 857c478bd9Sstevel@tonic-gate volatile uint64_t *ib_obio_intr_state_diag_reg; 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate uint_t ib_max_ino; /* largest supported INO */ 887c478bd9Sstevel@tonic-gate ib_ino_info_t *ib_ino_lst; /* ino link list */ 897c478bd9Sstevel@tonic-gate kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 907c478bd9Sstevel@tonic-gate kmutex_t ib_intr_lock; /* lock for internal intr */ 917c478bd9Sstevel@tonic-gate uint16_t ib_map_reg_counters[8]; /* counters for shared map */ 927c478bd9Sstevel@tonic-gate /* registers */ 937c478bd9Sstevel@tonic-gate }; 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate #define PCI_PULSE_INO 0x80000000 967c478bd9Sstevel@tonic-gate #define PSYCHO_MAX_INO 0x3f 977c478bd9Sstevel@tonic-gate #define SCHIZO_MAX_INO 0x37 987c478bd9Sstevel@tonic-gate #define PCI_INO_BITS 6 /* INO#s are 6 bits long */ 997c478bd9Sstevel@tonic-gate #define PCI_IGN_BITS 5 /* IGN#s are 5 bits long */ 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate /* 1027c478bd9Sstevel@tonic-gate * The following structure represents an interrupt entry for an INO. 1037c478bd9Sstevel@tonic-gate */ 1047c478bd9Sstevel@tonic-gate typedef struct ih { 1057c478bd9Sstevel@tonic-gate dev_info_t *ih_dip; /* devinfo structure */ 1067c478bd9Sstevel@tonic-gate uint32_t ih_inum; /* interrupt number for this device */ 1077c478bd9Sstevel@tonic-gate uint_t ih_intr_state; /* Only used for fixed interrupts */ 1087c478bd9Sstevel@tonic-gate uint_t (*ih_handler)(); /* interrupt handler */ 1097c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 1107c478bd9Sstevel@tonic-gate caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 1117c478bd9Sstevel@tonic-gate ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 1127c478bd9Sstevel@tonic-gate struct ih *ih_next; /* next entry in list */ 1137c478bd9Sstevel@tonic-gate uint64_t ih_ticks; /* ticks spent in this handler */ 1147c478bd9Sstevel@tonic-gate uint64_t ih_nsec; /* nsec spent in this handler */ 1157c478bd9Sstevel@tonic-gate kstat_t *ih_ksp; 1167c478bd9Sstevel@tonic-gate struct ib_ino_info *ih_ino_p; /* only for use by kstat */ 1177c478bd9Sstevel@tonic-gate } ih_t; 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */ 1207c478bd9Sstevel@tonic-gate #define PCI_INTR_STATE_DISABLE 0 /* disabled */ 1217c478bd9Sstevel@tonic-gate #define PCI_INTR_STATE_ENABLE 1 /* enabled */ 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate /* 1247c478bd9Sstevel@tonic-gate * ino structure : one per each psycho slot ino with interrupt registered 1257c478bd9Sstevel@tonic-gate */ 1267c478bd9Sstevel@tonic-gate struct ib_ino_info { 1277c478bd9Sstevel@tonic-gate ib_ino_t ino_ino; /* INO number - 8 bit */ 1287c478bd9Sstevel@tonic-gate uint8_t ino_slot_no; /* PCI slot number 0-8 */ 1297c478bd9Sstevel@tonic-gate uint16_t ino_ih_size; /* size of the pci intrspec list */ 1307c478bd9Sstevel@tonic-gate struct ib_ino_info *ino_next; 1317c478bd9Sstevel@tonic-gate ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 1327c478bd9Sstevel@tonic-gate ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 1337c478bd9Sstevel@tonic-gate ih_t *ino_ih_start; /* starting point in intr spec list */ 1347c478bd9Sstevel@tonic-gate ib_t *ino_ib_p; /* link back to interrupt block state */ 1357c478bd9Sstevel@tonic-gate volatile uint64_t *ino_clr_reg; /* ino interrupt clear register */ 1367c478bd9Sstevel@tonic-gate volatile uint64_t *ino_map_reg; /* ino interrupt mapping register */ 1377c478bd9Sstevel@tonic-gate uint64_t ino_map_reg_save; /* = *ino_map_reg if saved */ 1387c478bd9Sstevel@tonic-gate uint32_t ino_pil; /* PIL for this ino */ 1397c478bd9Sstevel@tonic-gate volatile uint_t ino_unclaimed; /* number of unclaimed interrupts */ 1407c478bd9Sstevel@tonic-gate clock_t ino_spurintr_begin; /* begin time of spurious intr series */ 1417c478bd9Sstevel@tonic-gate int ino_established; /* ino has been associated with a cpu */ 1427c478bd9Sstevel@tonic-gate uint32_t ino_cpuid; /* cpu that ino is targeting */ 1437c478bd9Sstevel@tonic-gate int32_t ino_intr_weight; /* intr weight of devices sharing ino */ 1447c478bd9Sstevel@tonic-gate }; 1457c478bd9Sstevel@tonic-gate 1467c478bd9Sstevel@tonic-gate #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 1477c478bd9Sstevel@tonic-gate #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 1487c478bd9Sstevel@tonic-gate 1497c478bd9Sstevel@tonic-gate #define IB2CB(ib_p) ((ib_p)->ib_pci_p->pci_cb_p) 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate #define IB_MONDO_TO_INO(mondo) ((ib_ino_t)((mondo) & 0x3f)) 1527c478bd9Sstevel@tonic-gate #define IB_INO_INTR_ON(reg_p) *(reg_p) |= COMMON_INTR_MAP_REG_VALID 1537c478bd9Sstevel@tonic-gate #define IB_INO_INTR_OFF(reg_p) *(reg_p) &= ~COMMON_INTR_MAP_REG_VALID 1547c478bd9Sstevel@tonic-gate #define IB_INO_INTR_RESET(reg_p) *(reg_p) = 0ull 1557c478bd9Sstevel@tonic-gate #define IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \ 1567c478bd9Sstevel@tonic-gate ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg) 1577c478bd9Sstevel@tonic-gate #define IB_INO_INTR_PENDING(reg_p, ino) \ 1587c478bd9Sstevel@tonic-gate (((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \ 1597c478bd9Sstevel@tonic-gate COMMON_CLEAR_INTR_REG_PENDING) 1607c478bd9Sstevel@tonic-gate #define IB_INO_INTR_CLEAR(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_IDLE 1617c478bd9Sstevel@tonic-gate #define IB_INO_INTR_TRIG(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED 1627c478bd9Sstevel@tonic-gate #define IB_INO_INTR_PEND(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_PENDING 1637c478bd9Sstevel@tonic-gate #define IB_INO_INTR_ISON(imr) ((imr) >> 31) 1647c478bd9Sstevel@tonic-gate #define IB_IMR2MONDO(imr) \ 1657c478bd9Sstevel@tonic-gate ((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO)) 1667c478bd9Sstevel@tonic-gate 1677c478bd9Sstevel@tonic-gate #define IB_IS_OBIO_INO(ino) (ino & 0x20) 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate #ifdef _STARFIRE 1707c478bd9Sstevel@tonic-gate /* 1717c478bd9Sstevel@tonic-gate * returns a uniq ino per interrupt mapping register 1727c478bd9Sstevel@tonic-gate * For on board devices, inos are not shared. But for plugin devices, 1737c478bd9Sstevel@tonic-gate * return the 1st ino of the 4 that are sharing the same mapping register. 1747c478bd9Sstevel@tonic-gate */ 1757c478bd9Sstevel@tonic-gate #define IB_GET_MAPREG_INO(ino) \ 1767c478bd9Sstevel@tonic-gate ((volatile uint64_t *)((ino & 0x20) ? ino : ((ino >> 2) << 2))) 1777c478bd9Sstevel@tonic-gate #endif /* _STARFIRE */ 1787c478bd9Sstevel@tonic-gate 1797c478bd9Sstevel@tonic-gate #define IB_IGN_TO_MONDO(ign, ino) (((ign) << PCI_INO_BITS) | (ino)) 1807c478bd9Sstevel@tonic-gate #define IB_INO_TO_MONDO(ib_p, ino) IB_IGN_TO_MONDO((ib_p)->ib_ign, ino) 1817c478bd9Sstevel@tonic-gate 1827c478bd9Sstevel@tonic-gate extern void ib_create(pci_t *pci_p); 1837c478bd9Sstevel@tonic-gate extern void ib_destroy(pci_t *pci_p); 1847c478bd9Sstevel@tonic-gate extern void ib_configure(ib_t *ib_p); 1857c478bd9Sstevel@tonic-gate extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id); 1867c478bd9Sstevel@tonic-gate extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino); 1877c478bd9Sstevel@tonic-gate extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait); 1887c478bd9Sstevel@tonic-gate extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino); 1897c478bd9Sstevel@tonic-gate extern void ib_suspend(ib_t *ib_p); 1907c478bd9Sstevel@tonic-gate extern void ib_resume(ib_t *ib_p); 1917c478bd9Sstevel@tonic-gate 1927c478bd9Sstevel@tonic-gate extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num); 1937c478bd9Sstevel@tonic-gate extern ib_ino_info_t *ib_new_ino(ib_t *ib_p, ib_ino_t ino_num, ih_t *ih_p); 1947c478bd9Sstevel@tonic-gate extern void ib_delete_ino(ib_t *ib_p, ib_ino_info_t *ino_p); 1957c478bd9Sstevel@tonic-gate extern void ib_free_ino_all(ib_t *ib_p); 1967c478bd9Sstevel@tonic-gate extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip, 1977c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state); 1987c478bd9Sstevel@tonic-gate extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 1997c478bd9Sstevel@tonic-gate extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 2007c478bd9Sstevel@tonic-gate extern ih_t *ib_ino_locate_intr(ib_ino_info_t *ino_p, dev_info_t *dip, 2017c478bd9Sstevel@tonic-gate uint32_t inum); 2027c478bd9Sstevel@tonic-gate extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum, 2037c478bd9Sstevel@tonic-gate uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2), 2047c478bd9Sstevel@tonic-gate caddr_t int_handler_arg1, caddr_t int_handler_arg2); 2057c478bd9Sstevel@tonic-gate extern void ib_free_ih(ih_t *ih_p); 2067c478bd9Sstevel@tonic-gate extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, 2077c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p); 2087c478bd9Sstevel@tonic-gate extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, 2097c478bd9Sstevel@tonic-gate ib_ino_info_t *ino_p); 2107c478bd9Sstevel@tonic-gate extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil, 2117c478bd9Sstevel@tonic-gate uint_t (*handler)(caddr_t arg), caddr_t arg); 2127c478bd9Sstevel@tonic-gate extern void ib_unregister_intr(ib_mondo_t mondo); 2137c478bd9Sstevel@tonic-gate extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, 2147c478bd9Sstevel@tonic-gate volatile uint64_t *imr_p); 2157c478bd9Sstevel@tonic-gate extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight); 216*7851eb82Sschwartz extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id); 217*7851eb82Sschwartz extern uint8_t ib_get_ino_devs(ib_t *ib_p, uint32_t ino, uint8_t *devs_ret, 218*7851eb82Sschwartz pcitool_intr_dev_t *devs); 219*7851eb82Sschwartz extern void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id, 220*7851eb82Sschwartz uint32_t ino); 2217c478bd9Sstevel@tonic-gate 2227c478bd9Sstevel@tonic-gate extern int pci_pil[]; 2237c478bd9Sstevel@tonic-gate 2247c478bd9Sstevel@tonic-gate #ifdef __cplusplus 2257c478bd9Sstevel@tonic-gate } 2267c478bd9Sstevel@tonic-gate #endif 2277c478bd9Sstevel@tonic-gate 2287c478bd9Sstevel@tonic-gate #endif /* _SYS_PCI_IB_H */ 229