17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 23*c6701b14Sayznaga * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #ifndef _SYS_MC_US3I_H 287c478bd9Sstevel@tonic-gate #define _SYS_MC_US3I_H 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate #ifdef __cplusplus 337c478bd9Sstevel@tonic-gate extern "C" { 347c478bd9Sstevel@tonic-gate #endif 357c478bd9Sstevel@tonic-gate 367c478bd9Sstevel@tonic-gate #if defined(_KERNEL) 377c478bd9Sstevel@tonic-gate 387c478bd9Sstevel@tonic-gate #define NDGRPS_PER_MC 2 /* max dimm groups per mctrl */ 397c478bd9Sstevel@tonic-gate #define NDIMMS_PER_DGRP 2 /* max dimms in a group/pair */ 407c478bd9Sstevel@tonic-gate #define NLOGBANKS_PER_DGRP 2 /* max logical banks per grp */ 417c478bd9Sstevel@tonic-gate #define NLOGBANKS_PER_MC 16 /* max logical banks per mc */ 427c478bd9Sstevel@tonic-gate #define NLOGBANKS_PER_SEG 16 /* max logical banks per seg */ 437c478bd9Sstevel@tonic-gate #define MAX_DEVLEN 8 447c478bd9Sstevel@tonic-gate #define TRANSFER_SIZE 64 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #define MC_SELECT_MASK 0x3000000000LL /* upto 4 MCs at 64GB boundry */ 477c478bd9Sstevel@tonic-gate #define MC_SELECT_SHIFT 36 487c478bd9Sstevel@tonic-gate #define DIMM_PAIR_SELECT_MASK 0x200000000LL /* at 8GB boundry */ 497c478bd9Sstevel@tonic-gate #define DIMM_PAIR_SELECT_SHIFT 33 507c478bd9Sstevel@tonic-gate #define LOG_BANK_SELECT_MASK 0x100000000LL /* at 4GB boundry */ 517c478bd9Sstevel@tonic-gate #define LOG_BANK_SELECT_SHIFT 32 527c478bd9Sstevel@tonic-gate #define XOR_DEVICE_SELECT_MASK 0x200000LL /* at 2MB boundry */ 537c478bd9Sstevel@tonic-gate #define XOR_DEVICE_SELECT_SHIFT 21 547c478bd9Sstevel@tonic-gate #define XOR_BANK_SELECT_MASK 0x100000LL /* at 1MB boundry */ 557c478bd9Sstevel@tonic-gate #define XOR_BANK_SELECT_SHIFT 20 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate #define MC_SIZE_MAX 0x1000000000LL /* 64GB */ 587c478bd9Sstevel@tonic-gate #define DGRP_SIZE_MAX 0x200000000LL /* 8GB */ 597c478bd9Sstevel@tonic-gate #define BANK_SIZE_MAX 0x100000000LL /* 4GB */ 607c478bd9Sstevel@tonic-gate 617c478bd9Sstevel@tonic-gate #define MC_BASE(id) (id * MC_SIZE_MAX) 627c478bd9Sstevel@tonic-gate #define DGRP_BASE(id) ((id & (NDGRPS_PER_MC - 1)) * DGRP_SIZE_MAX) 637c478bd9Sstevel@tonic-gate #define LOGBANK_BASE(id) ((id & (NLOGBANKS_PER_SEG - 1)) * BANK_SIZE_MAX) 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate #define ADDR_GEN_128Mb_X8_ROW_0 14 667c478bd9Sstevel@tonic-gate #define ADDR_GEN_512Mb_X8_ROW_0 15 677c478bd9Sstevel@tonic-gate 687c478bd9Sstevel@tonic-gate #ifndef _ASM 697c478bd9Sstevel@tonic-gate 707c478bd9Sstevel@tonic-gate struct mc_soft_state { 717c478bd9Sstevel@tonic-gate dev_info_t *dip; /* dev info of myself */ 727c478bd9Sstevel@tonic-gate int portid; 737c478bd9Sstevel@tonic-gate int mcr_read_ok; 747c478bd9Sstevel@tonic-gate uint64_t mcreg1; 757c478bd9Sstevel@tonic-gate int reglen; 767c478bd9Sstevel@tonic-gate void *reg; 777c478bd9Sstevel@tonic-gate int memlayoutlen; 787c478bd9Sstevel@tonic-gate void *memlayoutp; 797c478bd9Sstevel@tonic-gate }; 807c478bd9Sstevel@tonic-gate 817c478bd9Sstevel@tonic-gate struct memory_reg_info { 827c478bd9Sstevel@tonic-gate uint64_t base; 837c478bd9Sstevel@tonic-gate uint64_t size; 847c478bd9Sstevel@tonic-gate }; 857c478bd9Sstevel@tonic-gate 867c478bd9Sstevel@tonic-gate struct dimm_info { 877c478bd9Sstevel@tonic-gate char label[NDGRPS_PER_MC * NDIMMS_PER_DGRP][MAX_DEVLEN]; 887c478bd9Sstevel@tonic-gate char table_width; /* 1: symmetric 0: asymmetric */ 897c478bd9Sstevel@tonic-gate char data[1]; 907c478bd9Sstevel@tonic-gate }; 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate struct pin_info { 937c478bd9Sstevel@tonic-gate uchar_t dimmtable[18]; 947c478bd9Sstevel@tonic-gate uchar_t pintable[144]; 957c478bd9Sstevel@tonic-gate }; 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate /* This struct is included at the following structs to set up list */ 987c478bd9Sstevel@tonic-gate typedef struct mc_dlist { 997c478bd9Sstevel@tonic-gate struct mc_dlist *next; 1007c478bd9Sstevel@tonic-gate struct mc_dlist *prev; 1017c478bd9Sstevel@tonic-gate int id; 1027c478bd9Sstevel@tonic-gate } mc_dlist_t; 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate /* unique segment id */ 1057c478bd9Sstevel@tonic-gate struct seg_info { 1067c478bd9Sstevel@tonic-gate mc_dlist_t seg_node; 1077c478bd9Sstevel@tonic-gate int nbanks; /* The number of banks at this segment */ 1087c478bd9Sstevel@tonic-gate uint32_t ifactor; /* Max interleave factor at this segment */ 1097c478bd9Sstevel@tonic-gate uint64_t base; 1107c478bd9Sstevel@tonic-gate uint64_t size; /* memory size per segment */ 1117c478bd9Sstevel@tonic-gate struct bank_info *head; /* first bank at this segment */ 1127c478bd9Sstevel@tonic-gate struct bank_info *tail; /* last bank at this segment */ 1137c478bd9Sstevel@tonic-gate }; 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate /* id = mc_id * nbanks + bank_no */ 1167c478bd9Sstevel@tonic-gate struct bank_info { 1177c478bd9Sstevel@tonic-gate mc_dlist_t bank_node; 1187c478bd9Sstevel@tonic-gate int local_id; /* unique local bank id per segment */ 1197c478bd9Sstevel@tonic-gate int seg_id; /* unique segment id */ 1207c478bd9Sstevel@tonic-gate int devgrp_id; /* unique device group id */ 1217c478bd9Sstevel@tonic-gate uint64_t mask; /* If (Physical Address & MASK) == MATCH */ 1227c478bd9Sstevel@tonic-gate uint64_t match; /* Physic Address is located at this bank. */ 1237c478bd9Sstevel@tonic-gate uint64_t base; /* base address of the logical bank */ 1247c478bd9Sstevel@tonic-gate uint64_t size; /* memory size per logical bank */ 1257c478bd9Sstevel@tonic-gate struct bank_info *next; /* next bank at the same segment */ 1267c478bd9Sstevel@tonic-gate }; 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate /* id = id of dgrp_info * ndevices + device_no */ 1297c478bd9Sstevel@tonic-gate struct device_info { 1307c478bd9Sstevel@tonic-gate mc_dlist_t dev_node; 1317c478bd9Sstevel@tonic-gate char label[MAX_DEVLEN]; 1327c478bd9Sstevel@tonic-gate uint64_t size; /* memory size per physical dimm */ 1337c478bd9Sstevel@tonic-gate }; 1347c478bd9Sstevel@tonic-gate 1357c478bd9Sstevel@tonic-gate /* id = mc_id * ndevgrps + devgrp_no */ 1367c478bd9Sstevel@tonic-gate struct dgrp_info { 1377c478bd9Sstevel@tonic-gate mc_dlist_t dgrp_node; 1387c478bd9Sstevel@tonic-gate int ndevices; /* number of physical dimms - always a pair */ 1397c478bd9Sstevel@tonic-gate int nlogbanks; /* number of logical banks - single or dual */ 1407c478bd9Sstevel@tonic-gate int base_device; /* base density - 128Mb, 256Mb, 512Mb or 1Gb */ 1417c478bd9Sstevel@tonic-gate int part_type; /* part type - x4, x8 */ 1427c478bd9Sstevel@tonic-gate uint64_t base; /* physical memory base of the dev group */ 1437c478bd9Sstevel@tonic-gate uint64_t size; /* total memory size of the dev group */ 1447c478bd9Sstevel@tonic-gate int deviceids[NDIMMS_PER_DGRP]; /* 2 dimms per group on Jalapeno */ 1457c478bd9Sstevel@tonic-gate }; 1467c478bd9Sstevel@tonic-gate 1477c478bd9Sstevel@tonic-gate /* id = portid */ 1487c478bd9Sstevel@tonic-gate struct mctrl_info { 1497c478bd9Sstevel@tonic-gate mc_dlist_t mctrl_node; 1507c478bd9Sstevel@tonic-gate int ndevgrps; /* The number of dimm groups */ 1517c478bd9Sstevel@tonic-gate int devgrpids[NDGRPS_PER_MC]; 1527c478bd9Sstevel@tonic-gate struct dimm_info *dimminfop; 1537c478bd9Sstevel@tonic-gate }; 1547c478bd9Sstevel@tonic-gate 1557c478bd9Sstevel@tonic-gate extern int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 1567c478bd9Sstevel@tonic-gate extern int (*p2get_mem_info)(int, uint64_t, uint64_t *, uint64_t *, 1577c478bd9Sstevel@tonic-gate uint64_t *, int *, int *, int *); 158*c6701b14Sayznaga extern void plat_add_mem_unum_label(char *, int, int, int); 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate uint64_t get_mcr(int); 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate /* #ifdef DEBUG */ 1637c478bd9Sstevel@tonic-gate 1647c478bd9Sstevel@tonic-gate #include <sys/promif.h> 1657c478bd9Sstevel@tonic-gate 1667c478bd9Sstevel@tonic-gate /* useful debugging level of DPRINTF */ 1677c478bd9Sstevel@tonic-gate #define MC_ATTACH_DEBUG 0x00000001 1687c478bd9Sstevel@tonic-gate #define MC_DETACH_DEBUG 0x00000002 1697c478bd9Sstevel@tonic-gate #define MC_CMD_DEBUG 0x00000004 1707c478bd9Sstevel@tonic-gate #define MC_REG_DEBUG 0x00000008 1717c478bd9Sstevel@tonic-gate #define MC_GUNUM_DEBUG 0x00000010 1727c478bd9Sstevel@tonic-gate #define MC_CNSTRC_DEBUG 0x00000020 1737c478bd9Sstevel@tonic-gate #define MC_DESTRC_DEBUG 0x00000040 1747c478bd9Sstevel@tonic-gate #define MC_LIST_DEBUG 0x00000080 1757c478bd9Sstevel@tonic-gate 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate #define _PRINTF printf 1787c478bd9Sstevel@tonic-gate #define DPRINTF(flag, args) if (mc_debug & flag) _PRINTF args; 1797c478bd9Sstevel@tonic-gate #else 1807c478bd9Sstevel@tonic-gate #define DPRINTF(flag, args) 1817c478bd9Sstevel@tonic-gate 1827c478bd9Sstevel@tonic-gate /* #endif DEBUG */ 1837c478bd9Sstevel@tonic-gate 1847c478bd9Sstevel@tonic-gate #endif /* !_ASM */ 1857c478bd9Sstevel@tonic-gate 1867c478bd9Sstevel@tonic-gate /* Memory Control Registers */ 1877c478bd9Sstevel@tonic-gate #define ASI_MCU_CTRL 0x72 1887c478bd9Sstevel@tonic-gate #define MCREG1OFFSET 0x00 1897c478bd9Sstevel@tonic-gate 1907c478bd9Sstevel@tonic-gate /* Mask and shift constants for Memory Control Register I */ 1917c478bd9Sstevel@tonic-gate #define MCREG1_DIMM2_BANK3 0x8000000000000000ULL /* bit 63 */ 1927c478bd9Sstevel@tonic-gate #define MCREG1_DIMM1_BANK1 0x4000000000000000ULL /* bit 62 */ 1937c478bd9Sstevel@tonic-gate #define MCREG1_DIMM2_BANK2 0x2000000000000000ULL /* bit 61 */ 1947c478bd9Sstevel@tonic-gate #define MCREG1_DIMM1_BANK0 0x1000000000000000ULL /* bit 60 */ 1957c478bd9Sstevel@tonic-gate 1967c478bd9Sstevel@tonic-gate #define MCREG1_XOR_ENABLE 0x10000000000LL /* bit 40 */ 1977c478bd9Sstevel@tonic-gate #define MCREG1_ADDRGEN2_MASK 0xE000000000LL /* bits 39:37 */ 1987c478bd9Sstevel@tonic-gate #define MCREG1_ADDRGEN2_SHIFT 37 1997c478bd9Sstevel@tonic-gate #define MCREG1_ADDRGEN1_MASK 0x1C00000000LL /* bits 36:34 */ 2007c478bd9Sstevel@tonic-gate #define MCREG1_ADDRGEN1_SHIFT 34 2017c478bd9Sstevel@tonic-gate #define BASE_DEVICE_128Mb 0 2027c478bd9Sstevel@tonic-gate #define BASE_DEVICE_256Mb 1 2037c478bd9Sstevel@tonic-gate #define BASE_DEVICE_512Mb 2 2047c478bd9Sstevel@tonic-gate #define BASE_DEVICE_1Gb 3 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate #define MCREG1_INTERLEAVE_MASK 0x1800000LL /* bits 24:23 */ 2077c478bd9Sstevel@tonic-gate #define MCREG1_INTERLEAVE_SHIFT 23 2087c478bd9Sstevel@tonic-gate #define INTERLEAVE_DISABLE 0 2097c478bd9Sstevel@tonic-gate #define INTERLEAVE_INTEXT_SAME_DIMM_PAIR 1 2107c478bd9Sstevel@tonic-gate #define INTERLEAVE_INTERNAL 2 2117c478bd9Sstevel@tonic-gate #define INTERLEAVE_INTEXT_BOTH_DIMM_PAIR 3 2127c478bd9Sstevel@tonic-gate 2137c478bd9Sstevel@tonic-gate #define MCREG1_X4DIMM2_MASK 0x200000LL /* bit 21 */ 2147c478bd9Sstevel@tonic-gate #define MCREG1_X4DIMM2_SHIFT 21 2157c478bd9Sstevel@tonic-gate #define MCREG1_X4DIMM1_MASK 0x100000LL /* bit 20 */ 2167c478bd9Sstevel@tonic-gate #define MCREG1_X4DIMM1_SHIFT 20 2177c478bd9Sstevel@tonic-gate #define PART_TYPE_X4 1 2187c478bd9Sstevel@tonic-gate #define PART_TYPE_X8 0 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate #endif /* _KERNEL */ 2217c478bd9Sstevel@tonic-gate 2227c478bd9Sstevel@tonic-gate #ifdef __cplusplus 2237c478bd9Sstevel@tonic-gate } 2247c478bd9Sstevel@tonic-gate #endif 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate #endif /* _SYS_MC_US3I_H */ 227