xref: /illumos-gate/usr/src/uts/sun4u/sys/isadma.h (revision 7c478bd9)
1*7c478bd9Sstevel@tonic-gate /*
2*7c478bd9Sstevel@tonic-gate  * CDDL HEADER START
3*7c478bd9Sstevel@tonic-gate  *
4*7c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*7c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*7c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*7c478bd9Sstevel@tonic-gate  * with the License.
8*7c478bd9Sstevel@tonic-gate  *
9*7c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*7c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*7c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*7c478bd9Sstevel@tonic-gate  * and limitations under the License.
13*7c478bd9Sstevel@tonic-gate  *
14*7c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*7c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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17*7c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*7c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
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20*7c478bd9Sstevel@tonic-gate  * CDDL HEADER END
21*7c478bd9Sstevel@tonic-gate  */
22*7c478bd9Sstevel@tonic-gate /*
23*7c478bd9Sstevel@tonic-gate  * Copyright (c) 2000 by Sun Microsystems, Inc.
24*7c478bd9Sstevel@tonic-gate  * All rights reserved.
25*7c478bd9Sstevel@tonic-gate  */
26*7c478bd9Sstevel@tonic-gate 
27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_ISADMA_H
28*7c478bd9Sstevel@tonic-gate #define	_SYS_ISADMA_H
29*7c478bd9Sstevel@tonic-gate 
30*7c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*7c478bd9Sstevel@tonic-gate 
32*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
33*7c478bd9Sstevel@tonic-gate extern "C" {
34*7c478bd9Sstevel@tonic-gate #endif
35*7c478bd9Sstevel@tonic-gate 
36*7c478bd9Sstevel@tonic-gate /*
37*7c478bd9Sstevel@tonic-gate  * definition of ebus reg spec entry:
38*7c478bd9Sstevel@tonic-gate  */
39*7c478bd9Sstevel@tonic-gate typedef struct {
40*7c478bd9Sstevel@tonic-gate 	uint32_t ebus_addr_hi;
41*7c478bd9Sstevel@tonic-gate 	uint32_t ebus_addr_low;
42*7c478bd9Sstevel@tonic-gate 	uint32_t ebus_size;
43*7c478bd9Sstevel@tonic-gate } ebus_regspec_t;
44*7c478bd9Sstevel@tonic-gate 
45*7c478bd9Sstevel@tonic-gate /*
46*7c478bd9Sstevel@tonic-gate  * driver soft state structure:
47*7c478bd9Sstevel@tonic-gate  */
48*7c478bd9Sstevel@tonic-gate typedef struct {
49*7c478bd9Sstevel@tonic-gate 	dev_info_t *isadma_dip;			/* Our dip */
50*7c478bd9Sstevel@tonic-gate 	ebus_regspec_t *isadma_regp;		/* Our cached registers */
51*7c478bd9Sstevel@tonic-gate 	int32_t isadma_reglen;			/* reg len */
52*7c478bd9Sstevel@tonic-gate 	kmutex_t isadma_access_lock;		/* PIO/DMA lock */
53*7c478bd9Sstevel@tonic-gate 	kcondvar_t isadma_access_cv;		/* cv to prevent PIO's */
54*7c478bd9Sstevel@tonic-gate 	dev_info_t *isadma_ldip;		/* DMA lock dip */
55*7c478bd9Sstevel@tonic-gate 	int isadma_want;			/* Want state flag */
56*7c478bd9Sstevel@tonic-gate } isadma_devstate_t;
57*7c478bd9Sstevel@tonic-gate 
58*7c478bd9Sstevel@tonic-gate /*
59*7c478bd9Sstevel@tonic-gate  * Lower bound and upper bound of DMA address space hole. Registers
60*7c478bd9Sstevel@tonic-gate  * in this hole belong to our childs  devices.
61*7c478bd9Sstevel@tonic-gate  */
62*7c478bd9Sstevel@tonic-gate #define	LO_BOUND	DMAC2_ALLMASK
63*7c478bd9Sstevel@tonic-gate #define	HI_BOUND	DMA_0XCNT
64*7c478bd9Sstevel@tonic-gate #define	IN_CHILD_SPACE(o)	((o) > LO_BOUND && (o) < HI_BOUND)
65*7c478bd9Sstevel@tonic-gate #define	IN_16BIT_SPACE(o)	((((o) >= DMA_0ADR) && (o) <= DMA_3WCNT) || \
66*7c478bd9Sstevel@tonic-gate 	(((o) >= DMA_4ADR) && ((o) <= DMA_7WCNT)))
67*7c478bd9Sstevel@tonic-gate #define	IS_SEQREG(o)		(((o) == DMAC1_CLFF) || ((o) == DMAC2_CLFF))
68*7c478bd9Sstevel@tonic-gate #define	HDL_TO_SEQREG_ADDR(h, o) \
69*7c478bd9Sstevel@tonic-gate 	((((o) >= DMA_0ADR) && ((o) <= DMA_3WCNT)) ? \
70*7c478bd9Sstevel@tonic-gate 	(h)->ahi_common.ah_addr + DMAC1_CLFF : \
71*7c478bd9Sstevel@tonic-gate 	(h)->ahi_common.ah_addr + DMAC2_CLFF)
72*7c478bd9Sstevel@tonic-gate 
73*7c478bd9Sstevel@tonic-gate #define	BEGIN_ISADMA(o, v)	((o) == DMAC1_ALLMASK && (v))
74*7c478bd9Sstevel@tonic-gate #define	END_ISADMA(o, v)	((o) == DMAC1_ALLMASK && (v) == 0)
75*7c478bd9Sstevel@tonic-gate 
76*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
77*7c478bd9Sstevel@tonic-gate }
78*7c478bd9Sstevel@tonic-gate #endif
79*7c478bd9Sstevel@tonic-gate 
80*7c478bd9Sstevel@tonic-gate #endif	/* _SYS_ISADMA_H */
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