17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
5ed05dc5vb * Common Development and Distribution License (the "License").
6ed05dc5vb * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
217c478bdstevel@tonic-gate/*
22ed05dc5vb * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
237c478bdstevel@tonic-gate * Use is subject to license terms.
247c478bdstevel@tonic-gate */
257c478bdstevel@tonic-gate
267c478bdstevel@tonic-gate#ifndef	_CHEETAHASM_H
277c478bdstevel@tonic-gate#define	_CHEETAHASM_H
287c478bdstevel@tonic-gate
297c478bdstevel@tonic-gate#pragma ident	"%Z%%M%	%I%	%E% SMI"
307c478bdstevel@tonic-gate
317c478bdstevel@tonic-gate#ifdef	__cplusplus
327c478bdstevel@tonic-gateextern "C" {
337c478bdstevel@tonic-gate#endif
347c478bdstevel@tonic-gate
357c478bdstevel@tonic-gate#ifdef _ASM
367c478bdstevel@tonic-gate/* BEGIN CSTYLED */
377c478bdstevel@tonic-gate
387c478bdstevel@tonic-gate#define	ASM_LD(reg, symbol)						\
397c478bdstevel@tonic-gate	sethi	%hi(symbol), reg;					\
407c478bdstevel@tonic-gate	ld	[reg + %lo(symbol)], reg;				\
417c478bdstevel@tonic-gate
427c478bdstevel@tonic-gate#define	ASM_LDX(reg, symbol)						\
437c478bdstevel@tonic-gate	sethi	%hi(symbol), reg;					\
447c478bdstevel@tonic-gate	ldx	[reg + %lo(symbol)], reg;				\
457c478bdstevel@tonic-gate
467c478bdstevel@tonic-gate#define	ASM_JMP(reg, symbol)						\
477c478bdstevel@tonic-gate	sethi	%hi(symbol), reg;					\
487c478bdstevel@tonic-gate	jmp	reg + %lo(symbol);					\
497c478bdstevel@tonic-gate	nop
507c478bdstevel@tonic-gate
517c478bdstevel@tonic-gate/*
527c478bdstevel@tonic-gate * Macro for getting to offset from 'cpu_private' ptr.  The 'cpu_private'
537c478bdstevel@tonic-gate * ptr is in the machcpu structure.
547c478bdstevel@tonic-gate *  off_reg:  Register offset from 'cpu_private' ptr.
557c478bdstevel@tonic-gate *  scr1:    Scratch, ptr is returned in this register.
567c478bdstevel@tonic-gate *  scr2:    Scratch
577c478bdstevel@tonic-gate *  label:   Label to branch to if cpu_private ptr is null/zero.
587c478bdstevel@tonic-gate */
597c478bdstevel@tonic-gate#define	GET_CPU_PRIVATE_PTR(off_reg, scr1, scr2, label)			\
607c478bdstevel@tonic-gate	CPU_ADDR(scr1, scr2);						\
617c478bdstevel@tonic-gate	ldn	[scr1 + CPU_PRIVATE], scr1;				\
627c478bdstevel@tonic-gate	cmp	scr1, 0;						\
637c478bdstevel@tonic-gate	be	label;							\
647c478bdstevel@tonic-gate	  nop;								\
657c478bdstevel@tonic-gate	add	scr1, off_reg, scr1
667c478bdstevel@tonic-gate
677c478bdstevel@tonic-gate/*
687c478bdstevel@tonic-gate * Macro version of get_dcache_dtag.  We use this macro in the
697c478bdstevel@tonic-gate * CPU logout code. Since the Dcache is virtually indexed, only
707c478bdstevel@tonic-gate * bits [12:5] of the AFAR can be used so we need to search through
717c478bdstevel@tonic-gate * 8 indexes (4 ways + bit 13) in order to find the tag we want.
727c478bdstevel@tonic-gate *   afar:  input AFAR, not modified.
737c478bdstevel@tonic-gate *   datap: input ptr to ch_dc_data_t, at end pts to end of ch_dc_data_t.
747c478bdstevel@tonic-gate *   scr1:  scratch.
757c478bdstevel@tonic-gate *   scr2:  scratch, will hold tag to look for.
767c478bdstevel@tonic-gate *   scr3:  used for Dcache index, loops through 4 ways.
777c478bdstevel@tonic-gate */
787c478bdstevel@tonic-gate#define	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
797c478bdstevel@tonic-gate	set	CH_DCACHE_IDX_MASK, scr3;				\
807c478bdstevel@tonic-gate	and	afar, scr3, scr3;					\
817c478bdstevel@tonic-gate	srlx	afar, CH_DCTAG_PA_SHIFT, scr2;				\
827c478bdstevel@tonic-gate	b	1f;							\
837c478bdstevel@tonic-gate	  or	scr2, CH_DCTAG_VALID_BIT, scr2; /* tag we want */	\
847c478bdstevel@tonic-gate	.align	128;							\
857c478bdstevel@tonic-gate1:									\
867c478bdstevel@tonic-gate	ldxa	[scr3]ASI_DC_TAG, scr1;		/* read tag */		\
877c478bdstevel@tonic-gate	cmp	scr1, scr2;						\
887c478bdstevel@tonic-gate	bne	4f;				/* not found? */	\
897c478bdstevel@tonic-gate	  nop;								\
907c478bdstevel@tonic-gate	stxa	scr3, [datap + CH_DC_IDX]%asi;	/* store index */	\
917c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_DC_TAG]%asi;	/* store tag */		\
927c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.3 */	\
937c478bdstevel@tonic-gate	ldxa	[scr3]ASI_DC_UTAG, scr1;	/* read utag */		\
947c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.3 */	\
957c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_DC_UTAG]%asi;				\
967c478bdstevel@tonic-gate	ldxa	[scr3]ASI_DC_SNP_TAG, scr1;	/* read snoop tag */	\
977c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_DC_SNTAG]%asi;			\
987c478bdstevel@tonic-gate	add	datap, CH_DC_DATA, datap;				\
997c478bdstevel@tonic-gate	clr	scr2;							\
1007c478bdstevel@tonic-gate2:									\
1017c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
1027c478bdstevel@tonic-gate	ldxa	[scr3 + scr2]ASI_DC_DATA, scr1;	/* read data */		\
1037c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
1047c478bdstevel@tonic-gate	stxa	scr1, [datap]%asi;					\
1057c478bdstevel@tonic-gate	add	datap, 8, datap;					\
1067c478bdstevel@tonic-gate	cmp	scr2, CH_DC_DATA_REG_SIZE - 8;				\
1077c478bdstevel@tonic-gate	blt	2b;							\
1087c478bdstevel@tonic-gate	  add	scr2, 8, scr2;						\
1097c478bdstevel@tonic-gate									\
1107c478bdstevel@tonic-gate	GET_CPU_IMPL(scr2);	/* Parity bits are elsewhere for */	\
1117c478bdstevel@tonic-gate	cmp	scr2, PANTHER_IMPL;	/* panther processors. */	\
1127c478bdstevel@tonic-gate	bne,a	5f;			/* Done if not panther. */	\
1137c478bdstevel@tonic-gate	  add	datap, 8, datap; /* Skip to the end of the struct. */	\
1147c478bdstevel@tonic-gate	clr	scr2;							\
1157c478bdstevel@tonic-gate	add	datap, 7, datap; /* offset of the last parity byte */	\
1167c478bdstevel@tonic-gate	mov	1, scr1;						\
1177c478bdstevel@tonic-gate	sll	scr1, PN_DC_DATA_PARITY_BIT_SHIFT, scr1;		\
1187c478bdstevel@tonic-gate	or	scr3, scr1, scr3; /* add DC_data_parity bit to index */	\
1197c478bdstevel@tonic-gate3:									\
1207c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
1217c478bdstevel@tonic-gate	ldxa	[scr3 + scr2]ASI_DC_DATA, scr1;	/* read parity bits */	\
1227c478bdstevel@tonic-gate	membar	#Sync;			/* Cheetah PRM 10.6.1 */	\
1237c478bdstevel@tonic-gate	stba	scr1, [datap]%asi;					\
1247c478bdstevel@tonic-gate	dec	datap;							\
1257c478bdstevel@tonic-gate	cmp	scr2, CH_DC_DATA_REG_SIZE - 8;				\
1267c478bdstevel@tonic-gate	blt	3b;							\
1277c478bdstevel@tonic-gate	  add	scr2, 8, scr2;						\
1287c478bdstevel@tonic-gate	b	5f;							\
1297c478bdstevel@tonic-gate	  add	datap, 5, datap; /* set pointer to end of our struct */	\
1307c478bdstevel@tonic-gate4:									\
1317c478bdstevel@tonic-gate	set	CH_DCACHE_IDX_INCR, scr1;	/* incr. idx (scr3) */	\
1327c478bdstevel@tonic-gate	add	scr3, scr1, scr3;					\
1337c478bdstevel@tonic-gate	set	CH_DCACHE_IDX_LIMIT, scr1;	/* done? */		\
1347c478bdstevel@tonic-gate	cmp	scr3, scr1;						\
1357c478bdstevel@tonic-gate	blt	1b;							\
1367c478bdstevel@tonic-gate	  nop;								\
1377c478bdstevel@tonic-gate	add	datap, CH_DC_DATA_SIZE, datap;				\
1387c478bdstevel@tonic-gate5:
1397c478bdstevel@tonic-gate
1407c478bdstevel@tonic-gate/*
1417c478bdstevel@tonic-gate * Macro version of get_icache_dtag.  We use this macro in the CPU
1427c478bdstevel@tonic-gate * logout code. If the Icache is on, we don't want to capture the data.
1437c478bdstevel@tonic-gate *   afar:  input AFAR, not modified.
1447c478bdstevel@tonic-gate *   datap: input ptr to ch_ic_data_t, at end pts to end of ch_ic_data_t.
1457c478bdstevel@tonic-gate *   scr1:  scratch.
1467c478bdstevel@tonic-gate *   scr2:  scratch, will hold tag to look for.
1477c478bdstevel@tonic-gate *   scr3:  used for Icache index, loops through 4 ways.
1487c478bdstevel@tonic-gate * Note: For Panther, the Icache is virtually indexed and increases in
1497c478bdstevel@tonic-gate * size to 64KB (instead of 32KB) with a line size of 64 bytes (instead
1507c478bdstevel@tonic-gate * of 32). This means the IC_addr index bits[14:7] for Panther now
1517c478bdstevel@tonic-gate * correspond to VA bits[13:6]. But since it is virtually indexed, we
1527c478bdstevel@tonic-gate * still mask out only bits[12:5] from the AFAR (we have to manually
1537c478bdstevel@tonic-gate * check bit 13). In order to make this code work for all processors,
1547c478bdstevel@tonic-gate * we end up checking twice as many indexes (8 instead of 4) as required
1557c478bdstevel@tonic-gate * for non-Panther CPUs and saving off twice as much data (16 instructions
1567c478bdstevel@tonic-gate * instead of just 8).
1577c478bdstevel@tonic-gate */
1587c478bdstevel@tonic-gate#define	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
1597c478bdstevel@tonic-gate	ldxa	[%g0]ASI_DCU, scr1;					\
1607c478bdstevel@tonic-gate	btst	DCU_IC, scr1;		/* is Icache enabled? */	\
1617c478bdstevel@tonic-gate	bne,a	6f;			/* yes, don't capture */	\
1627c478bdstevel@tonic-gate	  add	datap, CH_IC_DATA_SIZE, datap;	/* anul if no branch */	\
1637c478bdstevel@tonic-gate	GET_CPU_IMPL(scr2);	/* Panther only uses VA[13:6] */	\
1647c478bdstevel@tonic-gate	cmp	scr2, PANTHER_IMPL;	/* and we also want to mask */	\
1657c478bdstevel@tonic-gate	be	1f;			/* out bit 13 since the */	\
1667c478bdstevel@tonic-gate	  nop;				/* Panther I$ is VIPT. */	\
1677c478bdstevel@tonic-gate	set	CH_ICACHE_IDX_MASK, scr3;				\
1687c478bdstevel@tonic-gate	b	2f;							\
1697c478bdstevel@tonic-gate	  nop;								\
1707c478bdstevel@tonic-gate1:									\
1717c478bdstevel@tonic-gate	set	PN_ICACHE_VA_IDX_MASK, scr3;				\
1727c478bdstevel@tonic-gate2:									\
1737c478bdstevel@tonic-gate	and	afar, scr3, scr3;					\
1747c478bdstevel@tonic-gate	sllx	scr3, CH_ICACHE_IDX_SHIFT, scr3;			\
1757c478bdstevel@tonic-gate	srlx	afar, CH_ICPATAG_SHIFT, scr2;	/* pa tag we want */	\
1767c478bdstevel@tonic-gate	andn	scr2, CH_ICPATAG_LBITS, scr2;	/* mask off lower */	\
1777c478bdstevel@tonic-gate	b	3f;							\
1787c478bdstevel@tonic-gate	  nop;								\
1797c478bdstevel@tonic-gate	.align	128;							\
1807c478bdstevel@tonic-gate3:									\
1817c478bdstevel@tonic-gate	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read pa tag */	\
1827c478bdstevel@tonic-gate	andn	scr1, CH_ICPATAG_LBITS, scr1;	/* mask off lower */	\
1837c478bdstevel@tonic-gate	cmp	scr1, scr2;						\
1847c478bdstevel@tonic-gate	bne	5f;				/* not found? */	\
1857c478bdstevel@tonic-gate	  nop;								\
1867c478bdstevel@tonic-gate	stxa	scr3, [datap + CH_IC_IDX]%asi;	/* store index */	\
1877c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_IC_PATAG]%asi; /* store pa tag */	\
1887c478bdstevel@tonic-gate	add	scr3, CH_ICTAG_UTAG, scr3;	/* read utag */		\
1897c478bdstevel@tonic-gate	ldxa	[scr3]ASI_IC_TAG, scr1;					\
1907c478bdstevel@tonic-gate	add	scr3, (CH_ICTAG_UPPER - CH_ICTAG_UTAG), scr3;		\
1917c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_IC_UTAG]%asi;				\
1927c478bdstevel@tonic-gate	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read upper tag */	\
1937c478bdstevel@tonic-gate	add	scr3, (CH_ICTAG_LOWER - CH_ICTAG_UPPER), scr3;		\
1947c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_IC_UPPER]%asi;			\
1957c478bdstevel@tonic-gate	ldxa	[scr3]ASI_IC_TAG, scr1;		/* read lower tag */	\
1967c478bdstevel@tonic-gate	andn	scr3, CH_ICTAG_TMASK, scr3;				\
1977c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_IC_LOWER]%asi;			\
1987c478bdstevel@tonic-gate	ldxa	[scr3]ASI_IC_SNP_TAG, scr1;	/* read snoop tag */	\
1997c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_IC_SNTAG]%asi;			\
2007c478bdstevel@tonic-gate	add	datap, CH_IC_DATA, datap;				\
2017c478bdstevel@tonic-gate	clr	scr2;							\
2027c478bdstevel@tonic-gate4:									\
2037c478bdstevel@tonic-gate	ldxa	[scr3 + scr2]ASI_IC_DATA, scr1;	/* read ins. data */	\
2047c478bdstevel@tonic-gate	stxa	scr1, [datap]%asi;					\
2057c478bdstevel@tonic-gate	add	datap, 8, datap;					\
2067c478bdstevel@tonic-gate	cmp	scr2, PN_IC_DATA_REG_SIZE - 8;				\
2077c478bdstevel@tonic-gate	blt	4b;							\
2087c478bdstevel@tonic-gate	  add	scr2, 8, scr2;						\
2097c478bdstevel@tonic-gate	b	6f;							\
2107c478bdstevel@tonic-gate	  nop;								\
2117c478bdstevel@tonic-gate5:									\
2127c478bdstevel@tonic-gate	set	CH_ICACHE_IDX_INCR, scr1;	/* incr. idx (scr3) */	\
2137c478bdstevel@tonic-gate	add	scr3, scr1, scr3;					\
2147c478bdstevel@tonic-gate	set	PN_ICACHE_IDX_LIMIT, scr1;	/* done? */		\
2157c478bdstevel@tonic-gate	cmp	scr3, scr1;						\
2167c478bdstevel@tonic-gate	blt	3b;							\
2177c478bdstevel@tonic-gate	  nop;								\
2187c478bdstevel@tonic-gate	add	datap, CH_IC_DATA_SIZE, datap;				\
2197c478bdstevel@tonic-gate6:
2207c478bdstevel@tonic-gate
2217c478bdstevel@tonic-gate#if defined(JALAPENO) || defined(SERRANO)
2227c478bdstevel@tonic-gate/*
2237c478bdstevel@tonic-gate * Macro version of get_ecache_dtag.  We use this macro in the
2247c478bdstevel@tonic-gate * CPU logout code.
2257c478bdstevel@tonic-gate *   afar:	input AFAR, not modified
2267c478bdstevel@tonic-gate *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
2277c478bdstevel@tonic-gate *   ec_way:	Constant value (way number)
2287c478bdstevel@tonic-gate *   scr1:      Scratch
2297c478bdstevel@tonic-gate *   scr2:	Scratch.
2307c478bdstevel@tonic-gate *   scr3:	Scratch.
2317c478bdstevel@tonic-gate */
2327c478bdstevel@tonic-gate#define	GET_ECACHE_DTAG(afar, datap, ec_way, scr1, scr2, scr3)		\
2337c478bdstevel@tonic-gate	mov	ec_way, scr1;						\
2347c478bdstevel@tonic-gate	and	scr1, JP_ECACHE_NWAY - 1, scr1;	/* mask E$ way bits */	\
2357c478bdstevel@tonic-gate	sllx	scr1, JP_EC_TAG_DATA_WAY_SHIFT, scr1;			\
2367c478bdstevel@tonic-gate	set	((JP_ECACHE_MAX_SIZE / JP_ECACHE_NWAY) - 1), scr2;	\
2377c478bdstevel@tonic-gate	and	afar, scr2, scr3;		/* get set offset */	\
2387c478bdstevel@tonic-gate	andn	scr3, (JP_ECACHE_MAX_LSIZE - 1), scr3; /* VA<5:0>=0 */	\
2397c478bdstevel@tonic-gate	or	scr3, scr1, scr3;		/* or WAY bits */	\
2407c478bdstevel@tonic-gate	b	1f;							\
2417c478bdstevel@tonic-gate	  stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
2427c478bdstevel@tonic-gate	.align	64;							\
2437c478bdstevel@tonic-gate1:									\
2447c478bdstevel@tonic-gate	JP_EC_DIAG_ACCESS_MEMBAR;					\
2457c478bdstevel@tonic-gate	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
2467c478bdstevel@tonic-gate	JP_EC_DIAG_ACCESS_MEMBAR;					\
2477c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
2487c478bdstevel@tonic-gate	add	datap, CH_EC_DATA, datap;				\
2497c478bdstevel@tonic-gate2:									\
2507c478bdstevel@tonic-gate	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
2517c478bdstevel@tonic-gate	clr	scr1;							\
2527c478bdstevel@tonic-gate3:						/* loop thru 5 regs */	\
2537c478bdstevel@tonic-gate	ldxa	[scr1]ASI_EC_DATA, scr2;				\
2547c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;					\
2557c478bdstevel@tonic-gate	add	datap, 8, datap;					\
2567c478bdstevel@tonic-gate	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
2577c478bdstevel@tonic-gate	bne	3b;							\
2587c478bdstevel@tonic-gate	   add	scr1, 8, scr1;						\
2597c478bdstevel@tonic-gate	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
2607c478bdstevel@tonic-gate	beq	2b;							\
2617c478bdstevel@tonic-gate	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
2627c478bdstevel@tonic-gate
2637c478bdstevel@tonic-gate#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
2647c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
2657c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 1, scr1, scr2, scr3);		\
2667c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 2, scr1, scr2, scr3);		\
2677c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 3, scr1, scr2, scr3);		\
2687c478bdstevel@tonic-gate	add	datap, (CHD_EC_DATA_SETS-4)*CH_EC_DATA_SIZE, datap;	\
2697c478bdstevel@tonic-gate	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
2707c478bdstevel@tonic-gate
2717c478bdstevel@tonic-gate/*
2727c478bdstevel@tonic-gate * Jalapeno does not have cores so these macros are null.
2737c478bdstevel@tonic-gate */
2747c478bdstevel@tonic-gate#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
2757c478bdstevel@tonic-gate#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
2767c478bdstevel@tonic-gate
2777c478bdstevel@tonic-gate#if defined(JALAPENO)
2787c478bdstevel@tonic-gate/*
2797c478bdstevel@tonic-gate * Jalapeno gets primary AFSR and AFAR.  All bits in the AFSR except
2807c478bdstevel@tonic-gate * the fatal error bits are cleared.
2817c478bdstevel@tonic-gate *	datap:		pointer to cpu logout structure.
2827c478bdstevel@tonic-gate *	afar:		returned primary AFAR value.
2837c478bdstevel@tonic-gate *	scr1:		scratch
2847c478bdstevel@tonic-gate *	scr2:		scratch
2857c478bdstevel@tonic-gate */
2867c478bdstevel@tonic-gate#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
2877c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFAR, afar;					\
2887c478bdstevel@tonic-gate	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
2897c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFSR, scr2;					\
2907c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
2917c478bdstevel@tonic-gate	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
2927c478bdstevel@tonic-gate	sllx	scr1, 32, scr1;						\
2937c478bdstevel@tonic-gate	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
2947c478bdstevel@tonic-gate	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
2957c478bdstevel@tonic-gate	membar	#Sync
2967c478bdstevel@tonic-gate
2977c478bdstevel@tonic-gate/*
2987c478bdstevel@tonic-gate * Jalapeno has no shadow AFAR, null operation.
2997c478bdstevel@tonic-gate */
3007c478bdstevel@tonic-gate#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)
3017c478bdstevel@tonic-gate
3027c478bdstevel@tonic-gate#elif defined(SERRANO)
3037c478bdstevel@tonic-gate/*
3047c478bdstevel@tonic-gate * Serrano gets primary AFSR and AFAR.  All bits in the AFSR except
3057c478bdstevel@tonic-gate * the fatal error bits are cleared.  For Serrano, we also save the
3067c478bdstevel@tonic-gate * AFAR2 register.
3077c478bdstevel@tonic-gate *	datap:	pointer to cpu logout structure.
3087c478bdstevel@tonic-gate *	afar:	returned primary AFAR value.
3097c478bdstevel@tonic-gate *	scr1:	scratch
3107c478bdstevel@tonic-gate *	scr2:	scratch
3117c478bdstevel@tonic-gate */
3127c478bdstevel@tonic-gate#define GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
3137c478bdstevel@tonic-gate	set	ASI_MCU_AFAR2_VA, scr1;					\
3147c478bdstevel@tonic-gate	ldxa	[scr1]ASI_MCU_CTRL, afar;				\
3157c478bdstevel@tonic-gate	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR2)]%asi;	\
3167c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFAR, afar;					\
3177c478bdstevel@tonic-gate	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
3187c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFSR, scr2;					\
3197c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
3207c478bdstevel@tonic-gate	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
3217c478bdstevel@tonic-gate	sllx	scr1, 32, scr1;						\
3227c478bdstevel@tonic-gate	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
3237c478bdstevel@tonic-gate	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */ 	\
3247c478bdstevel@tonic-gate	membar	#Sync
3257c478bdstevel@tonic-gate
3267c478bdstevel@tonic-gate/*
3277c478bdstevel@tonic-gate * Serrano needs to capture E$, D$ and I$ lines associated with afar2.
3287c478bdstevel@tonic-gate *      afar:   scratch, holds afar2.
3297c478bdstevel@tonic-gate *      datap:  pointer to cpu logout structure
3307c478bdstevel@tonic-gate *      scr1:   scratch
3317c478bdstevel@tonic-gate *      scr2:   scratch
3327c478bdstevel@tonic-gate *      scr3:   scratch
3337c478bdstevel@tonic-gate */
3347c478bdstevel@tonic-gate#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)		\
3357c478bdstevel@tonic-gate	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR2)]%asi, afar;	\
3367c478bdstevel@tonic-gate	add	datap, CH_CLO_SDW_DATA + CH_CHD_EC_DATA, datap;		\
3377c478bdstevel@tonic-gate	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
3387c478bdstevel@tonic-gate	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
3397c478bdstevel@tonic-gate	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
3407c478bdstevel@tonic-gate	sub	datap, CH_CPU_LOGOUT_SIZE, datap
3417c478bdstevel@tonic-gate#endif /* SERRANO */
3427c478bdstevel@tonic-gate
3437c478bdstevel@tonic-gate#elif defined(CHEETAH_PLUS)
3447c478bdstevel@tonic-gate/*
3457c478bdstevel@tonic-gate * Macro version of get_ecache_dtag.  We use this macro in the
3467c478bdstevel@tonic-gate * CPU logout code.
3477c478bdstevel@tonic-gate *   afar:	input AFAR, not modified.
3487c478bdstevel@tonic-gate *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
3497c478bdstevel@tonic-gate *   pn_way:	ecache way for panther (value = 0-3). For non-panther
3507c478bdstevel@tonic-gate *		cpus, this macro will be called with pn_way = 0.
3517c478bdstevel@tonic-gate *   scr1:	Scratch.
3527c478bdstevel@tonic-gate *   scr2:	Scratch.
3537c478bdstevel@tonic-gate *   scr3:	Scratch.
3547c478bdstevel@tonic-gate */
3557c478bdstevel@tonic-gate#define	GET_ECACHE_DTAG(afar, datap, pn_way, scr1, scr2, scr3)		\
3567c478bdstevel@tonic-gate	mov	afar, scr3;						\
3577c478bdstevel@tonic-gate	andn	scr3, (CH_ECACHE_SUBBLK_SIZE - 1), scr3; /* VA<5:0>=0 */\
3587c478bdstevel@tonic-gate	set	(CH_ECACHE_8M_SIZE - 1), scr2;				\
3597c478bdstevel@tonic-gate	and	scr3, scr2, scr3;		/* VA<63:23>=0 */	\
3607c478bdstevel@tonic-gate	mov	pn_way, scr1;	/* panther L3$ is 4-way so we ...    */	\
3617c478bdstevel@tonic-gate	sllx	scr1, PN_L3_WAY_SHIFT, scr1;	/* need to mask...   */	\
3627c478bdstevel@tonic-gate	or	scr3, scr1, scr3;	/* in the way bits <24:23>.  */	\
3637c478bdstevel@tonic-gate	b	1f;							\
3647c478bdstevel@tonic-gate	   stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
3657c478bdstevel@tonic-gate	.align	64;							\
3667c478bdstevel@tonic-gate1:									\
3677c478bdstevel@tonic-gate	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
3687c478bdstevel@tonic-gate	stxa     scr1, [datap + CH_EC_TAG]%asi;				\
3697c478bdstevel@tonic-gate	set	CHP_ECACHE_IDX_TAG_ECC, scr1;				\
3707c478bdstevel@tonic-gate	or	scr3, scr1, scr1;					\
3717c478bdstevel@tonic-gate	ldxa    [scr1]ASI_EC_DIAG, scr1;	/* get E$ tag ECC */	\
3727c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_EC_TAG_ECC]%asi;			\
3737c478bdstevel@tonic-gate	add	datap, CH_EC_DATA, datap;				\
3747c478bdstevel@tonic-gate2:									\
3757c478bdstevel@tonic-gate	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
3767c478bdstevel@tonic-gate	clr	scr1;							\
3777c478bdstevel@tonic-gate3:						/* loop thru 5 regs */	\
3787c478bdstevel@tonic-gate	ldxa	[scr1]ASI_EC_DATA, scr2;				\
3797c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;					\
3807c478bdstevel@tonic-gate	add	datap, 8, datap;					\
3817c478bdstevel@tonic-gate	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
3827c478bdstevel@tonic-gate	bne	3b;							\
3837c478bdstevel@tonic-gate	   add	scr1, 8, scr1;						\
3847c478bdstevel@tonic-gate	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
3857c478bdstevel@tonic-gate	beq	2b;							\
3867c478bdstevel@tonic-gate	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
3877c478bdstevel@tonic-gate
3887c478bdstevel@tonic-gate/*
3897c478bdstevel@tonic-gate * If this is a panther, we need to make sure the sibling core is
3907c478bdstevel@tonic-gate * parked so that we avoid any race conditions during diagnostic
3917c478bdstevel@tonic-gate * accesses to the shared L2 and L3 caches.
3927c478bdstevel@tonic-gate * dcucr_reg:	This register will be used to keep track of whether
3937c478bdstevel@tonic-gate *		or not we need to unpark the core later.
3947c478bdstevel@tonic-gate *		It just so happens that we also use this same register
3957c478bdstevel@tonic-gate *		to keep track of our saved DCUCR value so we only touch
3967c478bdstevel@tonic-gate *		bit 4 of the register (which is a "reserved" bit in the
3977c478bdstevel@tonic-gate *		DCUCR) for keeping track of core parking.
3987c478bdstevel@tonic-gate * scr1:	Scratch register.
3997c478bdstevel@tonic-gate * scr2:	Scratch register.
4007c478bdstevel@tonic-gate */
4017c478bdstevel@tonic-gate#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)			\
4027c478bdstevel@tonic-gate	GET_CPU_IMPL(scr1);						\
4037c478bdstevel@tonic-gate	cmp	scr1, PANTHER_IMPL;	/* only park for panthers */	\
4047c478bdstevel@tonic-gate	bne,a	%xcc, 2f;						\
4057c478bdstevel@tonic-gate	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
4067c478bdstevel@tonic-gate	set	ASI_CORE_RUNNING_STATUS, scr1;	/* check other core */	\
4077c478bdstevel@tonic-gate	ldxa	[scr1]ASI_CMP_SHARED, scr2;	/* is it running?   */	\
4087c478bdstevel@tonic-gate	cmp	scr2, PN_BOTH_CORES_RUNNING;				\
4097c478bdstevel@tonic-gate	bne,a	%xcc, 2f;	/* if not running, we are done */	\
4107c478bdstevel@tonic-gate	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
4117c478bdstevel@tonic-gate	or	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
4127c478bdstevel@tonic-gate	set	ASI_CORE_ID, scr1;					\
4137c478bdstevel@tonic-gate	ldxa	[scr1]ASI_CMP_PER_CORE, scr2;				\
4147c478bdstevel@tonic-gate	and	scr2, COREID_MASK, scr2;				\
4157c478bdstevel@tonic-gate	or	%g0, 1, scr1;		/* find out which core... */	\
4167c478bdstevel@tonic-gate	sll	scr1, scr2, scr2;	/* ... we need to park... */	\
4177c478bdstevel@tonic-gate1:									\
4187c478bdstevel@tonic-gate	set	ASI_CORE_RUNNING_RW, scr1;				\
419ed05dc5vb	ldxa    [scr1]ASI_CMP_SHARED, scr1;	/* ...but are we? */	\
420ed05dc5vb	btst    scr1, scr2;        /* check our own parked status */	\
421ed05dc5vb	bz      %xcc, 1b;        /* if we are then go round again */	\
422ed05dc5vb	nop;								\
423ed05dc5vb	set	ASI_CORE_RUNNING_RW, scr1;	/* else proceed... */	\
4247c478bdstevel@tonic-gate	stxa	scr2, [scr1]ASI_CMP_SHARED;	/* ... and park it. */	\
42599d4e82cv	membar	#Sync;							\
42699d4e82cv	set	ASI_CORE_RUNNING_STATUS, scr1;	/* spin until... */	\
4277c478bdstevel@tonic-gate	ldxa	[scr1]ASI_CMP_SHARED, scr1;	/* ... the other...  */	\
4287c478bdstevel@tonic-gate	cmp	scr1, scr2;	/* ...core is parked according to... */	\
4297c478bdstevel@tonic-gate	bne,a	%xcc, 1b;	/* ...the core running status reg.  */	\
4307c478bdstevel@tonic-gate	  nop;								\
4317c478bdstevel@tonic-gate2:
4327c478bdstevel@tonic-gate
4337c478bdstevel@tonic-gate/*
4347c478bdstevel@tonic-gate * The core running this code will unpark its sibling core if the
4357c478bdstevel@tonic-gate * sibling core had been parked by the current core earlier in this
4367c478bdstevel@tonic-gate * trap handler.
4377c478bdstevel@tonic-gate * dcucr_reg:	This register is used to keep track of whether or not
4387c478bdstevel@tonic-gate *		we need to unpark our sibling core.
4397c478bdstevel@tonic-gate *		It just so happens that we also use this same register
4407c478bdstevel@tonic-gate *		to keep track of our saved DCUCR value so we only touch
4417c478bdstevel@tonic-gate *		bit 4 of the register (which is a "reserved" bit in the
4427c478bdstevel@tonic-gate *		DCUCR) for keeping track of core parking.
4437c478bdstevel@tonic-gate * scr1:	Scratch register.
4447c478bdstevel@tonic-gate * scr2:	Scratch register.
4457c478bdstevel@tonic-gate */
4467c478bdstevel@tonic-gate#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)			\
4477c478bdstevel@tonic-gate	btst	PN_PARKED_OTHER_CORE, dcucr_reg;			\
4487c478bdstevel@tonic-gate	bz,pt	%xcc, 1f;	/* if nothing to unpark, we are done */	\
4497c478bdstevel@tonic-gate	  andn	dcucr_reg, PN_PARKED_OTHER_CORE, dcucr_reg;		\
4507c478bdstevel@tonic-gate	set	ASI_CORE_RUNNING_RW, scr1;				\
4517c478bdstevel@tonic-gate	set	PN_BOTH_CORES_RUNNING, scr2;	/* we want both...   */	\
4527c478bdstevel@tonic-gate	stxa	scr2, [scr1]ASI_CMP_SHARED;	/* ...cores running. */	\
4537c478bdstevel@tonic-gate	membar	#Sync;							\
4547c478bdstevel@tonic-gate1:
4557c478bdstevel@tonic-gate
4567c478bdstevel@tonic-gate/*
4577c478bdstevel@tonic-gate * Cheetah+ and Jaguar get both primary and secondary AFSR/AFAR.  All bits
4587c478bdstevel@tonic-gate * in the primary AFSR are cleared except the fatal error bits.  For Panther,
4597c478bdstevel@tonic-gate * we also have to read and clear the AFSR_EXT, again leaving the fatal
4607c478bdstevel@tonic-gate * error bits alone.
4617c478bdstevel@tonic-gate *	datap:		pointer to cpu logout structure.
4627c478bdstevel@tonic-gate *	afar:		returned primary AFAR value.
4637c478bdstevel@tonic-gate *	scr1:		scratch
4647c478bdstevel@tonic-gate *	scr2:		scratch
4657c478bdstevel@tonic-gate */
4667c478bdstevel@tonic-gate#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)				\
4677c478bdstevel@tonic-gate	set	ASI_SHADOW_REG_VA, scr1;				\
4687c478bdstevel@tonic-gate	ldxa	[scr1]ASI_AFAR, scr2;					\
4697c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFAR)]%asi;	\
4707c478bdstevel@tonic-gate	ldxa	[scr1]ASI_AFSR, scr2;					\
4717c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFSR)]%asi;	\
4727c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFAR, afar;					\
4737c478bdstevel@tonic-gate	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
4747c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFSR, scr2;					\
4757c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
4767c478bdstevel@tonic-gate	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
4777c478bdstevel@tonic-gate	sllx	scr1, 32, scr1;						\
4787c478bdstevel@tonic-gate	bclr	scr1, scr2;	/* Clear fatal error bits here, so */ 	\
4797c478bdstevel@tonic-gate	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
4807c478bdstevel@tonic-gate	membar	#Sync;							\
4817c478bdstevel@tonic-gate	GET_CPU_IMPL(scr1);						\
4827c478bdstevel@tonic-gate	cmp	scr1, PANTHER_IMPL;					\
4837c478bdstevel@tonic-gate	bne	%xcc, 1f;						\
4847c478bdstevel@tonic-gate	   nop;								\
4857c478bdstevel@tonic-gate	set	ASI_SHADOW_AFSR_EXT_VA, scr1;	/* shadow AFSR_EXT */	\
4867c478bdstevel@tonic-gate	ldxa	[scr1]ASI_AFSR, scr2;					\
4877c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_SDW_DATA + CH_CHD_AFSR_EXT)]%asi; \
4887c478bdstevel@tonic-gate	set	ASI_AFSR_EXT_VA, scr1;		/* primary AFSR_EXT */	\
4897c478bdstevel@tonic-gate	ldxa	[scr1]ASI_AFSR, scr2;					\
4907c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR_EXT)]%asi;	\
4917c478bdstevel@tonic-gate	set	C_AFSR_EXT_FATAL_ERRS, scr1;				\
4927c478bdstevel@tonic-gate	bclr	scr1, scr2;	/* Clear fatal error bits here, */	\
4937c478bdstevel@tonic-gate	set	ASI_AFSR_EXT_VA, scr1;	/* so they're left */		\
4947c478bdstevel@tonic-gate	stxa	scr2, [scr1]ASI_AFSR;	/* as is in AFSR_EXT */		\
4957c478bdstevel@tonic-gate	membar	#Sync;							\
4967c478bdstevel@tonic-gate1:
4977c478bdstevel@tonic-gate
4987c478bdstevel@tonic-gate/*
4997c478bdstevel@tonic-gate * This macro is used in the CPU logout code to capture diagnostic
5007c478bdstevel@tonic-gate * information from the L2 cache on panther processors.
5017c478bdstevel@tonic-gate *   afar:	input AFAR, not modified.
5027c478bdstevel@tonic-gate *   datap:	Ptr to pn_l2_data_t, at end pts just past pn_l2_data_t.
5037c478bdstevel@tonic-gate *   scr1:	Scratch.
5047c478bdstevel@tonic-gate *   scr2:	Scratch.
5057c478bdstevel@tonic-gate *   scr3:	Scratch.
5067c478bdstevel@tonic-gate */
5077c478bdstevel@tonic-gate#define	GET_PN_L2_CACHE_DTAGS(afar, datap, scr1, scr2, scr3)		\
5087c478bdstevel@tonic-gate	mov	afar, scr3;						\
5097c478bdstevel@tonic-gate	set	PN_L2_INDEX_MASK, scr1;					\
5107c478bdstevel@tonic-gate	and	scr3, scr1, scr3;					\
5117c478bdstevel@tonic-gate	b	1f;	/* code to read tags and data should be ...  */	\
5127c478bdstevel@tonic-gate	   nop;		/* ...on the same cache line if possible.    */	\
5137c478bdstevel@tonic-gate	.align	128;	/* update this line if you add lines below. */	\
5147c478bdstevel@tonic-gate1:									\
5157c478bdstevel@tonic-gate	stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store L2$ index  */	\
5167c478bdstevel@tonic-gate	ldxa	[scr3]ASI_L2_TAG, scr1;		/* read the L2$ tag */	\
5177c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
5187c478bdstevel@tonic-gate	add	datap, CH_EC_DATA, datap;				\
5197c478bdstevel@tonic-gate	clr	scr1;							\
5207c478bdstevel@tonic-gate2:									\
5217c478bdstevel@tonic-gate	ldxa	[scr3 + scr1]ASI_L2_DATA, scr2;	/* loop through     */	\
5227c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;		/* <511:256> of L2  */	\
5237c478bdstevel@tonic-gate	add	datap, 8, datap;		/* data and record  */	\
5247c478bdstevel@tonic-gate	cmp	scr1, (PN_L2_LINESIZE / 2) - 8;	/* it in the cpu    */	\
5257c478bdstevel@tonic-gate	bne	2b;				/* logout struct.   */	\
5267c478bdstevel@tonic-gate	  add	scr1, 8, scr1;						\
5277c478bdstevel@tonic-gate	set	PN_L2_DATA_ECC_SEL, scr2;	/* ECC_sel bit.     */	\
5287c478bdstevel@tonic-gate	ldxa	[scr3 + scr2]ASI_L2_DATA, scr2;	/* Read and record  */	\
5297c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;		/* ecc of <511:256> */	\
5307c478bdstevel@tonic-gate	add	datap, 8, datap;					\
5317c478bdstevel@tonic-gate3:									\
5327c478bdstevel@tonic-gate	ldxa	[scr3 + scr1]ASI_L2_DATA, scr2;	/* loop through     */	\
5337c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;		/* <255:0> of L2    */	\
5347c478bdstevel@tonic-gate	add	datap, 8, datap;		/* data and record  */	\
5357c478bdstevel@tonic-gate	cmp	scr1, PN_L2_LINESIZE - 8;	/* it in the cpu    */	\
5367c478bdstevel@tonic-gate	bne	3b;				/* logout struct.   */	\
5377c478bdstevel@tonic-gate	  add	scr1, 8, scr1;						\
5387c478bdstevel@tonic-gate	set	PN_L2_DATA_ECC_SEL, scr2;	/* ECC_sel bit.     */	\
5397c478bdstevel@tonic-gate	add	scr2, PN_L2_ECC_LO_REG, scr2;				\
5407c478bdstevel@tonic-gate	ldxa	[scr3 + scr2]ASI_L2_DATA, scr2;	/* Read and record  */	\
5417c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;		/* ecc of <255:0>.  */	\
5427c478bdstevel@tonic-gate	add	datap, 8, datap;		/* Advance pointer  */	\
5437c478bdstevel@tonic-gate	set	PN_L2_SET_SIZE, scr2;					\
5447c478bdstevel@tonic-gate	set	PN_L2_MAX_SET, scr1;					\
5457c478bdstevel@tonic-gate	cmp	scr1, scr3;	/* more ways to try for this line? */	\
5467c478bdstevel@tonic-gate	bg,a	%xcc, 1b;	/* if so, start over with next way */	\
5477c478bdstevel@tonic-gate	  add	scr3, scr2, scr3
5487c478bdstevel@tonic-gate
5497c478bdstevel@tonic-gate/*
5507c478bdstevel@tonic-gate * Cheetah+ assumes E$ is 2-way and grabs both E$ lines associated with afar.
5517c478bdstevel@tonic-gate *	afar:	AFAR from access.
5527c478bdstevel@tonic-gate *	datap:	pointer to cpu logout structure.
5537c478bdstevel@tonic-gate *	scr1:	scratch
5547c478bdstevel@tonic-gate *	scr2:	scratch
5557c478bdstevel@tonic-gate *	scr3:	scratch
5567c478bdstevel@tonic-gate */
5577c478bdstevel@tonic-gate#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
5587c478bdstevel@tonic-gate	GET_CPU_IMPL(scr1);						\
5597c478bdstevel@tonic-gate	cmp	scr1, PANTHER_IMPL;					\
5607c478bdstevel@tonic-gate	bne	%xcc, 4f;						\
5617c478bdstevel@tonic-gate	  nop;								\
5627c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
5637c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 1, scr1, scr2, scr3);		\
5647c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 2, scr1, scr2, scr3);		\
5657c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 3, scr1, scr2, scr3);		\
5667c478bdstevel@tonic-gate	add	datap, (CHD_EC_DATA_SETS-4)*CH_EC_DATA_SIZE, datap;	\
5677c478bdstevel@tonic-gate	GET_PN_L2_CACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
5687c478bdstevel@tonic-gate	b	5f;							\
5697c478bdstevel@tonic-gate	  nop;								\
5707c478bdstevel@tonic-gate4:									\
5717c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
5727c478bdstevel@tonic-gate	GET_ECACHE_WAY_BIT(scr1, scr2);					\
5737c478bdstevel@tonic-gate	xor	afar, scr1, afar;					\
5747c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, 0, scr1, scr2, scr3);		\
5757c478bdstevel@tonic-gate	GET_ECACHE_WAY_BIT(scr1, scr2);		/* restore AFAR */	\
5767c478bdstevel@tonic-gate	xor	afar, scr1, afar;					\
5777c478bdstevel@tonic-gate	add	datap, (CHD_EC_DATA_SETS-2)*CH_EC_DATA_SIZE, datap;	\
5787c478bdstevel@tonic-gate	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
5797c478bdstevel@tonic-gate5:
5807c478bdstevel@tonic-gate
5817c478bdstevel@tonic-gate/*
5827c478bdstevel@tonic-gate * Cheetah+ needs to capture E$, D$ and I$ lines associated with
5837c478bdstevel@tonic-gate * shadow afar.
5847c478bdstevel@tonic-gate *	afar:	scratch, holds shadow afar.
5857c478bdstevel@tonic-gate *	datap:	pointer to cpu logout structure
5867c478bdstevel@tonic-gate *	scr1:	scratch
5877c478bdstevel@tonic-gate *	scr2:	scratch
5887c478bdstevel@tonic-gate *	scr3:	scratch
5897c478bdstevel@tonic-gate */
5907c478bdstevel@tonic-gate#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)		\
5917c478bdstevel@tonic-gate	ldxa	[datap + (CH_CLO_SDW_DATA + CH_CHD_AFAR)]%asi, afar;	\
5927c478bdstevel@tonic-gate	add	datap, CH_CLO_SDW_DATA + CH_CHD_EC_DATA, datap;	\
5937c478bdstevel@tonic-gate	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
5947c478bdstevel@tonic-gate	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
5957c478bdstevel@tonic-gate	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
5967c478bdstevel@tonic-gate	sub	datap, CH_CPU_LOGOUT_SIZE, datap
5977c478bdstevel@tonic-gate
5987c478bdstevel@tonic-gate/*
5997c478bdstevel@tonic-gate * Compute the "Way" bit for 2-way Ecache for Cheetah+.
6007c478bdstevel@tonic-gate */
6017c478bdstevel@tonic-gate#define	GET_ECACHE_WAY_BIT(scr1, scr2)					\
6027c478bdstevel@tonic-gate	CPU_INDEX(scr1, scr2);						\
6037c478bdstevel@tonic-gate	mulx	scr1, CPU_NODE_SIZE, scr1;				\
6047c478bdstevel@tonic-gate	add	scr1, ECACHE_SIZE, scr1;				\
6057c478bdstevel@tonic-gate	set	cpunodes, scr2;						\
6067c478bdstevel@tonic-gate	ld	[scr1 + scr2], scr1;					\
6077c478bdstevel@tonic-gate	srlx	scr1, 1, scr1
6087c478bdstevel@tonic-gate
6097c478bdstevel@tonic-gate#else /* CHEETAH_PLUS */
6107c478bdstevel@tonic-gate/*
6117c478bdstevel@tonic-gate * Macro version of get_ecache_dtag.  We use this macro in the
6127c478bdstevel@tonic-gate * CPU logout code.
6137c478bdstevel@tonic-gate *   afar:	input AFAR, not modified.
6147c478bdstevel@tonic-gate *   datap:	Ptr to ch_ec_data_t, at end pts just past ch_ec_data_t.
6157c478bdstevel@tonic-gate *   scr1:      Scratch.
6167c478bdstevel@tonic-gate *   scr2:	Scratch.
6177c478bdstevel@tonic-gate *   scr3:	Scratch.
6187c478bdstevel@tonic-gate */
6197c478bdstevel@tonic-gate#define	GET_ECACHE_DTAG(afar, datap, scr1, scr2, scr3)			\
6207c478bdstevel@tonic-gate	mov	afar, scr3;						\
6217c478bdstevel@tonic-gate	andn	scr3, (CH_ECACHE_SUBBLK_SIZE - 1), scr3; /* VA<5:0>=0 */\
6227c478bdstevel@tonic-gate	set	(CH_ECACHE_8M_SIZE - 1), scr2;				\
6237c478bdstevel@tonic-gate	and	scr3, scr2, scr3;		/* VA<63:23>=0 */	\
6247c478bdstevel@tonic-gate	b	1f;							\
6257c478bdstevel@tonic-gate	   stxa	scr3, [datap + CH_EC_IDX]%asi;	/* store E$ index */	\
6267c478bdstevel@tonic-gate	.align	64;							\
6277c478bdstevel@tonic-gate1:									\
6287c478bdstevel@tonic-gate	ldxa    [scr3]ASI_EC_DIAG, scr1;	/* get E$ tag */	\
6297c478bdstevel@tonic-gate	stxa	scr1, [datap + CH_EC_TAG]%asi;				\
6307c478bdstevel@tonic-gate	add	datap, CH_EC_DATA, datap;				\
6317c478bdstevel@tonic-gate2:									\
6327c478bdstevel@tonic-gate	ldxa	[scr3]ASI_EC_R, %g0;		/* ld E$ stging regs */	\
6337c478bdstevel@tonic-gate	clr	scr1;							\
6347c478bdstevel@tonic-gate3:						/* loop thru 5 regs */	\
6357c478bdstevel@tonic-gate	ldxa	[scr1]ASI_EC_DATA, scr2;				\
6367c478bdstevel@tonic-gate	stxa	scr2, [datap]%asi;					\
6377c478bdstevel@tonic-gate	add	datap, 8, datap;					\
6387c478bdstevel@tonic-gate	cmp	scr1, CH_ECACHE_STGREG_TOTALSIZE - 8;			\
6397c478bdstevel@tonic-gate	bne	3b;							\
6407c478bdstevel@tonic-gate	   add	scr1, 8, scr1;						\
6417c478bdstevel@tonic-gate	btst	CH_ECACHE_STGREG_SIZE, scr3;	/* done? */		\
6427c478bdstevel@tonic-gate	beq	2b;							\
6437c478bdstevel@tonic-gate	   add	scr3, CH_ECACHE_STGREG_SIZE, scr3
6447c478bdstevel@tonic-gate
6457c478bdstevel@tonic-gate/*
6467c478bdstevel@tonic-gate * Cheetah does not have cores so these macros are null.
6477c478bdstevel@tonic-gate */
6487c478bdstevel@tonic-gate#define	PARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
6497c478bdstevel@tonic-gate#define	UNPARK_SIBLING_CORE(dcucr_reg, scr1, scr2)
6507c478bdstevel@tonic-gate
6517c478bdstevel@tonic-gate/*
6527c478bdstevel@tonic-gate * Cheetah gets primary AFSR and AFAR and clears the AFSR, except for the
6537c478bdstevel@tonic-gate * fatal error bits.
6547c478bdstevel@tonic-gate *	datap:		pointer to cpu logout structure.
6557c478bdstevel@tonic-gate *	afar:		returned primary AFAR value.
6567c478bdstevel@tonic-gate *	scr1:		scratch
6577c478bdstevel@tonic-gate *	scr2:		scratch
6587c478bdstevel@tonic-gate */
6597c478bdstevel@tonic-gate#define	GET_AFSR_AFAR(datap, afar, scr1, scr2)	\
6607c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFAR, afar;					\
6617c478bdstevel@tonic-gate	stxa	afar, [datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi;	\
6627c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFSR, scr2;					\
6637c478bdstevel@tonic-gate	stxa	scr2, [datap + (CH_CLO_DATA + CH_CHD_AFSR)]%asi;	\
6647c478bdstevel@tonic-gate	sethi	%hh(C_AFSR_FATAL_ERRS), scr1;				\
6657c478bdstevel@tonic-gate	sllx	scr1, 32, scr1;						\
6667c478bdstevel@tonic-gate	bclr	scr1, scr2;	/* Clear fatal error bits here, so */	\
6677c478bdstevel@tonic-gate	stxa	scr2, [%g0]ASI_AFSR; /* they're left as is in AFSR */	\
6687c478bdstevel@tonic-gate	membar	#Sync
6697c478bdstevel@tonic-gate
6707c478bdstevel@tonic-gate/*
6717c478bdstevel@tonic-gate * Cheetah E$ is direct-mapped, so we grab line data and skip second line.
6727c478bdstevel@tonic-gate *	afar:	AFAR from access.
6737c478bdstevel@tonic-gate *	datap:	pointer to cpu logout structure.
6747c478bdstevel@tonic-gate *	scr1:	scratch
6757c478bdstevel@tonic-gate *	scr2:	scratch
6767c478bdstevel@tonic-gate *	scr3:	scratch
6777c478bdstevel@tonic-gate */
6787c478bdstevel@tonic-gate#define	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3)			\
6797c478bdstevel@tonic-gate	GET_ECACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
6807c478bdstevel@tonic-gate	add	datap, (CHD_EC_DATA_SETS-1)*CH_EC_DATA_SIZE, datap;	\
6817c478bdstevel@tonic-gate	add	datap, CH_EC_DATA_SIZE * PN_L2_NWAYS, datap;		\
6827c478bdstevel@tonic-gate
6837c478bdstevel@tonic-gate/*
6847c478bdstevel@tonic-gate * Cheetah has no shadow AFAR, null operation.
6857c478bdstevel@tonic-gate */
6867c478bdstevel@tonic-gate#define	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3)
6877c478bdstevel@tonic-gate
6887c478bdstevel@tonic-gate#endif	/* CHEETAH_PLUS */
6897c478bdstevel@tonic-gate
6907c478bdstevel@tonic-gate/*
6917c478bdstevel@tonic-gate * Cheetah/(Cheetah+ Jaguar Panther)/Jalapeno Macro for capturing CPU
6927c478bdstevel@tonic-gate * logout data at TL>0. r_val is a register that returns the "failure count"
6937c478bdstevel@tonic-gate * to the caller, and may be used as a scratch register until the end of
6947c478bdstevel@tonic-gate * the macro.  afar is used to return the primary AFAR value to the caller
6957c478bdstevel@tonic-gate * and it too can be used as a scratch register until the end. r_or_s is
6967c478bdstevel@tonic-gate * a reg or symbol that has the offset within the "cpu_private" data area
6977c478bdstevel@tonic-gate * to deposit the logout data.  t_flags is a register that has the
6987c478bdstevel@tonic-gate * trap-type/trap-level/CEEN info. This t_flags register may be used after
6997c478bdstevel@tonic-gate * the GET_AFSR_AFAR macro.
7007c478bdstevel@tonic-gate *
7017c478bdstevel@tonic-gate * The CPU logout operation will fail (r_val > 0) if the logout
7027c478bdstevel@tonic-gate * structure in question is already being used. Otherwise, the CPU
7037c478bdstevel@tonic-gate * logout operation will succeed (r_val = 0). For failures, r_val
7047c478bdstevel@tonic-gate * returns the busy count (# of times we tried using this CPU logout
7057c478bdstevel@tonic-gate * structure when it was busy.)
7067c478bdstevel@tonic-gate *
7077c478bdstevel@tonic-gate *   Register usage:
7087c478bdstevel@tonic-gate *	%asi:   Must be set to either ASI_MEM if the address in datap
7097c478bdstevel@tonic-gate *		is a physical address or to ASI_N if the address in
7107c478bdstevel@tonic-gate *		datap is a virtual address.
7117c478bdstevel@tonic-gate *	r_val:	This register is the return value which tells the
7127c478bdstevel@tonic-gate *		caller whether or not the LOGOUT operation was successful.
7137c478bdstevel@tonic-gate *		For failures, r_val returns the fail count (i.e. number of
7147c478bdstevel@tonic-gate *		times we have tried to use this logout structure when it was
7157c478bdstevel@tonic-gate *		already being used.
7167c478bdstevel@tonic-gate *	afar:	output: contains AFAR on exit
7177c478bdstevel@tonic-gate *	t_flags: input trap type info, may be used as scratch after stored
7187c478bdstevel@tonic-gate *		to cpu log out structure.
7197c478bdstevel@tonic-gate *	datap:	Points to log out data area.
7207c478bdstevel@tonic-gate *	scr1:	Scratch
7217c478bdstevel@tonic-gate *	scr2:	Scratch (may be r_val)
7227c478bdstevel@tonic-gate *	scr3:   Scratch (may be t_flags)
7237c478bdstevel@tonic-gate */
7247c478bdstevel@tonic-gate#define	DO_TL1_CPU_LOGOUT(r_val, afar, t_flags, datap, scr1, scr2, scr3) \
7257c478bdstevel@tonic-gate	setx	LOGOUT_INVALID, scr2, scr1;				\
7267c478bdstevel@tonic-gate	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi, scr2;	\
7277c478bdstevel@tonic-gate	cmp	scr2, scr1;						\
7287c478bdstevel@tonic-gate	bne	8f;							\
7297c478bdstevel@tonic-gate	  nop;								\
7307c478bdstevel@tonic-gate	stxa	t_flags, [datap + CH_CLO_FLAGS]%asi;			\
7317c478bdstevel@tonic-gate	GET_AFSR_AFAR(datap, afar, scr1, scr2);				\
7327c478bdstevel@tonic-gate	add	datap, CH_CLO_DATA + CH_CHD_EC_DATA, datap;		\
7337c478bdstevel@tonic-gate	GET_ECACHE_DTAGS(afar, datap, scr1, scr2, scr3);		\
7347c478bdstevel@tonic-gate	GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
7357c478bdstevel@tonic-gate	GET_ICACHE_DTAG(afar, datap, scr1, scr2, scr3);			\
7367c478bdstevel@tonic-gate	sub	datap, CH_CLO_DATA + CH_DIAG_DATA_SIZE, datap;		\
7377c478bdstevel@tonic-gate	GET_SHADOW_DATA(afar, datap, scr1, scr2, scr3);			\
7387c478bdstevel@tonic-gate	ldxa	[datap + (CH_CLO_DATA + CH_CHD_AFAR)]%asi, afar;	\
7397c478bdstevel@tonic-gate	set	0, r_val;	/* return value for success */		\
7407c478bdstevel@tonic-gate	ba	9f;							\
7417c478bdstevel@tonic-gate	  nop;								\
7427c478bdstevel@tonic-gate8:									\
7437c478bdstevel@tonic-gate	ldxa	[%g0]ASI_AFAR, afar;					\
7447c478bdstevel@tonic-gate	ldxa	[datap + CH_CLO_NEST_CNT]%asi, r_val;			\
7457c478bdstevel@tonic-gate	inc	r_val;		/* return value for failure */		\
7467c478bdstevel@tonic-gate	stxa	r_val, [datap + CH_CLO_NEST_CNT]%asi;			\
7477c478bdstevel@tonic-gate	membar	#Sync;							\
7487c478bdstevel@tonic-gate9:
7497c478bdstevel@tonic-gate
7507c478bdstevel@tonic-gate/*
7517c478bdstevel@tonic-gate * Cheetah/(Cheetah+ Jaguar Panther)/Jalapeno Macro for capturing CPU
7527c478bdstevel@tonic-gate * logout data.  Uses DO_TL1_CPU_LOGOUT macro defined above, and sets
7537c478bdstevel@tonic-gate * up the expected data pointer in the scr1 register and sets the %asi
7547c478bdstevel@tonic-gate * register to ASI_N for kernel virtual addresses instead of ASI_MEM as
7557c478bdstevel@tonic-gate * is used at TL>0.
7567c478bdstevel@tonic-gate *
7577c478bdstevel@tonic-gate * The CPU logout operation will fail (r_val > 0) if the logout
7587c478bdstevel@tonic-gate * structure in question is already being used. Otherwise, the CPU
7597c478bdstevel@tonic-gate * logout operation will succeed (r_val = 0). For failures, r_val
7607c478bdstevel@tonic-gate * returns the busy count (# of times we tried using this CPU logout
7617c478bdstevel@tonic-gate * structure when it was busy.)
7627c478bdstevel@tonic-gate *
7637c478bdstevel@tonic-gate *   Register usage:
7647c478bdstevel@tonic-gate *	r_val:	This register is the return value which tells the
7657c478bdstevel@tonic-gate *		caller whether or not the LOGOUT operation was successful.
7667c478bdstevel@tonic-gate *		For failures, r_val returns the fail count (i.e. number of
7677c478bdstevel@tonic-gate *		times we have tried to use this logout structure when it was
7687c478bdstevel@tonic-gate *		already being used.
7697c478bdstevel@tonic-gate *	afar:	returns AFAR, used internally as afar value.
7707c478bdstevel@tonic-gate *		output: if the cpu_private struct has not been initialized,
7717c478bdstevel@tonic-gate *		        then we return the t_flags value listed below.
7727c478bdstevel@tonic-gate *	r_or_s:	input offset, either register or constant (symbol).  It's
7737c478bdstevel@tonic-gate *		OK for r_or_s to be a register as long as it's not scr1 or
7747c478bdstevel@tonic-gate *		scr3.
7757c478bdstevel@tonic-gate *	t_flags: input trap type info, may be used as scratch after stored
7767c478bdstevel@tonic-gate *		to cpu log out structure.
7777c478bdstevel@tonic-gate *	scr1:	Scratch, points to log out data area.
7787c478bdstevel@tonic-gate *	scr2:	Scratch (may be r_or_s)
7797c478bdstevel@tonic-gate *	scr3:	Scratch (may be r_val)
7807c478bdstevel@tonic-gate *	scr4:   Scratch (may be t_flags)
7817c478bdstevel@tonic-gate */
7827c478bdstevel@tonic-gate#define	DO_CPU_LOGOUT(r_val, afar, r_or_s, t_flags, scr1, scr2, scr3, scr4) \
7837c478bdstevel@tonic-gate	GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr3, 7f); /* can't use scr2/4 */ \
7847c478bdstevel@tonic-gate	wr	%g0, ASI_N, %asi;					\
7857c478bdstevel@tonic-gate	DO_TL1_CPU_LOGOUT(r_val, afar, t_flags, scr1, scr2, scr3, scr4)	\
7867c478bdstevel@tonic-gate	ba	6f;							\
7877c478bdstevel@tonic-gate	  nop;								\
7887c478bdstevel@tonic-gate7:									\
7897c478bdstevel@tonic-gate	mov	t_flags, afar;		/* depends on afar = %g2  */	\
7907c478bdstevel@tonic-gate	set	0, r_val;		/* success in this case.  */	\
7917c478bdstevel@tonic-gate6:
7927c478bdstevel@tonic-gate
7937c478bdstevel@tonic-gate/*
7947c478bdstevel@tonic-gate * The P$ is flushed as a side effect of writing to the Primary
7957c478bdstevel@tonic-gate * or Secondary Context Register. After writing to a context
7967c478bdstevel@tonic-gate * register, every line of the P$ in the Valid state is invalidated,
7977c478bdstevel@tonic-gate * regardless of which context it belongs to.
7987c478bdstevel@tonic-gate * This routine simply touches the Primary context register by
7997c478bdstevel@tonic-gate * reading the current value and writing it back. The Primary
8007c478bdstevel@tonic-gate * context is not changed.
8017c478bdstevel@tonic-gate */
8027c478bdstevel@tonic-gate#define	PCACHE_FLUSHALL(tmp1, tmp2, tmp3)				\
8037c478bdstevel@tonic-gate	sethi	%hi(FLUSH_ADDR), tmp1					;\
8047c478bdstevel@tonic-gate	set	MMU_PCONTEXT, tmp2					;\
8057c478bdstevel@tonic-gate	ldxa	[tmp2]ASI_DMMU, tmp3					;\
8067c478bdstevel@tonic-gate	stxa	tmp3, [tmp2]ASI_DMMU					;\
8077c478bdstevel@tonic-gate	flush	tmp1	/* See Cheetah PRM 8.10.2 */
8087c478bdstevel@tonic-gate
8097c478bdstevel@tonic-gate/*
8107c478bdstevel@tonic-gate * Macro that flushes the entire Dcache.
8117c478bdstevel@tonic-gate *
8127c478bdstevel@tonic-gate * arg1 = dcache size
8137c478bdstevel@tonic-gate * arg2 = dcache linesize
8147c478bdstevel@tonic-gate */
8157c478bdstevel@tonic-gate#define	CH_DCACHE_FLUSHALL(arg1, arg2, tmp1)				\
8167c478bdstevel@tonic-gate	sub	arg1, arg2, tmp1;					\
8177c478bdstevel@tonic-gate1:									\
8187c478bdstevel@tonic-gate	stxa	%g0, [tmp1]ASI_DC_TAG;					\
8197c478bdstevel@tonic-gate	membar	#Sync;							\
8207c478bdstevel@tonic-gate	cmp	%g0, tmp1;						\
8217c478bdstevel@tonic-gate	bne,pt	%icc, 1b;						\
8227c478bdstevel@tonic-gate	  sub	tmp1, arg2, tmp1;
8237c478bdstevel@tonic-gate
8247c478bdstevel@tonic-gate/*
8257c478bdstevel@tonic-gate * Macro that flushes the entire Icache.
8267c478bdstevel@tonic-gate *
8277c478bdstevel@tonic-gate * Note that we cannot access ASI 0x67 (ASI_IC_TAG) with the Icache on,
8287c478bdstevel@tonic-gate * because accesses to ASI 0x67 interfere with Icache coherency.  We
8297c478bdstevel@tonic-gate * must make sure the Icache is off, then turn it back on after the entire
8307c478bdstevel@tonic-gate * cache has been invalidated.  If the Icache is originally off, we'll just
8317c478bdstevel@tonic-gate * clear the tags but not turn the Icache on.
8327c478bdstevel@tonic-gate *
8337c478bdstevel@tonic-gate * arg1 = icache size
8347c478bdstevel@tonic-gate * arg2 = icache linesize
8357c478bdstevel@tonic-gate */
8367c478bdstevel@tonic-gate#define	CH_ICACHE_FLUSHALL(arg1, arg2, tmp1, tmp2)			\
8377c478bdstevel@tonic-gate	ldxa	[%g0]ASI_DCU, tmp2;					\
8387c478bdstevel@tonic-gate	andn	tmp2, DCU_IC, tmp1;					\
8397c478bdstevel@tonic-gate	stxa	tmp1, [%g0]ASI_DCU;					\
8407c478bdstevel@tonic-gate	flush	%g0;	/* flush required after changing the IC bit */	\
8417c478bdstevel@tonic-gate	sllx	arg2, 1, arg2;		/* arg2 = linesize * 2 */	\
8427c478bdstevel@tonic-gate	sllx	arg1, 1, arg1;		/* arg1 = size * 2 */		\
8437c478bdstevel@tonic-gate	sub	arg1, arg2, arg1;					\
8447c478bdstevel@tonic-gate	or	arg1, CH_ICTAG_LOWER, arg1;	/* "write" tag */	\
8457c478bdstevel@tonic-gate1:									\
8467c478bdstevel@tonic-gate	stxa	%g0, [arg1]ASI_IC_TAG;					\
8477c478bdstevel@tonic-gate	membar	#Sync;				/* Cheetah PRM 8.9.3 */	\
8487c478bdstevel@tonic-gate	cmp	arg1, CH_ICTAG_LOWER;					\
8497c478bdstevel@tonic-gate	bne,pt	%icc, 1b;						\
8507c478bdstevel@tonic-gate	  sub	arg1, arg2, arg1;					\
8517c478bdstevel@tonic-gate	stxa	tmp2, [%g0]ASI_DCU;					\
8527c478bdstevel@tonic-gate	flush	%g0;	/* flush required after changing the IC bit */
8537c478bdstevel@tonic-gate
8547c478bdstevel@tonic-gate
8557c478bdstevel@tonic-gate#if defined(JALAPENO) || defined(SERRANO)
8567c478bdstevel@tonic-gate
8577c478bdstevel@tonic-gate/*
8587c478bdstevel@tonic-gate * ASI access to the L2 tag or L2 flush can hang the cpu when interacting
8597c478bdstevel@tonic-gate * with combinations of L2 snoops, victims and stores.
8607c478bdstevel@tonic-gate *
8617c478bdstevel@tonic-gate * A possible workaround is to surround each L2 ASI access with membars
8627c478bdstevel@tonic-gate * and make sure that the code is hitting in the Icache.  This requires
8637c478bdstevel@tonic-gate * aligning code sequence at E$ boundary and forcing I$ fetch by
8647c478bdstevel@tonic-gate * jumping to selected offsets so that we don't take any I$ misses
8657c478bdstevel@tonic-gate * during ASI access to the L2 tag or L2 flush.  This also requires
8667c478bdstevel@tonic-gate * making sure that we don't take any interrupts or traps (such as
8677c478bdstevel@tonic-gate * fast ECC trap, I$/D$ tag parity error) which can result in eviction
8687c478bdstevel@tonic-gate * of this code sequence from I$, thus causing a miss.
8697c478bdstevel@tonic-gate *
8707c478bdstevel@tonic-gate * Because of the complexity/risk, we have decided to do a partial fix
8717c478bdstevel@tonic-gate * of adding membar around each ASI access to the L2 tag or L2 flush.
8727c478bdstevel@tonic-gate */
8737c478bdstevel@tonic-gate
8747c478bdstevel@tonic-gate#define	JP_EC_DIAG_ACCESS_MEMBAR	\
8757c478bdstevel@tonic-gate	membar	#Sync
8767c478bdstevel@tonic-gate
8777c478bdstevel@tonic-gate/*
8787c478bdstevel@tonic-gate * Jalapeno version of macro that flushes the entire Ecache.
8797c478bdstevel@tonic-gate *
8807c478bdstevel@tonic-gate * Uses Jalapeno displacement flush feature of ASI_EC_DIAG.
8817c478bdstevel@tonic-gate *
8827c478bdstevel@tonic-gate * arg1 = ecache size
8837c478bdstevel@tonic-gate * arg2 = ecache linesize - not modified; can be an immediate constant.
8847c478bdstevel@tonic-gate */
8857c478bdstevel@tonic-gate#define	ECACHE_FLUSHALL(arg1, arg2, tmp1, tmp2)	\
8867c478bdstevel@tonic-gate	CPU_INDEX(tmp1, tmp2);						\
8877c478bdstevel@tonic-gate	set	JP_ECACHE_IDX_DISP_FLUSH, tmp2;				\
8887c478bdstevel@tonic-gate	sllx	tmp1, JP_ECFLUSH_PORTID_SHIFT, tmp1;			\
8897c478bdstevel@tonic-gate	or	tmp1, tmp2, tmp1;					\
8907c478bdstevel@tonic-gate	srlx	arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2;			\
8917c478bdstevel@tonic-gate1:									\
8927c478bdstevel@tonic-gate	subcc	tmp2, arg2, tmp2;					\
8937c478bdstevel@tonic-gate	JP_EC_DIAG_ACCESS_MEMBAR;					\
8947c478bdstevel@tonic-gate	ldxa	[tmp1 + tmp2]ASI_EC_DIAG, %g0;				\
8957c478bdstevel@tonic-gate	JP_EC_DIAG_ACCESS_MEMBAR;					\
8967c478bdstevel@tonic-gate	bg,pt	%xcc, 1b;						\
8977c478bdstevel@tonic-gate	  nop;								\
8987c478bdstevel@tonic-gate	mov	1, tmp2;						\
8997c478bdstevel@tonic-gate	sllx	tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2;			\
9007c478bdstevel@tonic-gate	add	tmp1, tmp2, tmp1;					\
9017c478bdstevel@tonic-gate	mov	(JP_ECACHE_NWAY-1), tmp2;				\
9027c478bdstevel@tonic-gate	sllx	tmp2, JP_ECFLUSH_EC_WAY_SHIFT, tmp2;			\
9037c478bdstevel@tonic-gate	andcc	tmp1, tmp2, tmp2;					\
9047c478bdstevel@tonic-gate	bnz,pt	%xcc, 1b;						\
9057c478bdstevel@tonic-gate	  srlx	arg1, JP_EC_TO_SET_SIZE_SHIFT, tmp2
9067c478bdstevel@tonic-gate
9077c478bdstevel@tonic-gate#else	/* JALAPENO || SERRANO */
9087c478bdstevel@tonic-gate
9097c478bdstevel@tonic-gate/*
9107c478bdstevel@tonic-gate * Cheetah version of macro that flushes the entire Ecache.
9117c478bdstevel@tonic-gate *
9127c478bdstevel@tonic-gate *  Need to displacement flush 2x ecache size from Ecache flush area.
9137c478bdstevel@tonic-gate *
9147c478bdstevel@tonic-gate * arg1 = ecache size
9157c478bdstevel@tonic-gate * arg2 = ecache linesize
9167c478bdstevel@tonic-gate * arg3 = ecache flush address - for cheetah only
9177c478bdstevel@tonic-gate */
9187c478bdstevel@tonic-gate#define	CH_ECACHE_FLUSHALL(arg1, arg2, arg3)				\
9197c478bdstevel@tonic-gate	sllx	arg1, 1, arg1;						\
9207c478bdstevel@tonic-gate1:									\
9217c478bdstevel@tonic-gate	subcc	arg1, arg2, arg1;					\
9227c478bdstevel@tonic-gate	bg,pt	%xcc, 1b;						\
9237c478bdstevel@tonic-gate	  ldxa	[arg1 + arg3]ASI_MEM, %g0;
9247c478bdstevel@tonic-gate
9257c478bdstevel@tonic-gate/*
9267c478bdstevel@tonic-gate * Cheetah+ version of macro that flushes the entire Ecache.
9277c478bdstevel@tonic-gate *
9287c478bdstevel@tonic-gate * Uses the displacement flush feature.
9297c478bdstevel@tonic-gate *
9307c478bdstevel@tonic-gate * arg1 = ecache size
9317c478bdstevel@tonic-gate * arg2 = ecache linesize
9327c478bdstevel@tonic-gate * impl = CPU implementation as returned from GET_CPU_IMPL()
9337c478bdstevel@tonic-gate *        The value in this register is destroyed during execution
9347c478bdstevel@tonic-gate *        of the macro.
9357c478bdstevel@tonic-gate */
9367c478bdstevel@tonic-gate#if defined(CHEETAH_PLUS)
9377c478bdstevel@tonic-gate#define	CHP_ECACHE_FLUSHALL(arg1, arg2, impl)				\
9387c478bdstevel@tonic-gate	cmp	impl, PANTHER_IMPL;					\
9397c478bdstevel@tonic-gate	bne	%xcc, 1f;						\
9407c478bdstevel@tonic-gate	  nop;								\
9417c478bdstevel@tonic-gate	set	PN_L3_IDX_DISP_FLUSH, impl;				\
9427c478bdstevel@tonic-gate	b	2f;							\
9437c478bdstevel@tonic-gate	  nop;								\
9447c478bdstevel@tonic-gate1:									\
9457c478bdstevel@tonic-gate	set	CHP_ECACHE_IDX_DISP_FLUSH, impl;			\
9467c478bdstevel@tonic-gate2:									\
9477c478bdstevel@tonic-gate	subcc	arg1, arg2, arg1;					\
9487c478bdstevel@tonic-gate	bg,pt	%xcc, 2b;						\
9497c478bdstevel@tonic-gate	  ldxa	[arg1 + impl]ASI_EC_DIAG, %g0;
9507c478bdstevel@tonic-gate#else	/* CHEETAH_PLUS */
9517c478bdstevel@tonic-gate#define	CHP_ECACHE_FLUSHALL(arg1, arg2, impl)
9527c478bdstevel@tonic-gate#endif	/* CHEETAH_PLUS */
9537c478bdstevel@tonic-gate
9547c478bdstevel@tonic-gate/*
9557c478bdstevel@tonic-gate * Macro that flushes the entire Ecache.
9567c478bdstevel@tonic-gate *
9577c478bdstevel@tonic-gate * arg1 = ecache size
9587c478bdstevel@tonic-gate * arg2 = ecache linesize
9597c478bdstevel@tonic-gate * arg3 = ecache flush address - for cheetah only
9607c478bdstevel@tonic-gate */
9617c478bdstevel@tonic-gate#define	ECACHE_FLUSHALL(arg1, arg2, arg3, tmp1)				\
9627c478bdstevel@tonic-gate	GET_CPU_IMPL(tmp1);						\
9637c478bdstevel@tonic-gate	cmp	tmp1, CHEETAH_IMPL;					\
9647c478bdstevel@tonic-gate	bne	%xcc, 2f;						\
9657c478bdstevel@tonic-gate	  nop;								\
9667c478bdstevel@tonic-gate	CH_ECACHE_FLUSHALL(arg1, arg2, arg3);				\
9677c478bdstevel@tonic-gate	ba	3f;							\
9687c478bdstevel@tonic-gate	  nop;								\
9697c478bdstevel@tonic-gate2:									\
9707c478bdstevel@tonic-gate	CHP_ECACHE_FLUSHALL(arg1, arg2, tmp1);				\
9717c478bdstevel@tonic-gate3:
9727c478bdstevel@tonic-gate
9737c478bdstevel@tonic-gate#endif	/* JALAPENO || SERRANO */
9747c478bdstevel@tonic-gate
9757c478bdstevel@tonic-gate/*
9767c478bdstevel@tonic-gate * Macro that flushes the Panther L2 cache.
9777c478bdstevel@tonic-gate */
9787c478bdstevel@tonic-gate#if defined(CHEETAH_PLUS)
9797c478bdstevel@tonic-gate#define	PN_L2_FLUSHALL(scr1, scr2, scr3)				\
9807c478bdstevel@tonic-gate	GET_CPU_IMPL(scr3);						\
9817c478bdstevel@tonic-gate	cmp	scr3, PANTHER_IMPL;					\
9827c478bdstevel@tonic-gate	bne	%xcc, 2f;						\
9837c478bdstevel@tonic-gate	  nop;								\
9847c478bdstevel@tonic-gate	set	PN_L2_SIZE, scr1;					\
9857c478bdstevel@tonic-gate	set	PN_L2_LINESIZE, scr2;					\
9867c478bdstevel@tonic-gate	set	PN_L2_IDX_DISP_FLUSH, scr3;				\
9877c478bdstevel@tonic-gate1:									\
9887c478bdstevel@tonic-gate	subcc	scr1, scr2, scr1;					\
9897c478bdstevel@tonic-gate	bg,pt	%xcc, 1b;						\
9907c478bdstevel@tonic-gate	  ldxa	[scr1 + scr3]ASI_L2_TAG, %g0;				\
9917c478bdstevel@tonic-gate2:
9927c478bdstevel@tonic-gate#else	/* CHEETAH_PLUS */
9937c478bdstevel@tonic-gate#define	PN_L2_FLUSHALL(scr1, scr2, scr3)
9947c478bdstevel@tonic-gate#endif	/* CHEETAH_PLUS */
9957c478bdstevel@tonic-gate
9967c478bdstevel@tonic-gate/*
9977c478bdstevel@tonic-gate * Given a VA and page size (page size as encoded in ASI_MMU_TAG_ACCESS_EXT),
9987c478bdstevel@tonic-gate * this macro returns the TLB index for that mapping based on a 512 entry
9997c478bdstevel@tonic-gate * (2-way set associative) TLB. Aaside from the 16 entry fully associative
10007c478bdstevel@tonic-gate * TLBs, all TLBs in Panther are 512 entry, 2-way set associative.
10017c478bdstevel@tonic-gate *
10027c478bdstevel@tonic-gate * To find the index, we shift the VA right by 13 + (3 * pg_sz) and then
10037c478bdstevel@tonic-gate * mask out all but the lower 8 bits because:
10047c478bdstevel@tonic-gate *
10057c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 0 for   8K
10067c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 1 for  64K
10077c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 2 for 512K
10087c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 3 for   4M
10097c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 4 for  32M
10107c478bdstevel@tonic-gate *    ASI_[D|I]MMU_TAG_ACCESS_EXT.PgSz = 5 for 256M
10117c478bdstevel@tonic-gate *
10127c478bdstevel@tonic-gate * and
10137c478bdstevel@tonic-gate *
10147c478bdstevel@tonic-gate *    array index for   8K pages = VA[20:13]
10157c478bdstevel@tonic-gate *    array index for  64K pages = VA[23:16]
10167c478bdstevel@tonic-gate *    array index for 512K pages = VA[26:19]
10177c478bdstevel@tonic-gate *    array index for   4M pages = VA[29:22]
10187c478bdstevel@tonic-gate *    array index for  32M pages = VA[32:25]
10197c478bdstevel@tonic-gate *    array index for 256M pages = VA[35:28]
10207c478bdstevel@tonic-gate *
10217c478bdstevel@tonic-gate * Inputs:
10227c478bdstevel@tonic-gate *
10237c478bdstevel@tonic-gate *    va	- Register.
10247c478bdstevel@tonic-gate *		  Input: Virtual address in which we are interested.
10257c478bdstevel@tonic-gate *		  Output: TLB index value.
10267c478bdstevel@tonic-gate *    pg_sz	- Register. Page Size of the TLB in question as encoded
10277c478bdstevel@tonic-gate *		  in the ASI_[D|I]MMU_TAG_ACCESS_EXT register.
10287c478bdstevel@tonic-gate */
10297c478bdstevel@tonic-gate#if defined(CHEETAH_PLUS)
10307c478bdstevel@tonic-gate#define	PN_GET_TLB_INDEX(va, pg_sz)					\
10317c478bdstevel@tonic-gate	srlx	va, 13, va;	/* first shift the 13 bits and then */	\
10327c478bdstevel@tonic-gate	srlx	va, pg_sz, va;	/* shift by pg_sz three times. */	\
10337c478bdstevel@tonic-gate	srlx	va, pg_sz, va;						\
10347c478bdstevel@tonic-gate	srlx	va, pg_sz, va;						\
10357c478bdstevel@tonic-gate	and	va, 0xff, va;	/* mask out all but the lower 8 bits */
10367c478bdstevel@tonic-gate#endif	/* CHEETAH_PLUS */
10377c478bdstevel@tonic-gate
10387c478bdstevel@tonic-gate/*
10397c478bdstevel@tonic-gate * The following macros are for error traps at TL>0.
10407c478bdstevel@tonic-gate * The issue with error traps at TL>0 is that there are no safely
10417c478bdstevel@tonic-gate * available global registers.  So we use the trick of generating a
10427c478bdstevel@tonic-gate * software trap, then using the %tpc, %tnpc and %tstate registers to
10437c478bdstevel@tonic-gate * temporarily save the values of %g1 and %g2.
10447c478bdstevel@tonic-gate */
10457c478bdstevel@tonic-gate
10467c478bdstevel@tonic-gate/*
10477c478bdstevel@tonic-gate * Macro to generate 8-instruction trap table entry for TL>0 trap handlers.
10487c478bdstevel@tonic-gate * Does the following steps:
10497c478bdstevel@tonic-gate *	1. membar #Sync - required for USIII family errors.
10507c478bdstevel@tonic-gate *	2. Specified software trap.
10517c478bdstevel@tonic-gate * NB: Must be 8 instructions or less to fit in trap table and code must
10527c478bdstevel@tonic-gate *     be relocatable.
10537c478bdstevel@tonic-gate */
10547c478bdstevel@tonic-gate#define	CH_ERR_TL1_TRAPENTRY(trapno)		\
10557c478bdstevel@tonic-gate	membar	#Sync;				\
10567c478bdstevel@tonic-gate	ta	trapno;				\
10577c478bdstevel@tonic-gate	nop; nop; nop; nop; nop; nop
10587c478bdstevel@tonic-gate
10597c478bdstevel@tonic-gate/*
10607c478bdstevel@tonic-gate * Macro to generate 8-instruction trap table entry for TL>0 software trap.
10617c478bdstevel@tonic-gate * We save the values of %g1 and %g2 in %tpc, %tnpc and %tstate (since
10627c478bdstevel@tonic-gate * the low-order two bits of %tpc/%tnpc are reserved and read as zero,
10637c478bdstevel@tonic-gate * we need to put the low-order two bits of %g1 and %g2 in %tstate).
10647c478bdstevel@tonic-gate * Note that %tstate has a reserved hole from bits 3-7, so we put the
10657c478bdstevel@tonic-gate * low-order two bits of %g1 in bits 0-1 and the low-order two bits of
10667c478bdstevel@tonic-gate * %g2 in bits 10-11 (insuring bits 8-9 are zero for use by the D$/I$
10677c478bdstevel@tonic-gate * state bits).  Note that we must do a jmp instruction, since this
10687c478bdstevel@tonic-gate * is moved into the trap table entry.
10697c478bdstevel@tonic-gate * NB: Must be 8 instructions or less to fit in trap table and code must
10707c478bdstevel@tonic-gate *     be relocatable.
10717c478bdstevel@tonic-gate */
10727c478bdstevel@tonic-gate#define	CH_ERR_TL1_SWTRAPENTRY(label)		\
10737c478bdstevel@tonic-gate	wrpr	%g1, %tpc;			\
10747c478bdstevel@tonic-gate	and	%g1, 3, %g1;			\
10757c478bdstevel@tonic-gate	wrpr	%g2, %tnpc;			\
10767c478bdstevel@tonic-gate	sllx	%g2, CH_ERR_G2_TO_TSTATE_SHFT, %g2; \
10777c478bdstevel@tonic-gate	or	%g1, %g2, %g2;			\
10787c478bdstevel@tonic-gate	sethi	%hi(label), %g1;		\
10797c478bdstevel@tonic-gate	jmp	%g1+%lo(label);			\
10807c478bdstevel@tonic-gate	  wrpr	%g2, %tstate
10817c478bdstevel@tonic-gate
10827c478bdstevel@tonic-gate/*
10837c478bdstevel@tonic-gate * Macro to get ptr to ch_err_tl1_data.
10847c478bdstevel@tonic-gate * reg1 will either point to a physaddr with ASI_MEM in %asi OR it
10857c478bdstevel@tonic-gate * will point to a kernel nucleus virtual address with ASI_N in %asi.
10867c478bdstevel@tonic-gate * This allows us to:
10877c478bdstevel@tonic-gate *   1. Avoid getting MMU misses.  We may have gotten the original
10887c478bdstevel@tonic-gate *	Fast ECC error in an MMU handler and if we get an MMU trap
10897c478bdstevel@tonic-gate *	in the TL>0 handlers, we'll scribble on the MMU regs.
10907c478bdstevel@tonic-gate *   2. Allows us to use the same code in the TL>0 handlers whether
10917c478bdstevel@tonic-gate *	we're accessing kernel nucleus virtual addresses or physical
10927c478bdstevel@tonic-gate *	addresses.
10937c478bdstevel@tonic-gate * pseudo-code:
10947c478bdstevel@tonic-gate *	reg1 <- ch_err_tl1_paddrs[CPUID];
10957c478bdstevel@tonic-gate *	if (reg1 == NULL) {
10967c478bdstevel@tonic-gate *		reg1 <- &ch_err_tl1_data
10977c478bdstevel@tonic-gate *		%asi <- ASI_N
10987c478bdstevel@tonic-gate *	} else {
10997c478bdstevel@tonic-gate *		reg1 <- reg1 + offset +
11007c478bdstevel@tonic-gate *		    sizeof (ch_err_tl1_data) * (%tl - 3)
11017c478bdstevel@tonic-gate *		%asi <- ASI_MEM
11027c478bdstevel@tonic-gate *	}
11037c478bdstevel@tonic-gate */
11047c478bdstevel@tonic-gate#define	GET_CH_ERR_TL1_PTR(reg1, reg2, offset)	\
11057c478bdstevel@tonic-gate	CPU_INDEX(reg1, reg2);			\
11067c478bdstevel@tonic-gate	sllx	reg1, 3, reg1;			\
11077c478bdstevel@tonic-gate	set	ch_err_tl1_paddrs, reg2;	\
11087c478bdstevel@tonic-gate	ldx	[reg1+reg2], reg1;		\
11097c478bdstevel@tonic-gate	brnz	reg1, 1f;			\
11107c478bdstevel@tonic-gate	add	reg1, offset, reg1;		\
11117c478bdstevel@tonic-gate	set	ch_err_tl1_data, reg1;		\
11127c478bdstevel@tonic-gate	ba	2f;				\
11137c478bdstevel@tonic-gate	wr	%g0, ASI_N, %asi;		\
11147c478bdstevel@tonic-gate1:	rdpr	%tl, reg2;			\
11157c478bdstevel@tonic-gate	sub	reg2, 3, reg2;			\
11167c478bdstevel@tonic-gate	mulx	reg2, CH_ERR_TL1_DATA_SIZE, reg2;	\
11177c478bdstevel@tonic-gate	add	reg1, reg2, reg1;		\
11187c478bdstevel@tonic-gate	wr	%g0, ASI_MEM, %asi;		\
11197c478bdstevel@tonic-gate2:
11207c478bdstevel@tonic-gate
11217c478bdstevel@tonic-gate/*
11227c478bdstevel@tonic-gate * Macro to generate entry code for TL>0 error handlers.
11237c478bdstevel@tonic-gate * At the end of this macro, %g1 will point to the ch_err_tl1_data
11247c478bdstevel@tonic-gate * structure and %g2 will have the original flags in the ch_err_tl1_data
11257c478bdstevel@tonic-gate * structure and %g5 will have the value of %tstate where the Fast ECC
11267c478bdstevel@tonic-gate * routines will save the state of the D$ in Bit2 CH_ERR_TSTATE_DC_ON.
11277c478bdstevel@tonic-gate * All %g registers except for %g1, %g2 and %g5 will be available after
11287c478bdstevel@tonic-gate * this macro.
11297c478bdstevel@tonic-gate * Does the following steps:
11307c478bdstevel@tonic-gate *   1. Compute physical address of per-cpu/per-tl save area using
11317c478bdstevel@tonic-gate *	only %g1+%g2 (which we've saved in %tpc, %tnpc, %tstate)
11327c478bdstevel@tonic-gate *	leaving address in %g1 and updating the %asi register.
11337c478bdstevel@tonic-gate *	If there is no data area available, we branch to label.
11347c478bdstevel@tonic-gate *   2. Save %g3-%g7 in save area.
11357c478bdstevel@tonic-gate *   3. Save %tpc->%g3, %tnpc->%g4, %tstate->%g5, which contain
11367c478bdstevel@tonic-gate *	original %g1+%g2 values (because we're going to change %tl).
11377c478bdstevel@tonic-gate *   4. set %tl <- %tl - 1.  We do this ASAP to make window of
11387c478bdstevel@tonic-gate *	running at %tl+1 as small as possible.
11397c478bdstevel@tonic-gate *   5. Reconstitute %g1+%g2 from %tpc (%g3), %tnpc (%g4),
11407c478bdstevel@tonic-gate *	%tstate (%g5) and save in save area, carefully preserving %g5
11417c478bdstevel@tonic-gate *	because it has the CH_ERR_TSTATE_DC_ON value.
11427c478bdstevel@tonic-gate *   6. Load existing ch_err_tl1_data flags in %g2
11437c478bdstevel@tonic-gate *   7. Compute the new flags
11447c478bdstevel@tonic-gate *   8. If %g2 is non-zero (the structure was busy), shift the new
11457c478bdstevel@tonic-gate *	flags by CH_ERR_ME_SHIFT and or them with the old flags.
11467c478bdstevel@tonic-gate *   9. Store the updated flags into ch_err_tl1_data flags.
11477c478bdstevel@tonic-gate *   10. If %g2 is non-zero, read the %tpc and store it in
11487c478bdstevel@tonic-gate *	ch_err_tl1_data.
11497c478bdstevel@tonic-gate */
11507c478bdstevel@tonic-gate#define	CH_ERR_TL1_ENTER(flags)			\
11517c478bdstevel@tonic-gate	GET_CH_ERR_TL1_PTR(%g1, %g2, CHPR_TL1_ERR_DATA);	\
11527c478bdstevel@tonic-gate	stxa	%g3, [%g1 + CH_ERR_TL1_G3]%asi;	\
11537c478bdstevel@tonic-gate	stxa	%g4, [%g1 + CH_ERR_TL1_G4]%asi;	\
11547c478bdstevel@tonic-gate	stxa	%g5, [%g1 + CH_ERR_TL1_G5]%asi;	\
11557c478bdstevel@tonic-gate	stxa	%g6, [%g1 + CH_ERR_TL1_G6]%asi;	\
11567c478bdstevel@tonic-gate	stxa	%g7, [%g1 + CH_ERR_TL1_G7]%asi;	\
11577c478bdstevel@tonic-gate	rdpr	%tpc, %g3;			\
11587c478bdstevel@tonic-gate	rdpr	%tnpc, %g4;			\
11597c478bdstevel@tonic-gate	rdpr	%tstate, %g5;			\
11607c478bdstevel@tonic-gate	rdpr	%tl, %g6;			\
11617c478bdstevel@tonic-gate	sub	%g6, 1, %g6;			\
11627c478bdstevel@tonic-gate	wrpr	%g6, %tl;			\
11637c478bdstevel@tonic-gate	and	%g5, 3, %g6;			\
11647c478bdstevel@tonic-gate	andn	%g3, 3, %g3;			\
11657c478bdstevel@tonic-gate	or	%g3, %g6, %g3;			\
11667c478bdstevel@tonic-gate	stxa	%g3, [%g1 + CH_ERR_TL1_G1]%asi;	\
11677c478bdstevel@tonic-gate	srlx	%g5, CH_ERR_G2_TO_TSTATE_SHFT, %g6;	\
11687c478bdstevel@tonic-gate	and	%g6, 3, %g6;			\
11697c478bdstevel@tonic-gate	andn	%g4, 3, %g4;			\
11707c478bdstevel@tonic-gate	or	%g6, %g4, %g4;			\
11717c478bdstevel@tonic-gate	stxa	%g4, [%g1 + CH_ERR_TL1_G2]%asi;	\
11727c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_FLAGS]%asi, %g2;	\
11737c478bdstevel@tonic-gate	set	flags | CH_ERR_TL, %g3;		\
11747c478bdstevel@tonic-gate	brz	%g2, 9f;			\
11757c478bdstevel@tonic-gate	sllx	%g3, CH_ERR_ME_SHIFT, %g4;	\
11767c478bdstevel@tonic-gate	or	%g2, %g4, %g3;			\
11777c478bdstevel@tonic-gate9:	stxa	%g3, [%g1 + CH_ERR_TL1_FLAGS]%asi;	\
11787c478bdstevel@tonic-gate	brnz	%g2, 8f;			\
11797c478bdstevel@tonic-gate	rdpr	%tpc, %g4;			\
11807c478bdstevel@tonic-gate	stxa	%g4, [%g1 + CH_ERR_TL1_TPC]%asi;	\
11817c478bdstevel@tonic-gate8:
11827c478bdstevel@tonic-gate
11837c478bdstevel@tonic-gate/*
11847c478bdstevel@tonic-gate * Turns off D$/I$ and saves the state of DCU_DC+DCU_IC in %tstate Bits 8+9
11857c478bdstevel@tonic-gate * (CH_ERR_TSTATE_DC_ON/CH_ERR_TSTATE_IC_ON).  This is invoked on Fast ECC
11867c478bdstevel@tonic-gate * at TL>0 handlers because the D$ may have corrupted data and we need to
11877c478bdstevel@tonic-gate * turn off the I$ to allow for diagnostic accesses.  We then invoke
11887c478bdstevel@tonic-gate * the normal entry macro and after it is done we save the values of
11897c478bdstevel@tonic-gate * the original D$/I$ state, which is in %g5 bits CH_ERR_TSTATE_DC_ON/
11907c478bdstevel@tonic-gate * CH_ERR_TSTATE_IC_ON in ch_err_tl1_tmp.
11917c478bdstevel@tonic-gate */
11927c478bdstevel@tonic-gate#define	CH_ERR_TL1_FECC_ENTER			\
11937c478bdstevel@tonic-gate	ldxa	[%g0]ASI_DCU, %g1;		\
11947c478bdstevel@tonic-gate	andn	%g1, DCU_DC + DCU_IC, %g2;	\
11957c478bdstevel@tonic-gate	stxa	%g2, [%g0]ASI_DCU;		\
11967c478bdstevel@tonic-gate	flush	%g0;	/* DCU_IC need flush */	\
11977c478bdstevel@tonic-gate	rdpr	%tstate, %g2;			\
11987c478bdstevel@tonic-gate	and	%g1, DCU_DC + DCU_IC, %g1;	\
11997c478bdstevel@tonic-gate	sllx	%g1, CH_ERR_DCU_TO_TSTATE_SHFT, %g1;	\
12007c478bdstevel@tonic-gate	or	%g1, %g2, %g2;			\
12017c478bdstevel@tonic-gate	wrpr	%g2, %tstate;			\
12027c478bdstevel@tonic-gate	CH_ERR_TL1_ENTER(CH_ERR_FECC);		\
12037c478bdstevel@tonic-gate	and	%g5, CH_ERR_TSTATE_DC_ON + CH_ERR_TSTATE_IC_ON, %g5;	\
12047c478bdstevel@tonic-gate	stxa	%g5, [%g1 + CH_ERR_TL1_TMP]%asi
12057c478bdstevel@tonic-gate
12067c478bdstevel@tonic-gate/*
12077c478bdstevel@tonic-gate * Macro to generate exit code for TL>0 error handlers.
12087c478bdstevel@tonic-gate * We fall into this macro if we've successfully logged the error in
12097c478bdstevel@tonic-gate * the ch_err_tl1_data structure and want the PIL15 softint to pick
12107c478bdstevel@tonic-gate * it up and log it.
12117c478bdstevel@tonic-gate * Does the following steps:
12127c478bdstevel@tonic-gate *   1.	Set pending flag for this cpu in ch_err_tl1_pending.
12137c478bdstevel@tonic-gate *   2.	Write %set_softint with (1<<pil) to cause a pil level trap
12147c478bdstevel@tonic-gate *   3.	Restore registers from ch_err_tl1_data, which is pointed to
12157c478bdstevel@tonic-gate *	by %g1, last register to restore is %g1 since it's pointing
12167c478bdstevel@tonic-gate *	to the save area.
12177c478bdstevel@tonic-gate *   4. Execute retry
12187c478bdstevel@tonic-gate */
12197c478bdstevel@tonic-gate#define	CH_ERR_TL1_EXIT				\
12207c478bdstevel@tonic-gate	CPU_INDEX(%g2, %g3);			\
12217c478bdstevel@tonic-gate	set	ch_err_tl1_pending, %g3;	\
12227c478bdstevel@tonic-gate	set	-1, %g4;			\
12237c478bdstevel@tonic-gate	stb	%g4, [%g2 + %g3];		\
12247c478bdstevel@tonic-gate	mov	1, %g2;				\
12257c478bdstevel@tonic-gate	sll	%g2, PIL_15, %g2;		\
12267c478bdstevel@tonic-gate	wr	%g2, SET_SOFTINT;		\
12277c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G7]%asi, %g7;	\
12287c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G6]%asi, %g6;	\
12297c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G5]%asi, %g5;	\
12307c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G4]%asi, %g4;	\
12317c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G3]%asi, %g3;	\
12327c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G2]%asi, %g2;	\
12337c478bdstevel@tonic-gate	ldxa	[%g1 + CH_ERR_TL1_G1]%asi, %g1;	\
12347c478bdstevel@tonic-gate	retry
12357c478bdstevel@tonic-gate
12367c478bdstevel@tonic-gate/*
12377c478bdstevel@tonic-gate * Generates unrecoverable error label for TL>0 handlers.
12387c478bdstevel@tonic-gate * At label (Unrecoverable error routine)
12397c478bdstevel@tonic-gate *   1. Sets flags in ch_err_tl1_data and leaves in %g2 (first
12407c478bdstevel@tonic-gate *	argument to cpu_tl1_err_panic).
12417c478bdstevel@tonic-gate *   2.	Call cpu_tl1_err_panic via systrap at PIL 15
12427c478bdstevel@tonic-gate */
12437c478bdstevel@tonic-gate#define	CH_ERR_TL1_PANIC_EXIT(label)		\
12447c478bdstevel@tonic-gatelabel:	ldxa	[%g1 + CH_ERR_TL1_FLAGS]%asi, %g2;	\
12457c478bdstevel@tonic-gate	or	%g2, CH_ERR_TL | CH_ERR_PANIC, %g2;	\
12467c478bdstevel@tonic-gate	stxa	%g2, [%g1 + CH_ERR_TL1_FLAGS]%asi;	\
12477c478bdstevel@tonic-gate	set	cpu_tl1_err_panic, %g1;		\
12487c478bdstevel@tonic-gate	ba	sys_trap;			\
12497c478bdstevel@tonic-gate	  mov	PIL_15, %g4
12507c478bdstevel@tonic-gate
12517c478bdstevel@tonic-gate
12527c478bdstevel@tonic-gate
12537c478bdstevel@tonic-gate/* END CSTYLED */
12547c478bdstevel@tonic-gate#endif	/* _ASM */
12557c478bdstevel@tonic-gate
12567c478bdstevel@tonic-gate#ifdef	__cplusplus
12577c478bdstevel@tonic-gate}
12587c478bdstevel@tonic-gate#endif
12597c478bdstevel@tonic-gate
12607c478bdstevel@tonic-gate#endif /* _CHEETAHASM_H */
1261