129949e86Sstevel /* 229949e86Sstevel * CDDL HEADER START 329949e86Sstevel * 429949e86Sstevel * The contents of this file are subject to the terms of the 529949e86Sstevel * Common Development and Distribution License (the "License"). 629949e86Sstevel * You may not use this file except in compliance with the License. 729949e86Sstevel * 829949e86Sstevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 929949e86Sstevel * or http://www.opensolaris.org/os/licensing. 1029949e86Sstevel * See the License for the specific language governing permissions 1129949e86Sstevel * and limitations under the License. 1229949e86Sstevel * 1329949e86Sstevel * When distributing Covered Code, include this CDDL HEADER in each 1429949e86Sstevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1529949e86Sstevel * If applicable, add the following below this CDDL HEADER, with the 1629949e86Sstevel * fields enclosed by brackets "[]" replaced with your own identifying 1729949e86Sstevel * information: Portions Copyright [yyyy] [name of copyright owner] 1829949e86Sstevel * 1929949e86Sstevel * CDDL HEADER END 2029949e86Sstevel */ 2129949e86Sstevel 2229949e86Sstevel /* 2329949e86Sstevel * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 2429949e86Sstevel * Use is subject to license terms. 2529949e86Sstevel */ 2629949e86Sstevel 2729949e86Sstevel #ifndef _SYS_FHC_H 2829949e86Sstevel #define _SYS_FHC_H 2929949e86Sstevel 3029949e86Sstevel #ifdef __cplusplus 3129949e86Sstevel extern "C" { 3229949e86Sstevel #endif 3329949e86Sstevel 3429949e86Sstevel #include <sys/types32.h> 3529949e86Sstevel #include <sys/dditypes.h> 3629949e86Sstevel 3729949e86Sstevel /* useful debugging stuff */ 3829949e86Sstevel #define FHC_ATTACH_DEBUG 0x1 3929949e86Sstevel #define FHC_INTERRUPT_DEBUG 0x2 4029949e86Sstevel #define FHC_REGISTERS_DEBUG 0x4 4129949e86Sstevel #define FHC_CTLOPS_DEBUG 0x8 4229949e86Sstevel 4329949e86Sstevel #define FHC_BOARDS 0 4429949e86Sstevel #define FHC_CLOCKS 1 4529949e86Sstevel 4629949e86Sstevel /* 4729949e86Sstevel * OBP supplies us with 6 register sets for the FHC. The code for the fhc 4829949e86Sstevel * driver relies on these register sets being presented by the PROM in the 4929949e86Sstevel * order specified below. If this changes, the following comments must be 5029949e86Sstevel * revised and the code in fhc_init() must be changed to reflect these 5129949e86Sstevel * revisions. 5229949e86Sstevel * 5329949e86Sstevel * They are: 5429949e86Sstevel * 0 FHC internal registers 5529949e86Sstevel * 1 IGR Interrupt Group Number 5629949e86Sstevel * 2 FanFail IMR, ISMR 5729949e86Sstevel * 3 System IMR, ISMR 5829949e86Sstevel * 4 UART IMR, ISMR 5929949e86Sstevel * 5 TOD IMR, ISMR 6029949e86Sstevel */ 6129949e86Sstevel 6229949e86Sstevel /* 6329949e86Sstevel * The offsets are defined as offsets from the base of the OBP register 6429949e86Sstevel * set which the register belongs to. 6529949e86Sstevel */ 6629949e86Sstevel 6729949e86Sstevel /* Register set 0 */ 6829949e86Sstevel #define FHC_OFF_ID 0x0 /* FHC ID register */ 6929949e86Sstevel #define FHC_OFF_RCTRL 0x10 /* FHC Reset Control and Status */ 7029949e86Sstevel #define FHC_OFF_CTRL 0x20 /* FHC Control and Status */ 7129949e86Sstevel #define FHC_OFF_BSR 0x30 /* FHC Board Status Register */ 7229949e86Sstevel #define FHC_OFF_JTAG_CTRL 0xF0 /* JTAG Control Register */ 7329949e86Sstevel #define FHC_OFF_JTAG_CMD 0x100 /* JTAG Comamnd Register */ 7429949e86Sstevel 7529949e86Sstevel /* Register sets 2-5, the ISMR offset is the same */ 7629949e86Sstevel #define FHC_OFF_ISMR 0x10 /* FHC Interrupt State Machine */ 7729949e86Sstevel 7829949e86Sstevel /* Bit field defines for FHC Control and Status Register */ 7929949e86Sstevel #define FHC_CENTERDIS 0x00100000 8029949e86Sstevel 8129949e86Sstevel /* NOTE: this bit is only used by firmware and must always be cleared by OS */ 8229949e86Sstevel #define FHC_CSR_SYNC 0x00010000 8329949e86Sstevel #define FHC_MOD_OFF 0x00008000 8429949e86Sstevel #define FHC_ACDC_OFF 0x00004000 8529949e86Sstevel #define FHC_FHC_OFF 0x00002000 8629949e86Sstevel #define FHC_EPDA_OFF 0x00001000 8729949e86Sstevel #define FHC_EPDB_OFF 0x00000800 8829949e86Sstevel #define FHC_PS_OFF 0x00000400 8929949e86Sstevel #define FHC_NOT_BRD_PRES 0x00000200 9029949e86Sstevel #define FHC_LED_LEFT 0x00000040 9129949e86Sstevel #define FHC_LED_MID 0x00000020 9229949e86Sstevel #define FHC_LED_RIGHT 0x00000010 9329949e86Sstevel 9429949e86Sstevel /* Bit field defines for FHC Reset Control and Status Register */ 9529949e86Sstevel #define FHC_POR 0x80000000 9629949e86Sstevel #define FHC_SOFT_POR 0x40000000 9729949e86Sstevel #define FHC_SOFT_XIR 0x20000000 9829949e86Sstevel 9929949e86Sstevel /* Bit field defines for the JTAG control register. */ 10029949e86Sstevel #define JTAG_MASTER_EN 0x80000000 10129949e86Sstevel #define JTAG_MASTER_NPRES 0x40000000 10229949e86Sstevel 10329949e86Sstevel 10429949e86Sstevel /* Macros for decoding UPA speed pins from the Board Status Register */ 10529949e86Sstevel #define CPU_0_PINS(bsr) (((bsr) >> 10) & 0x7) 10629949e86Sstevel #define CPU_1_PINS(bsr) (((bsr) >> 7) & 0x7) 10729949e86Sstevel 10829949e86Sstevel #define CID_REV_MASK 0x0fffffff 10929949e86Sstevel #define ULTRAI_COMPID 0x0002502f 11029949e86Sstevel #define ULTRAII_COMPID 0x0003602f 11129949e86Sstevel 11229949e86Sstevel /* Macro for extracting the "plus" bit from the Board Status Register */ 11329949e86Sstevel #define ISPLUSBRD(bsr) (((bsr) & 1) == 0) 11429949e86Sstevel 11529949e86Sstevel /* Macros for physical access */ 11629949e86Sstevel #define FHC_OFFSET 0xf8000000ull 11729949e86Sstevel #define FHC_REGOFF 0x800000ull 11829949e86Sstevel #define FHC_OFF_IGN 0x2000ull 11929949e86Sstevel #define FHC_OFF_SIM 0x6000ull 12029949e86Sstevel #define FHC_OFF_SSM 0x6010ull 12129949e86Sstevel #define FHC_OFF_UIM 0x8000ull 12229949e86Sstevel #define FHC_OFF_USM 0x8010ull 12329949e86Sstevel #define FHC_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 12429949e86Sstevel FHC_REGOFF + FHC_OFF_CTRL) 12529949e86Sstevel #define FHC_JTAG_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 12629949e86Sstevel FHC_REGOFF + FHC_OFF_JTAG_CTRL) 12729949e86Sstevel #define FHC_IGN(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 12829949e86Sstevel FHC_REGOFF + FHC_OFF_IGN) 12929949e86Sstevel #define FHC_SIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 13029949e86Sstevel FHC_REGOFF + FHC_OFF_SIM) 13129949e86Sstevel #define FHC_SSM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 13229949e86Sstevel FHC_REGOFF + FHC_OFF_SSM) 13329949e86Sstevel #define FHC_UIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 13429949e86Sstevel FHC_REGOFF + FHC_OFF_UIM) 13529949e86Sstevel #define FHC_USM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 13629949e86Sstevel FHC_REGOFF + FHC_OFF_USM) 13729949e86Sstevel 13829949e86Sstevel /* 13929949e86Sstevel * the foolowing defines are used for trans phy-addr to board number 14029949e86Sstevel */ 14129949e86Sstevel #define BOARD_PHYADDR_SHIFT 24 14229949e86Sstevel #define CLOCKBOARD_PHYADDR_BITS 0x1fff8 14329949e86Sstevel #define IO_BOARD_NUMBER_SHIFT 10 14429949e86Sstevel #define IO_BOARD_NUMBER_MASK 0xf 14529949e86Sstevel 14629949e86Sstevel /* 14729949e86Sstevel * The following defines are used by the fhc driver to determine the 14829949e86Sstevel * difference between IO and CPU type boards. This will be replaced 14929949e86Sstevel * later by JTAG scan to determine board type. 15029949e86Sstevel */ 15129949e86Sstevel 15229949e86Sstevel /* XXX */ 15329949e86Sstevel #define FHC_UPADATA64A 0x40000 15429949e86Sstevel #define FHC_UPADATA64B 0x20000 15529949e86Sstevel /* XXX */ 15629949e86Sstevel 15729949e86Sstevel /* Bit field defines for Board Status Register */ 15829949e86Sstevel #define FHC_DIAG_MODE 0x40 15929949e86Sstevel 16029949e86Sstevel /* Bit field defines for the FHC Board Status Register when on a disk board */ 16129949e86Sstevel #define FHC_FANFAIL 0x00000040 16229949e86Sstevel #define FHC_SCSI_VDD_OK 0x00000001 16329949e86Sstevel 16429949e86Sstevel /* Size of temperature recording array */ 16529949e86Sstevel #define MAX_TEMP_HISTORY 16 16629949e86Sstevel 16729949e86Sstevel /* Maximum number of boards in system */ 16829949e86Sstevel #define MAX_BOARDS 16 16929949e86Sstevel 17029949e86Sstevel /* Maximum number of Board Power Supplies. */ 17129949e86Sstevel #define MAX_PS_COUNT 8 17229949e86Sstevel 17329949e86Sstevel /* Use predefined strings to name the kstats from this driver. */ 17429949e86Sstevel #define FHC_KSTAT_NAME "fhc" 17529949e86Sstevel #define CSR_KSTAT_NAMED "csr" 17629949e86Sstevel #define BSR_KSTAT_NAMED "bsr" 17729949e86Sstevel 17829949e86Sstevel /* 17929949e86Sstevel * The following defines are for the AC chip, but are needed to be global, 18029949e86Sstevel * so have been put in the fhc header file. 18129949e86Sstevel */ 18229949e86Sstevel 18329949e86Sstevel /* 18429949e86Sstevel * Most Sunfire ASICs have the chip rev encoded into bits 31-28 of the 18529949e86Sstevel * component ID register. 18629949e86Sstevel */ 18729949e86Sstevel #define CHIP_REV(c) ((c) >> 28) 18829949e86Sstevel 18929949e86Sstevel #ifndef _ASM 19029949e86Sstevel 19129949e86Sstevel /* Use predefined strings to name the kstats from this driver. */ 19229949e86Sstevel 19329949e86Sstevel /* Bit field defines for Interrupt Mapping registers */ 19429949e86Sstevel #define IMR_VALID ((uint_t)1 << INR_EN_SHIFT) /* Mondo valid bit */ 19529949e86Sstevel 19629949e86Sstevel /* Bit defines for Interrupt State Machine Register */ 19729949e86Sstevel #define INT_PENDING 3 /* state of the interrupt dispatch */ 19829949e86Sstevel 19929949e86Sstevel struct intr_regs { 20029949e86Sstevel volatile uint_t *mapping_reg; 20129949e86Sstevel volatile uint_t *clear_reg; 20229949e86Sstevel uint_t mapping_reg_cache; /* cache current value for CPR */ 20329949e86Sstevel }; 20429949e86Sstevel 20529949e86Sstevel #define BD_IVINTR_SHFT 0x7 20629949e86Sstevel 20729949e86Sstevel /* 20829949e86Sstevel * Convert the Board Number field in the FHC Board Status Register to 20929949e86Sstevel * a board number. The field in the register is bits 0,3-1 of the board 21029949e86Sstevel * number. Therefore a macro is necessary to extract the board number. 21129949e86Sstevel */ 21229949e86Sstevel #define FHC_BSR_TO_BD(bsr) ((((bsr) >> 16) & 0x1) | \ 21329949e86Sstevel (((bsr) >> 12) & 0xE)) 21429949e86Sstevel 21529949e86Sstevel #define FHC_INO(ino) ((ino) & 0x7) 21629949e86Sstevel #define FHC_CPU2BOARD(cpuid) ((cpuid) >> 1) 21729949e86Sstevel #define FHC_CPU_IS_A(cpuid) (!((cpuid) & 1)) 21829949e86Sstevel #define FHC_CPU_IS_B(cpuid) ((cpuid) & 1) 21929949e86Sstevel #define FHC_BOARD2CPU_A(board) ((board) << 1) 22029949e86Sstevel #define FHC_BOARD2CPU_B(board) (((board) << 1) + 1) 22129949e86Sstevel #define FHC_PS2BOARD(ps) ((((ps) & 0x6) << 1) | ((ps) & 0x1)) 22229949e86Sstevel #define FHC_BOARD2PS(board) ((((board) & 0xc) >> 1) | ((board) & 0x1)) 22329949e86Sstevel #define FHC_OTHER_CPU_ID(cpuid) ((cpuid) ^ 1) 22429949e86Sstevel 22529949e86Sstevel /* this base address is assumed to never map to real memory */ 22629949e86Sstevel #define FHC_BASE_NOMEM (1ull << 40) 22729949e86Sstevel #define FHC_MAX_ECACHE_SIZE (16 * 1024 * 1024) 22829949e86Sstevel 22929949e86Sstevel #define FHC_BOARD_0 0x1c000000000ull 23029949e86Sstevel #define FHC_BOARD_SPAN 0x200000000ull 23129949e86Sstevel #define FHC_DTAG_OFFSET 0xfa000000ull 23229949e86Sstevel #define FHC_BOARD_BASE(cpuid) (FHC_BOARD_0 + (cpuid) * FHC_BOARD_SPAN) 23329949e86Sstevel #define FHC_DTAG_BASE(cpuid) (FHC_BOARD_BASE(cpuid) + FHC_DTAG_OFFSET) 23429949e86Sstevel #define FHC_DTAG_LOW 0x300000000ull 23529949e86Sstevel #define FHC_DTAG_HIGH 0x3ull 23629949e86Sstevel #define FHC_DTAG_SIZE (16 * 1024 * 1024) 23729949e86Sstevel #define FHC_DTAG_SKIP 64 23829949e86Sstevel 23929949e86Sstevel /* 24029949e86Sstevel * Each Sunfire CPU Board has 32Kbytes of SRAM on the FireHose Bus. 24129949e86Sstevel * 24229949e86Sstevel * The SRAM is allocated as follows: 24329949e86Sstevel * 24429949e86Sstevel * 0x1ff.f020.0000 - 0x1ff.f020.5fff scratch/stacks 24529949e86Sstevel * 0x1ff.f020.6000 - 0x1ff.f020.67ff reset info (2K bytes) 24629949e86Sstevel * 0x1ff.f020.6800 - 0x1ff.f020.6fff POST private (2K bytes) 24729949e86Sstevel * 0x1ff.f020.7000 - 0x1ff.f020.77ff OS private (2K bytes) 24829949e86Sstevel * 0x1ff.f020.7800 - 0x1ff.f020.7fff OBP private (2K bytes) 24929949e86Sstevel */ 25029949e86Sstevel #define FHC_LOCAL_SRAM_BASE 0x1fff0200000ull 25129949e86Sstevel #define FHC_GLOBAL_SRAM_BASE 0x1c0f8200000ull 25229949e86Sstevel #define FHC_CPU2GLOBAL_SRAM(mid) \ 25329949e86Sstevel (FHC_GLOBAL_SRAM_BASE + (mid) * 0x200000000ull) 25429949e86Sstevel 25529949e86Sstevel #define FHC_SRAM_OS_BASE 0x7000 25629949e86Sstevel #define FHC_LOCAL_OS_PAGEBASE ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \ 25729949e86Sstevel MMU_PAGEMASK) 25829949e86Sstevel #define FHC_SRAM_OS_OFFSET ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \ 25929949e86Sstevel MMU_PAGEOFFSET) 26029949e86Sstevel 26129949e86Sstevel #define FHC_SHUTDOWN_WAIT_MSEC 1000 26229949e86Sstevel 26329949e86Sstevel #define FHC_MAX_INO 4 26429949e86Sstevel 26529949e86Sstevel #define FHC_SYS_INO 0x0 26629949e86Sstevel #define FHC_UART_INO 0x1 26729949e86Sstevel #define FHC_TOD_INO 0x2 26829949e86Sstevel #define FHC_FANFAIL_INO 0x3 26929949e86Sstevel 27029949e86Sstevel /* 27129949e86Sstevel * Defines for the kstats created for passing temperature values and 27229949e86Sstevel * history out to user level programs. All temperatures passed out 27329949e86Sstevel * will be in degrees Centigrade, corrected for the board type the 27429949e86Sstevel * temperature was read from. Since each Board type has a different 27529949e86Sstevel * response curve for the A/D convertor, the temperatures are all 27629949e86Sstevel * calibrated inside the kernel. 27729949e86Sstevel */ 27829949e86Sstevel 27929949e86Sstevel #define OVERTEMP_KSTAT_NAME "temperature" 28029949e86Sstevel 28129949e86Sstevel /* 28229949e86Sstevel * This kstat is used for manually overriding temperatures. 28329949e86Sstevel */ 28429949e86Sstevel 28529949e86Sstevel #define TEMP_OVERRIDE_KSTAT_NAME "temperature override" 28629949e86Sstevel 28729949e86Sstevel /* 28829949e86Sstevel * Time averaging based method of recording temperature history. 28929949e86Sstevel * Higher level temperature arrays are composed of temperature averages 29029949e86Sstevel * of the array one level below. When the lower array completes a 29129949e86Sstevel * set of data, the data is averaged and placed into the higher 29229949e86Sstevel * level array. Then the lower level array is overwritten until 29329949e86Sstevel * it is once again complete, where the process repeats. 29429949e86Sstevel * 29529949e86Sstevel * This method gives a user a fine grained view of the last minute, 29629949e86Sstevel * and larger grained views of the temperature as one goes back in 29729949e86Sstevel * time. 29829949e86Sstevel * 29929949e86Sstevel * The time units for the longer samples are based on the value 30029949e86Sstevel * of the OVERTEMP_TIMEOUT_SEC and the number of elements in each 30129949e86Sstevel * of the arrays between level 1 and the higher level. 30229949e86Sstevel */ 30329949e86Sstevel 30429949e86Sstevel #define OVERTEMP_TIMEOUT_SEC 2 30529949e86Sstevel 30629949e86Sstevel /* definition of the clock board index */ 30729949e86Sstevel #define CLOCK_BOARD_INDEX 16 30829949e86Sstevel 30929949e86Sstevel #define L1_SZ 30 /* # of OVERTEMP_TIMEOUT_SEC samples */ 31029949e86Sstevel #define L2_SZ 15 /* size of array for level 2 samples */ 31129949e86Sstevel #define L3_SZ 12 /* size of array for level 3 samples */ 31229949e86Sstevel #define L4_SZ 4 /* size of array for level 4 samples */ 31329949e86Sstevel #define L5_SZ 2 /* size of array for level 5 samples */ 31429949e86Sstevel 31529949e86Sstevel /* 31629949e86Sstevel * Macros for determining when to do the temperature averaging of arrays. 31729949e86Sstevel */ 31829949e86Sstevel #define L2_INDEX(i) ((i) / L1_SZ) 31929949e86Sstevel #define L2_REM(i) ((i) % L1_SZ) 32029949e86Sstevel #define L3_INDEX(i) ((i) / (L1_SZ * L2_SZ)) 32129949e86Sstevel #define L3_REM(i) ((i) % (L1_SZ * L2_SZ)) 32229949e86Sstevel #define L4_INDEX(i) ((i) / (L1_SZ * L2_SZ * L3_SZ)) 32329949e86Sstevel #define L4_REM(i) ((i) % (L1_SZ * L2_SZ * L3_SZ)) 32429949e86Sstevel #define L5_INDEX(i) ((i) / (L1_SZ * L2_SZ * L3_SZ * L4_SZ)) 32529949e86Sstevel #define L5_REM(i) ((i) % (L1_SZ * L2_SZ * L3_SZ * L4_SZ)) 32629949e86Sstevel 32729949e86Sstevel /* 32829949e86Sstevel * define for an illegal temperature. This temperature will never be seen 32929949e86Sstevel * in a real system, so it is used as an illegal value in the various 33029949e86Sstevel * functions processing the temperature data structure. 33129949e86Sstevel */ 33229949e86Sstevel #define NA_TEMP 0x7FFF 33329949e86Sstevel 33429949e86Sstevel /* 33529949e86Sstevel * State variable for board temperature. Each board has its own 33629949e86Sstevel * temperature state. State transitions from OK -> bad direction 33729949e86Sstevel * happen instantaneously, but use a counter in the opposite 33829949e86Sstevel * direction, so that noise in the A/D counters does not cause 33929949e86Sstevel * a large number of messages to appear. 34029949e86Sstevel */ 34129949e86Sstevel enum temp_state { TEMP_OK = 0, /* normal board temperature */ 34229949e86Sstevel TEMP_WARN = 1, /* start warning operator */ 34329949e86Sstevel TEMP_DANGER = 2 }; /* get ready to shutdown */ 34429949e86Sstevel 34529949e86Sstevel /* 34629949e86Sstevel * Number of temperature poll counts to wait before printing that the 34729949e86Sstevel * system has cooled down. 34829949e86Sstevel */ 34929949e86Sstevel #define TEMP_STATE_TIMEOUT_SEC 20 35029949e86Sstevel #define TEMP_STATE_COUNT ((TEMP_STATE_TIMEOUT_SEC) / \ 35129949e86Sstevel (OVERTEMP_TIMEOUT_SEC)) 35229949e86Sstevel 35329949e86Sstevel /* 35429949e86Sstevel * Number of poll counts that a system temperature must be at or above danger 35529949e86Sstevel * temperature before system is halted and powers down. 35629949e86Sstevel */ 35729949e86Sstevel #define SHUTDOWN_TIMEOUT_SEC 20 35829949e86Sstevel #define SHUTDOWN_COUNT ((SHUTDOWN_TIMEOUT_SEC) / \ 35929949e86Sstevel (OVERTEMP_TIMEOUT_SEC)) 36029949e86Sstevel 36129949e86Sstevel /* 36229949e86Sstevel * State variable for temperature trend. Each state represents the 36329949e86Sstevel * current temperature trend for a given device. 36429949e86Sstevel */ 36529949e86Sstevel enum temp_trend { TREND_UNKNOWN = 0, /* Unknown temperature trend */ 36629949e86Sstevel TREND_RAPID_FALL = 1, /* Rapidly falling temp. */ 36729949e86Sstevel TREND_FALL = 2, /* Falling temperature */ 36829949e86Sstevel TREND_STABLE = 3, /* Stable temperature */ 36929949e86Sstevel TREND_RISE = 4, /* Rising temperature */ 37029949e86Sstevel TREND_RAPID_RISE = 5, /* Rapidly rising temperature */ 37129949e86Sstevel TREND_NOISY = 6 }; /* Unknown trend (noisy) */ 37229949e86Sstevel 37329949e86Sstevel /* Thresholds for temperature trend */ 37429949e86Sstevel #define NOISE_THRESH 2 37529949e86Sstevel #define RAPID_RISE_THRESH 4 37629949e86Sstevel #define RAPID_FALL_THRESH 4 37729949e86Sstevel 37829949e86Sstevel /* 37929949e86Sstevel * Main structure for passing the calibrated and time averaged temperature 38029949e86Sstevel * values to user processes. This structure is copied out via the kstat 38129949e86Sstevel * mechanism. 38229949e86Sstevel */ 38329949e86Sstevel #define TEMP_KSTAT_VERSION 3 /* version of temp_stats structure */ 38429949e86Sstevel struct temp_stats { 38529949e86Sstevel uint_t index; /* index of current temperature */ 38629949e86Sstevel short l1[L1_SZ]; /* OVERTEMP_TIMEOUT_SEC samples */ 38729949e86Sstevel short l2[L2_SZ]; /* level 2 samples */ 38829949e86Sstevel short l3[L3_SZ]; /* level 3 samples */ 38929949e86Sstevel short l4[L4_SZ]; /* level 4 samples */ 39029949e86Sstevel short l5[L5_SZ]; /* level 5 samples */ 39129949e86Sstevel short max; /* maximum temperature recorded */ 39229949e86Sstevel short min; /* minimum temperature recorded */ 39329949e86Sstevel enum temp_state state; /* state of board temperature */ 39429949e86Sstevel int temp_cnt; /* counter for state changes */ 39529949e86Sstevel int shutdown_cnt; /* counter for overtemp shutdown */ 39629949e86Sstevel int version; /* version of this structure */ 39729949e86Sstevel enum temp_trend trend; /* temperature trend for board */ 39829949e86Sstevel short override; /* override temperature for testing */ 39929949e86Sstevel }; 40029949e86Sstevel 40129949e86Sstevel /* The variable fhc_cpu_warning_temp_threshold is initialized to this value. */ 40229949e86Sstevel #define FHC_CPU_WARNING_TEMP_THRESHOLD 45 40329949e86Sstevel 40429949e86Sstevel /* 40529949e86Sstevel * Fault list management. 40629949e86Sstevel * 40729949e86Sstevel * The following defines and enum definitions have been created to support 40829949e86Sstevel * the fault list (struct ft_list). These defines must match with the 40929949e86Sstevel * fault string table in fhc.c. If any faults are added, they must be 41029949e86Sstevel * added at the end of this list, and the table must be modified 41129949e86Sstevel * accordingly. 41229949e86Sstevel */ 41329949e86Sstevel enum ft_type { 41429949e86Sstevel FT_CORE_PS = 0, /* Core power supply */ 41529949e86Sstevel FT_OVERTEMP, /* Temperature */ 41629949e86Sstevel FT_AC_PWR, /* AC power Supply */ 41729949e86Sstevel FT_PPS, /* Peripheral Power Supply */ 41829949e86Sstevel FT_CLK_33, /* System 3.3 Volt Power */ 41929949e86Sstevel FT_CLK_50, /* System 5.0 Volt Power */ 42029949e86Sstevel FT_V5_P, /* Peripheral 5V Power */ 42129949e86Sstevel FT_V12_P, /* Peripheral 12V Power */ 42229949e86Sstevel FT_V5_AUX, /* Auxiliary 5V Power */ 42329949e86Sstevel FT_V5_P_PCH, /* Peripheral 5V Precharge */ 42429949e86Sstevel FT_V12_P_PCH, /* Peripheral 12V Precharge */ 42529949e86Sstevel FT_V3_PCH, /* System 3V Precharge */ 42629949e86Sstevel FT_V5_PCH, /* System 5V Precharge */ 42729949e86Sstevel FT_PPS_FAN, /* Peripheral Power Supply Fan */ 42829949e86Sstevel FT_RACK_EXH, /* Rack Exhaust Fan */ 42929949e86Sstevel FT_DSK_FAN, /* 4 (or 5) Slot Disk Fan */ 43029949e86Sstevel FT_AC_FAN, /* AC Box Fan */ 43129949e86Sstevel FT_KEYSW_FAN, /* Key Switch Fan */ 43229949e86Sstevel FT_INSUFFICIENT_POWER, /* System has insufficient power */ 43329949e86Sstevel FT_PROM, /* fault inherited from PROM */ 43429949e86Sstevel FT_HOT_PLUG, /* hot plug unavailable */ 43529949e86Sstevel FT_TODFAULT /* tod error detection */ 43629949e86Sstevel }; 43729949e86Sstevel 43829949e86Sstevel enum ft_class { 43929949e86Sstevel FT_BOARD, 44029949e86Sstevel FT_SYSTEM 44129949e86Sstevel }; 44229949e86Sstevel 44329949e86Sstevel /* 44429949e86Sstevel * This extern allows other drivers to use the ft_str_table if they 44529949e86Sstevel * have fhc specified as a depends_on driver. 44629949e86Sstevel */ 44729949e86Sstevel extern char *ft_str_table[]; 44829949e86Sstevel 44929949e86Sstevel /* Maximum length of string table entries */ 45029949e86Sstevel #define MAX_FT_DESC 64 45129949e86Sstevel 45229949e86Sstevel #define FT_LIST_KSTAT_NAME "fault_list" 45329949e86Sstevel 45429949e86Sstevel /* 45529949e86Sstevel * The fault list structure is a structure for holding information on 45629949e86Sstevel * kernel detected faults. The fault list structures are linked into 45729949e86Sstevel * a list and the list is protected by the ftlist_mutex. There are 45829949e86Sstevel * also several routines for manipulating the fault list. 45929949e86Sstevel */ 46029949e86Sstevel struct ft_list { 46129949e86Sstevel int32_t unit; /* unit number of faulting device */ 46229949e86Sstevel enum ft_type type; /* type of faulting device */ 46329949e86Sstevel int32_t pad; /* padding to replace old next pointer */ 46429949e86Sstevel enum ft_class fclass; /* System or board class fault */ 46529949e86Sstevel time32_t create_time; /* Time stamp at fault detection */ 46629949e86Sstevel char msg[MAX_FT_DESC]; /* fault string */ 46729949e86Sstevel }; 46829949e86Sstevel 46929949e86Sstevel /* 47029949e86Sstevel * Allow binary compatibility between ILP32 and LP64 by 47129949e86Sstevel * eliminating the next pointer and making ft_list a fixed size. 47229949e86Sstevel * The structure name "ft_list" remains unchanged for 47329949e86Sstevel * source compatibility of kstat applications. 47429949e86Sstevel */ 47529949e86Sstevel struct ft_link_list { 47629949e86Sstevel struct ft_list f; 47729949e86Sstevel struct ft_link_list *next; 47829949e86Sstevel }; 47929949e86Sstevel 48029949e86Sstevel /* 48129949e86Sstevel * Board list management. 48229949e86Sstevel * 48329949e86Sstevel * Enumerated types for defining type of system and clock 48429949e86Sstevel * boards. It is used by both the kernel and user programs. 48529949e86Sstevel */ 48629949e86Sstevel enum board_type { 487*c6a28d76SToomas Soome EMPTY_BOARD = -1, 48829949e86Sstevel UNINIT_BOARD = 0, /* Uninitialized board type */ 48929949e86Sstevel UNKNOWN_BOARD, /* Unknown board type */ 49029949e86Sstevel CPU_BOARD, /* System board CPU(s) */ 49129949e86Sstevel MEM_BOARD, /* System board no CPUs */ 49229949e86Sstevel IO_2SBUS_BOARD, /* 2 SBus & SOC IO Board */ 49329949e86Sstevel IO_SBUS_FFB_BOARD, /* SBus & FFB SOC IO Board */ 49429949e86Sstevel IO_PCI_BOARD, /* PCI IO Board */ 49529949e86Sstevel DISK_BOARD, /* Disk Drive Board */ 49629949e86Sstevel CLOCK_BOARD, /* System Clock board */ 49729949e86Sstevel IO_2SBUS_SOCPLUS_BOARD, /* 2 SBus & SOC+ IO board */ 49829949e86Sstevel IO_SBUS_FFB_SOCPLUS_BOARD /* SBus&FFB&SOC+ board */ 49929949e86Sstevel }; 50029949e86Sstevel 50129949e86Sstevel /* 50229949e86Sstevel * Defined strings for comparing with OBP board-type property. If OBP ever 50329949e86Sstevel * changes the board-type properties, these string defines must be changed 50429949e86Sstevel * as well. 50529949e86Sstevel */ 50629949e86Sstevel #define CPU_BD_NAME "cpu" 50729949e86Sstevel #define MEM_BD_NAME "mem" 50829949e86Sstevel #define IO_2SBUS_BD_NAME "dual-sbus" 50929949e86Sstevel #define IO_SBUS_FFB_BD_NAME "upa-sbus" 51029949e86Sstevel #define IO_PCI_BD_NAME "dual-pci" 51129949e86Sstevel #define DISK_BD_NAME "disk" 51229949e86Sstevel #define IO_2SBUS_SOCPLUS_BD_NAME "dual-sbus-soc+" 51329949e86Sstevel #define IO_SBUS_FFB_SOCPLUS_BD_NAME "upa-sbus-soc+" 51429949e86Sstevel 51529949e86Sstevel /* 51629949e86Sstevel * The following structures and union are needed because the bd_info 51729949e86Sstevel * structure describes all types of system boards. 51829949e86Sstevel * XXX - We cannot determine Spitfire rev from JTAG scan, so it is 51929949e86Sstevel * left blank for now. Future implementations might fill in this info. 52029949e86Sstevel */ 52129949e86Sstevel struct cpu_info { 52229949e86Sstevel int cpu_rev; /* CPU revision */ 52329949e86Sstevel int cpu_speed; /* rated speed of CPU in MHz */ 52429949e86Sstevel int cpu_compid; /* CPU component ID */ 52529949e86Sstevel int sdb0_compid; /* SDB component ID */ 52629949e86Sstevel int sdb1_compid; /* SDB component ID */ 52729949e86Sstevel int ec_compid; /* Ecache RAM ID, needed for cache size */ 52829949e86Sstevel int cache_size; /* Cache size in bytes */ 52929949e86Sstevel int cpu_sram_mode; /* module's sram mode */ 53029949e86Sstevel int cpu_detected; /* Something on the CPU JTAG ring. */ 53129949e86Sstevel }; 53229949e86Sstevel 53329949e86Sstevel struct io1_info { 53429949e86Sstevel int sio0_compid; /* Sysio component ID */ 53529949e86Sstevel int sio1_compid; /* Sysio component ID */ 53629949e86Sstevel int hme_compid; /* several revs in existence */ 53729949e86Sstevel int soc_compid; /* SOC */ 53829949e86Sstevel }; 53929949e86Sstevel 54029949e86Sstevel struct io1plus_info { 54129949e86Sstevel int sio0_compid; /* Sysio component ID */ 54229949e86Sstevel int sio1_compid; /* Sysio component ID */ 54329949e86Sstevel int hme_compid; /* several revs in existence */ 54429949e86Sstevel int socplus_compid; /* SOC+ */ 54529949e86Sstevel }; 54629949e86Sstevel 54729949e86Sstevel /* Defines for the FFB size field */ 54829949e86Sstevel #define FFB_FAILED -1 54929949e86Sstevel #define FFB_NOT_FOUND 0 55029949e86Sstevel #define FFB_SINGLE 1 55129949e86Sstevel #define FFB_DOUBLE 2 55229949e86Sstevel 55329949e86Sstevel struct io2_info { 55429949e86Sstevel int fbc_compid; /* FBC component ID */ 55529949e86Sstevel int ffb_size; /* not present, single or dbl buffered */ 55629949e86Sstevel int sio1_compid; /* Sysio component ID */ 55729949e86Sstevel int hme_compid; /* several revs in existence */ 55829949e86Sstevel int soc_compid; /* SOC component ID */ 55929949e86Sstevel }; 56029949e86Sstevel 56129949e86Sstevel struct io2plus_info { 56229949e86Sstevel int fbc_compid; /* FBC component ID */ 56329949e86Sstevel int ffb_size; /* not present, single or dbl buffered */ 56429949e86Sstevel int sio1_compid; /* Sysio component ID */ 56529949e86Sstevel int hme_compid; /* several revs in existence */ 56629949e86Sstevel int socplus_compid; /* or SOC+ component ID */ 56729949e86Sstevel }; 56829949e86Sstevel 56929949e86Sstevel struct io3_info { 57029949e86Sstevel int psyo0_compid; /* Psycho+ component ID */ 57129949e86Sstevel int psyo1_compid; /* Psycho+ component ID */ 57229949e86Sstevel int cheo_compid; /* Cheerio component ID */ 57329949e86Sstevel }; 57429949e86Sstevel 57529949e86Sstevel struct dsk_info { 57629949e86Sstevel int disk_pres[2]; 57729949e86Sstevel int disk_id[2]; 57829949e86Sstevel }; 57929949e86Sstevel 58029949e86Sstevel union bd_un { 58129949e86Sstevel struct cpu_info cpu[2]; 58229949e86Sstevel struct io1_info io1; 58329949e86Sstevel struct io2_info io2; 58429949e86Sstevel struct io3_info io3; 58529949e86Sstevel struct dsk_info dsk; 58629949e86Sstevel struct io1plus_info io1plus; 58729949e86Sstevel struct io2plus_info io2plus; 58829949e86Sstevel }; 58929949e86Sstevel 59029949e86Sstevel /* 59129949e86Sstevel * board_state and bd_info are maintained for backward 59229949e86Sstevel * compatibility with prtdiag and others user programs that may rely 59329949e86Sstevel * on them. 59429949e86Sstevel */ 59529949e86Sstevel enum board_state { 59629949e86Sstevel UNKNOWN_STATE = 0, /* Unknown board */ 59729949e86Sstevel ACTIVE_STATE, /* active and working */ 59829949e86Sstevel HOTPLUG_STATE, /* Hot plugged board */ 59929949e86Sstevel LOWPOWER_STATE, /* Powered down board */ 60029949e86Sstevel DISABLED_STATE, /* Board disabled by PROM */ 60129949e86Sstevel FAILED_STATE /* Board failed by POST */ 60229949e86Sstevel }; 60329949e86Sstevel 60429949e86Sstevel struct bd_info { 60529949e86Sstevel enum board_type type; /* Type of board */ 60629949e86Sstevel enum board_state state; /* current state of this board */ 60729949e86Sstevel int board; /* board number */ 60829949e86Sstevel int fhc_compid; /* fhc component id */ 60929949e86Sstevel int ac_compid; /* ac component id */ 61029949e86Sstevel char prom_rev[64]; /* best guess as to what is needed */ 61129949e86Sstevel union bd_un bd; 61229949e86Sstevel }; 61329949e86Sstevel 61429949e86Sstevel /* 61529949e86Sstevel * Config admin interface. 61629949e86Sstevel * 61729949e86Sstevel * Receptacle states. 61829949e86Sstevel */ 61929949e86Sstevel typedef enum { 62029949e86Sstevel SYSC_CFGA_RSTATE_EMPTY = 0, /* Empty state */ 62129949e86Sstevel SYSC_CFGA_RSTATE_DISCONNECTED, /* DISCONNECTED state */ 62229949e86Sstevel SYSC_CFGA_RSTATE_CONNECTED /* CONNECTED state */ 62329949e86Sstevel } sysc_cfga_rstate_t; 62429949e86Sstevel 62529949e86Sstevel /* 62629949e86Sstevel * Occupant states. 62729949e86Sstevel */ 62829949e86Sstevel typedef enum { 62929949e86Sstevel SYSC_CFGA_OSTATE_UNCONFIGURED = 0, /* UNCONFIGURED state */ 63029949e86Sstevel SYSC_CFGA_OSTATE_CONFIGURED /* CONFIGURED state */ 63129949e86Sstevel } sysc_cfga_ostate_t; 63229949e86Sstevel 63329949e86Sstevel /* 63429949e86Sstevel * Receptacle/Occupant condition. 63529949e86Sstevel */ 63629949e86Sstevel typedef enum { 63729949e86Sstevel SYSC_CFGA_COND_UNKNOWN = 0, /* Unknown condition */ 63829949e86Sstevel SYSC_CFGA_COND_OK, /* Condition OK */ 63929949e86Sstevel SYSC_CFGA_COND_FAILING, /* Failing */ 64029949e86Sstevel SYSC_CFGA_COND_FAILED, /* Failed */ 64129949e86Sstevel SYSC_CFGA_COND_UNUSABLE /* Unusable */ 64229949e86Sstevel } sysc_cfga_cond_t; 64329949e86Sstevel 64429949e86Sstevel /* 64529949e86Sstevel * Error definitions for CFGADM platform library 64629949e86Sstevel */ 64729949e86Sstevel typedef enum { 64829949e86Sstevel SYSC_ERR_DEFAULT = 0, /* generic errors */ 64929949e86Sstevel SYSC_ERR_INTRANS, /* hardware in transition */ 65029949e86Sstevel SYSC_ERR_UTHREAD, /* can't stop user thread */ 65129949e86Sstevel SYSC_ERR_KTHREAD, /* can't stop kernel thread */ 65229949e86Sstevel SYSC_ERR_SUSPEND, /* can't suspend a device */ 65329949e86Sstevel SYSC_ERR_RESUME, /* can't resume a device */ 65429949e86Sstevel SYSC_ERR_POWER, /* not enough power for slot */ 65529949e86Sstevel SYSC_ERR_COOLING, /* not enough cooling for slot */ 65629949e86Sstevel SYSC_ERR_PRECHARGE, /* not enough precharge for slot */ 65729949e86Sstevel SYSC_ERR_HOTPLUG, /* Hot Plug Unavailable */ 65829949e86Sstevel SYSC_ERR_HW_COMPAT, /* incompatible hardware found during dr */ 65929949e86Sstevel SYSC_ERR_NON_DR_PROM, /* prom not support Dynamic Reconfiguration */ 66029949e86Sstevel SYSC_ERR_CORE_RESOURCE, /* core resource cannot be removed */ 66129949e86Sstevel SYSC_ERR_PROM, /* error encountered in OBP/POST */ 66229949e86Sstevel SYSC_ERR_DR_INIT, /* error encountered in sysc_dr_init op */ 66329949e86Sstevel SYSC_ERR_NDI_ATTACH, /* error encountered in NDI attach operations */ 66429949e86Sstevel SYSC_ERR_NDI_DETACH, /* error encountered in NDI detach operations */ 66529949e86Sstevel SYSC_ERR_RSTATE, /* wrong receptacle state */ 66629949e86Sstevel SYSC_ERR_OSTATE, /* wrong occupant state */ 66729949e86Sstevel SYSC_ERR_COND /* invalid condition */ 66829949e86Sstevel } sysc_err_t; 66929949e86Sstevel 67029949e86Sstevel /* 67129949e86Sstevel * Config admin structure. 67229949e86Sstevel */ 67329949e86Sstevel typedef struct sysc_cfga_stat { 67429949e86Sstevel /* generic representation of the attachment point below */ 67529949e86Sstevel sysc_cfga_rstate_t rstate; /* current receptacle state */ 67629949e86Sstevel sysc_cfga_ostate_t ostate; /* current occupant state */ 67729949e86Sstevel sysc_cfga_cond_t condition; /* current board condition */ 67829949e86Sstevel time32_t last_change; /* last state/condition change */ 67929949e86Sstevel uint_t in_transition:1; /* board is in_transition */ 68029949e86Sstevel 68129949e86Sstevel /* platform specific below */ 68229949e86Sstevel enum board_type type; /* Type of board */ 68329949e86Sstevel int board; /* board number */ 68429949e86Sstevel int fhc_compid; /* fhc component id */ 68529949e86Sstevel int ac_compid; /* ac component id */ 68629949e86Sstevel char prom_rev[64]; /* best guess as to what is needed */ 68729949e86Sstevel union bd_un bd; 68829949e86Sstevel uint_t no_detach:1; /* board is non_detachable */ 68929949e86Sstevel uint_t plus_board:1; /* board is 98 MHz capable */ 69029949e86Sstevel } sysc_cfga_stat_t; 69129949e86Sstevel 69229949e86Sstevel /* 69329949e86Sstevel * Config admin command structure for SYSC_CFGA ioctls. 69429949e86Sstevel */ 69529949e86Sstevel typedef struct sysc_cfga_cmd { 69629949e86Sstevel uint_t force:1; /* force this state transition */ 69729949e86Sstevel uint_t test:1; /* Need to test hardware */ 69829949e86Sstevel int arg; /* generic data for test */ 69929949e86Sstevel sysc_err_t errtype; /* error code returned */ 70029949e86Sstevel char *outputstr; /* output returned from ioctl */ 70129949e86Sstevel } sysc_cfga_cmd_t; 70229949e86Sstevel 70329949e86Sstevel typedef struct sysc_cfga_cmd32 { 70429949e86Sstevel uint_t force:1; /* force this state transition */ 70529949e86Sstevel uint_t test:1; /* Need to test hardware */ 70629949e86Sstevel int arg; /* generic data for test */ 70729949e86Sstevel sysc_err_t errtype; /* error code returned */ 70829949e86Sstevel caddr32_t outputstr; /* output returned from ioctl */ 70929949e86Sstevel } sysc_cfga_cmd32_t; 71029949e86Sstevel 71129949e86Sstevel typedef struct sysc_cfga_pkt { 71229949e86Sstevel sysc_cfga_cmd_t cmd_cfga; 71329949e86Sstevel char *errbuf; /* internal error buffer */ 71429949e86Sstevel } sysc_cfga_pkt_t; 71529949e86Sstevel 71629949e86Sstevel /* 71729949e86Sstevel * Sysctrl DR sequencer interface. 71829949e86Sstevel */ 71929949e86Sstevel typedef struct sysc_dr_handle { 72029949e86Sstevel dev_info_t **dip_list; /* list of top dips for board */ 72129949e86Sstevel int dip_list_len; /* length devinfo list */ 72229949e86Sstevel int flags; /* dr specific flags */ 72329949e86Sstevel int error; /* dr operation error */ 72429949e86Sstevel char *errstr; /* dr config/unfig error message */ 72529949e86Sstevel } sysc_dr_handle_t; 72629949e86Sstevel 72729949e86Sstevel #define SYSC_DR_MAX_NODE 32 72829949e86Sstevel #define SYSC_DR_FHC 0x1 /* connect phase init (fhc) */ 72929949e86Sstevel #define SYSC_DR_DEVS 0x2 /* config phase init (devices) */ 73029949e86Sstevel #define SYSC_DR_FORCE 0x4 /* force detach */ 73129949e86Sstevel #define SYSC_DR_REMOVE 0x8 /* remove dev_info */ 73229949e86Sstevel 73329949e86Sstevel #define SYSC_DR_HANDLE_FHC 0x0 73429949e86Sstevel #define SYSC_DR_HANDLE_DEVS 0x1 73529949e86Sstevel 73629949e86Sstevel /* 73729949e86Sstevel * Sysctrl event interface. 73829949e86Sstevel */ 73929949e86Sstevel typedef enum sysc_evt { 74029949e86Sstevel SYSC_EVT_BD_EMPTY = 0, 74129949e86Sstevel SYSC_EVT_BD_PRESENT, 74229949e86Sstevel SYSC_EVT_BD_DISABLED, 74329949e86Sstevel SYSC_EVT_BD_FAILED, 74429949e86Sstevel SYSC_EVT_BD_OVERTEMP, 74529949e86Sstevel SYSC_EVT_BD_TEMP_OK, 74629949e86Sstevel SYSC_EVT_BD_PS_CHANGE, 74729949e86Sstevel SYSC_EVT_BD_INS_FAILED, 74829949e86Sstevel SYSC_EVT_BD_INSERTED, 74929949e86Sstevel SYSC_EVT_BD_REMOVED, 75029949e86Sstevel SYSC_EVT_BD_HP_DISABLED, 75129949e86Sstevel SYSC_EVT_BD_CORE_RESOURCE_DISCONNECT 75229949e86Sstevel } sysc_evt_t; 75329949e86Sstevel 75429949e86Sstevel /* 75529949e86Sstevel * sysctrl audit message events 75629949e86Sstevel */ 75729949e86Sstevel typedef enum sysc_audit_evt { 75829949e86Sstevel SYSC_AUDIT_RSTATE_EMPTY = 0, 75929949e86Sstevel SYSC_AUDIT_RSTATE_CONNECT, 76029949e86Sstevel SYSC_AUDIT_RSTATE_DISCONNECT, 76129949e86Sstevel SYSC_AUDIT_RSTATE_SUCCEEDED, 76229949e86Sstevel SYSC_AUDIT_RSTATE_EMPTY_FAILED, 76329949e86Sstevel SYSC_AUDIT_RSTATE_CONNECT_FAILED, 76429949e86Sstevel SYSC_AUDIT_RSTATE_DISCONNECT_FAILED, 76529949e86Sstevel SYSC_AUDIT_OSTATE_CONFIGURE, 76629949e86Sstevel SYSC_AUDIT_OSTATE_UNCONFIGURE, 76729949e86Sstevel SYSC_AUDIT_OSTATE_SUCCEEDED, 76829949e86Sstevel SYSC_AUDIT_OSTATE_CONFIGURE_FAILED, 76929949e86Sstevel SYSC_AUDIT_OSTATE_UNCONFIGURE_FAILED 77029949e86Sstevel } sysc_audit_evt_t; 77129949e86Sstevel 77229949e86Sstevel typedef struct { 77329949e86Sstevel void (*update)(void *, sysc_cfga_stat_t *, sysc_evt_t); 77429949e86Sstevel void *soft; 77529949e86Sstevel } sysc_evt_handle_t; 77629949e86Sstevel 77729949e86Sstevel void fhc_bd_sc_register(void f(void *, sysc_cfga_stat_t *, sysc_evt_t), void *); 77829949e86Sstevel 77929949e86Sstevel /* 78029949e86Sstevel * The board list structure is the central storage for the kernel's 78129949e86Sstevel * knowledge of normally booted and hotplugged boards. 78229949e86Sstevel */ 78329949e86Sstevel typedef struct bd_list { 78429949e86Sstevel struct fhc_soft_state *softsp; /* handle for DDI soft state */ 78529949e86Sstevel sysc_cfga_stat_t sc; /* board info */ 78629949e86Sstevel sysc_dr_handle_t sh[2]; /* sysctrl dr interface */ 78729949e86Sstevel void *dev_softsp; /* opaque pointer to device state */ 78829949e86Sstevel void *ac_softsp; /* opaque pointer to our AC */ 78929949e86Sstevel struct kstat *ksp; /* pointer used in kstat destroy */ 79029949e86Sstevel int fault; /* failure on this board? */ 79129949e86Sstevel int flags; /* board state flags */ 79229949e86Sstevel } fhc_bd_t; 79329949e86Sstevel 79429949e86Sstevel /* 79529949e86Sstevel * Fhc_bd.c holds 2 resizable arrays of boards. First for clock 79629949e86Sstevel * boards under central and second for normally booted and 79729949e86Sstevel * hotplugged boards. 79829949e86Sstevel */ 79929949e86Sstevel typedef struct resizable_bd_list { 80029949e86Sstevel fhc_bd_t **boards; 80129949e86Sstevel int size; 80229949e86Sstevel int last; 80329949e86Sstevel int sorted; 80429949e86Sstevel } fhc_bd_resizable_t; 80529949e86Sstevel 80629949e86Sstevel #define BDF_VALID 0x1 /* board entry valid */ 80729949e86Sstevel #define BDF_DETACH 0x2 /* board detachable */ 80829949e86Sstevel #define BDF_DISABLED 0x4 /* board disabled */ 80929949e86Sstevel 81029949e86Sstevel #define SYSC_OUTPUT_LEN MAXPATHLEN /* output str len */ 81129949e86Sstevel 81229949e86Sstevel /* 81329949e86Sstevel * Board list management interface. 81429949e86Sstevel */ 81529949e86Sstevel int fhc_max_boards(void); 81629949e86Sstevel void fhc_bdlist_init(void); 81729949e86Sstevel void fhc_bdlist_fini(void); 81829949e86Sstevel void fhc_bdlist_prime(int, int, int); 81929949e86Sstevel fhc_bd_t *fhc_bdlist_lock(int); 82029949e86Sstevel void fhc_bdlist_unlock(void); 82129949e86Sstevel 82229949e86Sstevel void fhc_bd_init(struct fhc_soft_state *, int, enum board_type); 82329949e86Sstevel fhc_bd_t *fhc_bd(int); 82429949e86Sstevel fhc_bd_t *fhc_bd_clock(void); 82529949e86Sstevel fhc_bd_t *fhc_bd_first(void); 82629949e86Sstevel fhc_bd_t *fhc_bd_next(fhc_bd_t *); 82729949e86Sstevel enum board_type fhc_bd_type(int); 82829949e86Sstevel char *fhc_bd_typestr(enum board_type); 82929949e86Sstevel int fhc_bd_valid(int); 83029949e86Sstevel int fhc_bd_detachable(int); 83129949e86Sstevel 83229949e86Sstevel int fhc_bd_insert_scan(void); 83329949e86Sstevel int fhc_bd_remove_scan(void); 83429949e86Sstevel int fhc_bd_test(int, sysc_cfga_pkt_t *); 83529949e86Sstevel int fhc_bd_test_set_cond(int, sysc_cfga_pkt_t *); 83629949e86Sstevel void fhc_bd_update(int, sysc_evt_t); 83729949e86Sstevel void fhc_bd_env_set(int, void *); 83829949e86Sstevel 83929949e86Sstevel int fhc_bdlist_locked(void); 84029949e86Sstevel int fhc_bd_busy(int); 84129949e86Sstevel int fhc_bd_is_jtag_master(int); 84229949e86Sstevel int fhc_bd_is_plus(int); 84329949e86Sstevel 84429949e86Sstevel #if defined(_KERNEL) 84529949e86Sstevel 84629949e86Sstevel /* 84729949e86Sstevel * In order to indicate that we are in an environmental chamber, or 84829949e86Sstevel * oven, the test people will set the 'mfg-mode' property in the 84929949e86Sstevel * options node to 'chamber'. Therefore we have the following define. 85029949e86Sstevel */ 85129949e86Sstevel #define CHAMBER_VALUE "chamber" 85229949e86Sstevel 85329949e86Sstevel /* 85429949e86Sstevel * zs design for fhc has two zs' interrupting on same interrupt mondo 85529949e86Sstevel * This requires us to poll for zs and zs alone. The poll list has been 85629949e86Sstevel * defined as a fixed size for simplicity. 85729949e86Sstevel */ 85829949e86Sstevel #define MAX_ZS_CNT 2 85929949e86Sstevel 86029949e86Sstevel /* FHC Interrupt routine wrapper structure */ 86129949e86Sstevel struct fhc_wrapper_arg { 86229949e86Sstevel struct fhc_soft_state *softsp; 86329949e86Sstevel volatile uint_t *clear_reg; 86429949e86Sstevel volatile uint_t *mapping_reg; 86529949e86Sstevel dev_info_t *child; 86629949e86Sstevel uint32_t inum; 86729949e86Sstevel uint_t (*funcp)(caddr_t, caddr_t); 86829949e86Sstevel caddr_t arg1; 86929949e86Sstevel caddr_t arg2; 87029949e86Sstevel }; 87129949e86Sstevel 87229949e86Sstevel /* 87329949e86Sstevel * The JTAG master command structure. It contains the address of the 87429949e86Sstevel * the JTAG controller on this system board. The controller can only 87529949e86Sstevel * be used if this FHC holds the JTAG master signal. This is checked 87629949e86Sstevel * by reading the JTAG control register on this FHC. 87729949e86Sstevel */ 87829949e86Sstevel struct jt_mstr { 87929949e86Sstevel volatile uint_t *jtag_cmd; 88029949e86Sstevel int is_master; 88129949e86Sstevel kmutex_t lock; 88229949e86Sstevel }; 88329949e86Sstevel 88429949e86Sstevel /* Functions exported to manage the fault list */ 88529949e86Sstevel void reg_fault(int, enum ft_type, enum ft_class); 88629949e86Sstevel void clear_fault(int, enum ft_type, enum ft_class); 88729949e86Sstevel int process_fault_list(void); 88829949e86Sstevel void create_ft_kstats(int); 88929949e86Sstevel 89029949e86Sstevel /* memloc's are protected under the bdlist lock */ 89129949e86Sstevel struct fhc_memloc { 89229949e86Sstevel struct fhc_memloc *next; 89329949e86Sstevel int board; /* reference our board element */ 89429949e86Sstevel uint_t pa; /* base PA of this segment (in MB) */ 89529949e86Sstevel uint_t size; /* size of this segment (in MB) */ 89629949e86Sstevel }; 89729949e86Sstevel 89829949e86Sstevel /* Functions used to manage memory 'segments' */ 89929949e86Sstevel #define FHC_MEMLOC_SHIFT 20 90029949e86Sstevel #define FHC_MEMLOC_MAX (0x10000000000ull >> FHC_MEMLOC_SHIFT) 90129949e86Sstevel void fhc_add_memloc(int board, uint64_t pa, uint_t size); 90229949e86Sstevel void fhc_del_memloc(int board); 90329949e86Sstevel uint64_t fhc_find_memloc_gap(uint_t size); 90429949e86Sstevel void fhc_program_memory(int board, uint64_t base); 90529949e86Sstevel 90629949e86Sstevel /* Structures used in the driver to manage the hardware */ 90729949e86Sstevel struct fhc_soft_state { 90829949e86Sstevel dev_info_t *dip; /* dev info of myself */ 90929949e86Sstevel struct bd_list *list; /* pointer to board list entry */ 91029949e86Sstevel int is_central; /* A central space instance of FHC */ 91129949e86Sstevel volatile uint_t *id; /* FHC ID register */ 91229949e86Sstevel volatile uint_t *rctrl; /* FHC Reset Control and Status */ 91329949e86Sstevel volatile uint_t *bsr; /* FHC Board Status register */ 91429949e86Sstevel volatile uint_t *jtag_ctrl; /* JTAG Control register */ 91529949e86Sstevel volatile uint_t *igr; /* Interrupt Group Number */ 91629949e86Sstevel struct intr_regs intr_regs[FHC_MAX_INO]; 91729949e86Sstevel struct fhc_wrapper_arg poll_list[MAX_ZS_CNT]; 91829949e86Sstevel struct fhc_wrapper_arg *intr_list[FHC_MAX_INO]; 91929949e86Sstevel kmutex_t poll_list_lock; 92029949e86Sstevel uchar_t spurious_zs_cntr; /* Spurious counter for zs devices */ 92129949e86Sstevel kmutex_t pokefault_mutex; 92229949e86Sstevel int pokefault; 92329949e86Sstevel 92429949e86Sstevel /* this lock protects the following data */ 92529949e86Sstevel /* ! non interrupt use only ! */ 92629949e86Sstevel kmutex_t ctrl_lock; /* lock for access to FHC CSR */ 92729949e86Sstevel volatile uint_t *ctrl; /* FHC Control and Status */ 92829949e86Sstevel 92929949e86Sstevel /* The JTAG master structure has internal locking */ 93029949e86Sstevel struct jt_mstr jt_master; 93129949e86Sstevel 93229949e86Sstevel /* the pointer to the kstat is stored for deletion upon detach */ 93329949e86Sstevel kstat_t *fhc_ksp; 93429949e86Sstevel }; 93529949e86Sstevel 93629949e86Sstevel /* 93729949e86Sstevel * Function shared with child drivers which require fhc 93829949e86Sstevel * support. They gain access to this function through the use of the 93929949e86Sstevel * _depends_on variable. 94029949e86Sstevel */ 94129949e86Sstevel enum board_type get_board_type(int board); 94229949e86Sstevel void update_temp(dev_info_t *pdip, struct temp_stats *envstat, uchar_t value); 94329949e86Sstevel enum temp_trend temp_trend(struct temp_stats *); 94429949e86Sstevel void fhc_reboot(void); 94529949e86Sstevel int overtemp_kstat_update(kstat_t *ksp, int rw); 94629949e86Sstevel int temp_override_kstat_update(kstat_t *ksp, int rw); 94729949e86Sstevel void init_temp_arrays(struct temp_stats *envstat); 94829949e86Sstevel void update_board_leds(fhc_bd_t *, uint_t, uint_t); 94929949e86Sstevel struct jt_mstr *jtag_master_lock(void); 95029949e86Sstevel void jtag_master_unlock(struct jt_mstr *); 95129949e86Sstevel extern int fhc_board_poweroffcpus(int board, char *errbuf, int cpu_flags); 95229949e86Sstevel 95329949e86Sstevel 95429949e86Sstevel /* FHC interrupt specification */ 95529949e86Sstevel struct fhcintrspec { 95629949e86Sstevel uint_t mondo; 95729949e86Sstevel uint_t pil; 95829949e86Sstevel dev_info_t *child; 95929949e86Sstevel struct fhc_wrapper_arg *handler_arg; 96029949e86Sstevel }; 96129949e86Sstevel 96229949e86Sstevel /* kstat structure used by fhc to pass data to user programs. */ 96329949e86Sstevel struct fhc_kstat { 96429949e86Sstevel struct kstat_named csr; /* FHC Control and Status Register */ 96529949e86Sstevel struct kstat_named bsr; /* FHC Board Status Register */ 96629949e86Sstevel }; 96729949e86Sstevel 96829949e86Sstevel #endif /* _KERNEL */ 96929949e86Sstevel 97029949e86Sstevel #endif /* _ASM */ 97129949e86Sstevel 97229949e86Sstevel #ifdef __cplusplus 97329949e86Sstevel } 97429949e86Sstevel #endif 97529949e86Sstevel 97629949e86Sstevel #endif /* _SYS_FHC_H */ 977