17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5c56c1e58Sgirish * Common Development and Distribution License (the "License").
6c56c1e58Sgirish * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
217c478bd9Sstevel@tonic-gate /*
220542eecfSRafael Vanoni * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23*6bf877adSPeter Tribble * Copyright 2019 Peter Tribble.
247c478bd9Sstevel@tonic-gate */
257c478bd9Sstevel@tonic-gate
267c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>
277c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
287c478bd9Sstevel@tonic-gate #include <sys/vm.h>
297c478bd9Sstevel@tonic-gate #include <sys/cpu.h>
3025cf1a30Sjl #include <sys/cpupart.h>
316890d023SEric Saxe #include <sys/cmt.h>
326890d023SEric Saxe #include <sys/bitset.h>
337c478bd9Sstevel@tonic-gate #include <sys/reboot.h>
347c478bd9Sstevel@tonic-gate #include <sys/kdi.h>
357c478bd9Sstevel@tonic-gate #include <sys/bootconf.h>
367c478bd9Sstevel@tonic-gate #include <sys/memlist_plat.h>
377c478bd9Sstevel@tonic-gate #include <sys/memlist_impl.h>
387c478bd9Sstevel@tonic-gate #include <sys/prom_plat.h>
397c478bd9Sstevel@tonic-gate #include <sys/prom_isa.h>
407c478bd9Sstevel@tonic-gate #include <sys/autoconf.h>
417c478bd9Sstevel@tonic-gate #include <sys/intreg.h>
427c478bd9Sstevel@tonic-gate #include <sys/ivintr.h>
437c478bd9Sstevel@tonic-gate #include <sys/fpu/fpusystm.h>
447c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h>
457c478bd9Sstevel@tonic-gate #include <vm/vm_dep.h>
467c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h>
477c478bd9Sstevel@tonic-gate #include <vm/seg_kpm.h>
487c478bd9Sstevel@tonic-gate #include <vm/seg_map.h>
497c478bd9Sstevel@tonic-gate #include <vm/seg_kp.h>
507c478bd9Sstevel@tonic-gate #include <sys/sysconf.h>
517c478bd9Sstevel@tonic-gate #include <vm/hat_sfmmu.h>
527c478bd9Sstevel@tonic-gate #include <sys/kobj.h>
537c478bd9Sstevel@tonic-gate #include <sys/sun4asi.h>
547c478bd9Sstevel@tonic-gate #include <sys/clconf.h>
557c478bd9Sstevel@tonic-gate #include <sys/platform_module.h>
567c478bd9Sstevel@tonic-gate #include <sys/panic.h>
577c478bd9Sstevel@tonic-gate #include <sys/cpu_sgnblk_defs.h>
587c478bd9Sstevel@tonic-gate #include <sys/clock.h>
597c478bd9Sstevel@tonic-gate #include <sys/fpras_impl.h>
607c478bd9Sstevel@tonic-gate #include <sys/prom_debug.h>
617c478bd9Sstevel@tonic-gate #include <sys/traptrace.h>
627c478bd9Sstevel@tonic-gate #include <sys/memnode.h>
637c478bd9Sstevel@tonic-gate #include <sys/mem_cage.h>
647c478bd9Sstevel@tonic-gate
657c478bd9Sstevel@tonic-gate /*
667c478bd9Sstevel@tonic-gate * fpRAS implementation structures.
677c478bd9Sstevel@tonic-gate */
687c478bd9Sstevel@tonic-gate struct fpras_chkfn *fpras_chkfnaddrs[FPRAS_NCOPYOPS];
697c478bd9Sstevel@tonic-gate struct fpras_chkfngrp *fpras_chkfngrps;
707c478bd9Sstevel@tonic-gate struct fpras_chkfngrp *fpras_chkfngrps_base;
717c478bd9Sstevel@tonic-gate int fpras_frequency = -1;
727c478bd9Sstevel@tonic-gate int64_t fpras_interval = -1;
737c478bd9Sstevel@tonic-gate
746ceee06eSJerry Gilliam /*
756ceee06eSJerry Gilliam * Increase unix symbol table size as a work around for 6828121
766ceee06eSJerry Gilliam */
776ceee06eSJerry Gilliam int alloc_mem_bermuda_triangle;
786ceee06eSJerry Gilliam
7925cf1a30Sjl /*
8025cf1a30Sjl * Halt idling cpus optimization
8125cf1a30Sjl *
8225cf1a30Sjl * This optimation is only enabled in platforms that have
8325cf1a30Sjl * the CPU halt support. The cpu_halt_cpu() support is provided
8425cf1a30Sjl * in the cpu module and it is referenced here with a pragma weak.
8525cf1a30Sjl * The presence of this routine automatically enable the halt idling
8625cf1a30Sjl * cpus functionality if the global switch enable_halt_idle_cpus
8725cf1a30Sjl * is set (default is set).
8825cf1a30Sjl *
8925cf1a30Sjl */
9025cf1a30Sjl #pragma weak cpu_halt_cpu
9125cf1a30Sjl extern void cpu_halt_cpu();
9225cf1a30Sjl
93c210ded4Sesaxe /*
94c210ded4Sesaxe * Defines for the idle_state_transition DTrace probe
95c210ded4Sesaxe *
96c210ded4Sesaxe * The probe fires when the CPU undergoes an idle state change (e.g. halting)
97c210ded4Sesaxe * The agument passed is the state to which the CPU is transitioning.
98c210ded4Sesaxe *
99c210ded4Sesaxe * The states are defined here.
100c210ded4Sesaxe */
101c210ded4Sesaxe #define IDLE_STATE_NORMAL 0
102c210ded4Sesaxe #define IDLE_STATE_HALTED 1
103c210ded4Sesaxe
10425cf1a30Sjl int enable_halt_idle_cpus = 1; /* global switch */
10525cf1a30Sjl
1060542eecfSRafael Vanoni uint_t cp_haltset_fanout = 3;
1070542eecfSRafael Vanoni
1087c478bd9Sstevel@tonic-gate void
setup_trap_table(void)1097c478bd9Sstevel@tonic-gate setup_trap_table(void)
1107c478bd9Sstevel@tonic-gate {
1117c478bd9Sstevel@tonic-gate intr_init(CPU); /* init interrupt request free list */
1127c478bd9Sstevel@tonic-gate setwstate(WSTATE_KERN);
1137c478bd9Sstevel@tonic-gate prom_set_traptable(&trap_table);
1147c478bd9Sstevel@tonic-gate }
1157c478bd9Sstevel@tonic-gate
1167c478bd9Sstevel@tonic-gate void
mach_fpras()1177c478bd9Sstevel@tonic-gate mach_fpras()
1187c478bd9Sstevel@tonic-gate {
1197c478bd9Sstevel@tonic-gate if (fpras_implemented && !fpras_disable) {
1207c478bd9Sstevel@tonic-gate int i;
1217c478bd9Sstevel@tonic-gate struct fpras_chkfngrp *fcgp;
1227c478bd9Sstevel@tonic-gate size_t chkfngrpsallocsz;
1237c478bd9Sstevel@tonic-gate
1247c478bd9Sstevel@tonic-gate /*
1257c478bd9Sstevel@tonic-gate * Note that we size off of NCPU and setup for
1267c478bd9Sstevel@tonic-gate * all those possibilities regardless of whether
1277c478bd9Sstevel@tonic-gate * the cpu id is present or not. We do this so that
1287c478bd9Sstevel@tonic-gate * we don't have any construction or destruction
1297c478bd9Sstevel@tonic-gate * activity to perform at DR time, and it's not
1307c478bd9Sstevel@tonic-gate * costly in memory. We require block alignment.
1317c478bd9Sstevel@tonic-gate */
1327c478bd9Sstevel@tonic-gate chkfngrpsallocsz = NCPU * sizeof (struct fpras_chkfngrp);
1337c478bd9Sstevel@tonic-gate fpras_chkfngrps_base = kmem_alloc(chkfngrpsallocsz, KM_SLEEP);
1347c478bd9Sstevel@tonic-gate if (IS_P2ALIGNED((uintptr_t)fpras_chkfngrps_base, 64)) {
1357c478bd9Sstevel@tonic-gate fpras_chkfngrps = fpras_chkfngrps_base;
1367c478bd9Sstevel@tonic-gate } else {
1377c478bd9Sstevel@tonic-gate kmem_free(fpras_chkfngrps_base, chkfngrpsallocsz);
1387c478bd9Sstevel@tonic-gate chkfngrpsallocsz += 64;
1397c478bd9Sstevel@tonic-gate fpras_chkfngrps_base = kmem_alloc(chkfngrpsallocsz,
1407c478bd9Sstevel@tonic-gate KM_SLEEP);
1417c478bd9Sstevel@tonic-gate fpras_chkfngrps = (struct fpras_chkfngrp *)
1427c478bd9Sstevel@tonic-gate P2ROUNDUP((uintptr_t)fpras_chkfngrps_base, 64);
1437c478bd9Sstevel@tonic-gate }
1447c478bd9Sstevel@tonic-gate
1457c478bd9Sstevel@tonic-gate /*
1467c478bd9Sstevel@tonic-gate * Copy our check function into place for each copy operation
1477c478bd9Sstevel@tonic-gate * and each cpu id.
1487c478bd9Sstevel@tonic-gate */
1497c478bd9Sstevel@tonic-gate fcgp = &fpras_chkfngrps[0];
1507c478bd9Sstevel@tonic-gate for (i = 0; i < FPRAS_NCOPYOPS; ++i)
1517c478bd9Sstevel@tonic-gate bcopy((void *)fpras_chkfn_type1, &fcgp->fpras_fn[i],
1527c478bd9Sstevel@tonic-gate sizeof (struct fpras_chkfn));
1537c478bd9Sstevel@tonic-gate for (i = 1; i < NCPU; ++i)
1547c478bd9Sstevel@tonic-gate *(&fpras_chkfngrps[i]) = *fcgp;
1557c478bd9Sstevel@tonic-gate
1567c478bd9Sstevel@tonic-gate /*
1577c478bd9Sstevel@tonic-gate * At definition fpras_frequency is set to -1, and it will
1587c478bd9Sstevel@tonic-gate * still have that value unless changed in /etc/system (not
1597c478bd9Sstevel@tonic-gate * strictly supported, but not preventable). The following
1607c478bd9Sstevel@tonic-gate * both sets the default and sanity checks anything from
1617c478bd9Sstevel@tonic-gate * /etc/system.
1627c478bd9Sstevel@tonic-gate */
1637c478bd9Sstevel@tonic-gate if (fpras_frequency < 0)
1647c478bd9Sstevel@tonic-gate fpras_frequency = FPRAS_DEFAULT_FREQUENCY;
1657c478bd9Sstevel@tonic-gate
1667c478bd9Sstevel@tonic-gate /*
1677c478bd9Sstevel@tonic-gate * Now calculate fpras_interval. When fpras_interval
1687c478bd9Sstevel@tonic-gate * becomes non-negative fpras checks will commence
1697c478bd9Sstevel@tonic-gate * (copies before this point in boot will bypass fpras).
1707c478bd9Sstevel@tonic-gate * Our stores of instructions must be visible; no need
1717c478bd9Sstevel@tonic-gate * to flush as they're never been executed before.
1727c478bd9Sstevel@tonic-gate */
1737c478bd9Sstevel@tonic-gate membar_producer();
1747c478bd9Sstevel@tonic-gate fpras_interval = (fpras_frequency == 0) ?
1757c478bd9Sstevel@tonic-gate 0 : sys_tick_freq / fpras_frequency;
1767c478bd9Sstevel@tonic-gate }
1777c478bd9Sstevel@tonic-gate }
1787c478bd9Sstevel@tonic-gate
1797c478bd9Sstevel@tonic-gate void
mach_hw_copy_limit(void)1807c478bd9Sstevel@tonic-gate mach_hw_copy_limit(void)
1817c478bd9Sstevel@tonic-gate {
1827c478bd9Sstevel@tonic-gate if (!fpu_exists) {
1837c478bd9Sstevel@tonic-gate use_hw_bcopy = 0;
1847c478bd9Sstevel@tonic-gate hw_copy_limit_1 = 0;
1857c478bd9Sstevel@tonic-gate hw_copy_limit_2 = 0;
1867c478bd9Sstevel@tonic-gate hw_copy_limit_4 = 0;
1877c478bd9Sstevel@tonic-gate hw_copy_limit_8 = 0;
1887c478bd9Sstevel@tonic-gate use_hw_bzero = 0;
1897c478bd9Sstevel@tonic-gate }
1907c478bd9Sstevel@tonic-gate }
1917c478bd9Sstevel@tonic-gate
1927c478bd9Sstevel@tonic-gate void
load_tod_module()1937c478bd9Sstevel@tonic-gate load_tod_module()
1947c478bd9Sstevel@tonic-gate {
1957c478bd9Sstevel@tonic-gate /*
1967c478bd9Sstevel@tonic-gate * Load tod driver module for the tod part found on this system.
1977c478bd9Sstevel@tonic-gate * Recompute the cpu frequency/delays based on tod as tod part
1987c478bd9Sstevel@tonic-gate * tends to keep time more accurately.
1997c478bd9Sstevel@tonic-gate */
2007c478bd9Sstevel@tonic-gate if (tod_module_name == NULL || modload("tod", tod_module_name) == -1)
2017c478bd9Sstevel@tonic-gate halt("Can't load tod module");
2027c478bd9Sstevel@tonic-gate }
2037c478bd9Sstevel@tonic-gate
2047c478bd9Sstevel@tonic-gate void
mach_memscrub(void)2057c478bd9Sstevel@tonic-gate mach_memscrub(void)
2067c478bd9Sstevel@tonic-gate {
2077c478bd9Sstevel@tonic-gate /*
2087c478bd9Sstevel@tonic-gate * Startup memory scrubber, if not running fpu emulation code.
2097c478bd9Sstevel@tonic-gate */
2107c478bd9Sstevel@tonic-gate
21125cf1a30Sjl #ifndef _HW_MEMSCRUB_SUPPORT
2127c478bd9Sstevel@tonic-gate if (fpu_exists) {
2137c478bd9Sstevel@tonic-gate if (memscrub_init()) {
2147c478bd9Sstevel@tonic-gate cmn_err(CE_WARN,
2157c478bd9Sstevel@tonic-gate "Memory scrubber failed to initialize");
2167c478bd9Sstevel@tonic-gate }
2177c478bd9Sstevel@tonic-gate }
21825cf1a30Sjl #endif /* _HW_MEMSCRUB_SUPPORT */
21925cf1a30Sjl }
22025cf1a30Sjl
22125cf1a30Sjl /*
2226b2c23f3SDave Plauger * Halt the present CPU until awoken via an interrupt.
22325cf1a30Sjl * This routine should only be invoked if cpu_halt_cpu()
22425cf1a30Sjl * exists and is supported, see mach_cpu_halt_idle()
22525cf1a30Sjl */
2266b2c23f3SDave Plauger void
cpu_halt(void)22725cf1a30Sjl cpu_halt(void)
22825cf1a30Sjl {
2296b2c23f3SDave Plauger cpu_t *cpup = CPU;
2306b2c23f3SDave Plauger processorid_t cpu_sid = cpup->cpu_seqid;
2316b2c23f3SDave Plauger cpupart_t *cp = cpup->cpu_part;
2326b2c23f3SDave Plauger int hset_update = 1;
2336b2c23f3SDave Plauger volatile int *p = &cpup->cpu_disp->disp_nrunnable;
2346b2c23f3SDave Plauger uint_t s;
23525cf1a30Sjl
23625cf1a30Sjl /*
2376b2c23f3SDave Plauger * If this CPU is online then we should notate our halting
23825cf1a30Sjl * by adding ourselves to the partition's halted CPU
2396890d023SEric Saxe * bitset. This allows other CPUs to find/awaken us when
24025cf1a30Sjl * work becomes available.
24125cf1a30Sjl */
2426b2c23f3SDave Plauger if (CPU->cpu_flags & CPU_OFFLINE)
24325cf1a30Sjl hset_update = 0;
24425cf1a30Sjl
24525cf1a30Sjl /*
2466b2c23f3SDave Plauger * Add ourselves to the partition's halted CPUs bitset
24725cf1a30Sjl * and set our HALTED flag, if necessary.
24825cf1a30Sjl *
24925cf1a30Sjl * When a thread becomes runnable, it is placed on the queue
2506890d023SEric Saxe * and then the halted cpu bitset is checked to determine who
25125cf1a30Sjl * (if anyone) should be awoken. We therefore need to first
2526b2c23f3SDave Plauger * add ourselves to the halted bitset, and then check if there
2536b2c23f3SDave Plauger * is any work available. The order is important to prevent a race
2546890d023SEric Saxe * that can lead to work languishing on a run queue somewhere while
2556890d023SEric Saxe * this CPU remains halted.
2566890d023SEric Saxe *
2576890d023SEric Saxe * Either the producing CPU will see we're halted and will awaken us,
2586890d023SEric Saxe * or this CPU will see the work available in disp_anywork()
25925cf1a30Sjl */
26025cf1a30Sjl if (hset_update) {
26125cf1a30Sjl cpup->cpu_disp_flags |= CPU_DISP_HALTED;
26225cf1a30Sjl membar_producer();
2636890d023SEric Saxe bitset_atomic_add(&cp->cp_haltset, cpu_sid);
26425cf1a30Sjl }
26525cf1a30Sjl
26625cf1a30Sjl /*
26725cf1a30Sjl * Check to make sure there's really nothing to do.
26825cf1a30Sjl * Work destined for this CPU may become available after
26925cf1a30Sjl * this check. We'll be notified through the clearing of our
2706890d023SEric Saxe * bit in the halted CPU bitset, and a poke.
27125cf1a30Sjl */
27225cf1a30Sjl if (disp_anywork()) {
27325cf1a30Sjl if (hset_update) {
27425cf1a30Sjl cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
2756890d023SEric Saxe bitset_atomic_del(&cp->cp_haltset, cpu_sid);
27625cf1a30Sjl }
27725cf1a30Sjl return;
27825cf1a30Sjl }
27925cf1a30Sjl
28025cf1a30Sjl /*
2816b2c23f3SDave Plauger * We're on our way to being halted. Wait until something becomes
2826b2c23f3SDave Plauger * runnable locally or we are awaken (i.e. removed from the halt set).
2836b2c23f3SDave Plauger * Note that the call to hv_cpu_yield() can return even if we have
2846b2c23f3SDave Plauger * nothing to do.
28525cf1a30Sjl *
28625cf1a30Sjl * Disable interrupts now, so that we'll awaken immediately
28725cf1a30Sjl * after halting if someone tries to poke us between now and
28825cf1a30Sjl * the time we actually halt.
28925cf1a30Sjl *
29025cf1a30Sjl * We check for the presence of our bit after disabling interrupts.
29125cf1a30Sjl * If it's cleared, we'll return. If the bit is cleared after
29225cf1a30Sjl * we check then the poke will pop us out of the halted state.
2936b2c23f3SDave Plauger * Also, if the offlined CPU has been brought back on-line, then
2946b2c23f3SDave Plauger * we return as well.
29525cf1a30Sjl *
29625cf1a30Sjl * The ordering of the poke and the clearing of the bit by cpu_wakeup
29725cf1a30Sjl * is important.
29825cf1a30Sjl * cpu_wakeup() must clear, then poke.
29925cf1a30Sjl * cpu_halt() must disable interrupts, then check for the bit.
3006b2c23f3SDave Plauger *
30125cf1a30Sjl * The check for anything locally runnable is here for performance
30225cf1a30Sjl * and isn't needed for correctness. disp_nrunnable ought to be
30325cf1a30Sjl * in our cache still, so it's inexpensive to check, and if there
30425cf1a30Sjl * is anything runnable we won't have to wait for the poke.
3056b2c23f3SDave Plauger *
3066b2c23f3SDave Plauger * Any interrupt will awaken the cpu from halt. Looping here
3076b2c23f3SDave Plauger * will filter spurious interrupts that wake us up, but don't
3086b2c23f3SDave Plauger * represent a need for us to head back out to idle(). This
3096b2c23f3SDave Plauger * will enable the idle loop to be more efficient and sleep in
3106b2c23f3SDave Plauger * the processor pipeline for a larger percent of the time,
3116b2c23f3SDave Plauger * which returns useful cycles to the peer hardware strand
3126b2c23f3SDave Plauger * that shares the pipeline.
31325cf1a30Sjl */
3146b2c23f3SDave Plauger s = disable_vec_intr();
3156b2c23f3SDave Plauger while (*p == 0 &&
3166b2c23f3SDave Plauger ((hset_update && bitset_in_set(&cp->cp_haltset, cpu_sid)) ||
3176b2c23f3SDave Plauger (!hset_update && (CPU->cpu_flags & CPU_OFFLINE)))) {
31825cf1a30Sjl
319c210ded4Sesaxe DTRACE_PROBE1(idle__state__transition,
320c210ded4Sesaxe uint_t, IDLE_STATE_HALTED);
3216b2c23f3SDave Plauger (void) cpu_halt_cpu();
322c210ded4Sesaxe DTRACE_PROBE1(idle__state__transition,
323c210ded4Sesaxe uint_t, IDLE_STATE_NORMAL);
3246b2c23f3SDave Plauger
3256b2c23f3SDave Plauger enable_vec_intr(s);
3266b2c23f3SDave Plauger s = disable_vec_intr();
327c210ded4Sesaxe }
328c210ded4Sesaxe
32925cf1a30Sjl /*
33025cf1a30Sjl * We're no longer halted
33125cf1a30Sjl */
3326b2c23f3SDave Plauger enable_vec_intr(s);
33325cf1a30Sjl if (hset_update) {
33425cf1a30Sjl cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
3356890d023SEric Saxe bitset_atomic_del(&cp->cp_haltset, cpu_sid);
33625cf1a30Sjl }
33725cf1a30Sjl }
33825cf1a30Sjl
33925cf1a30Sjl /*
34025cf1a30Sjl * If "cpu" is halted, then wake it up clearing its halted bit in advance.
34125cf1a30Sjl * Otherwise, see if other CPUs in the cpu partition are halted and need to
34225cf1a30Sjl * be woken up so that they can steal the thread we placed on this CPU.
34325cf1a30Sjl * This function is only used on MP systems.
34425cf1a30Sjl * This function should only be invoked if cpu_halt_cpu()
34525cf1a30Sjl * exists and is supported, see mach_cpu_halt_idle()
34625cf1a30Sjl */
34725cf1a30Sjl static void
cpu_wakeup(cpu_t * cpu,int bound)34825cf1a30Sjl cpu_wakeup(cpu_t *cpu, int bound)
34925cf1a30Sjl {
35025cf1a30Sjl uint_t cpu_found;
3516890d023SEric Saxe processorid_t cpu_sid;
35225cf1a30Sjl cpupart_t *cp;
35325cf1a30Sjl
35425cf1a30Sjl cp = cpu->cpu_part;
3556890d023SEric Saxe cpu_sid = cpu->cpu_seqid;
3566890d023SEric Saxe if (bitset_in_set(&cp->cp_haltset, cpu_sid)) {
35725cf1a30Sjl /*
35825cf1a30Sjl * Clear the halted bit for that CPU since it will be
35925cf1a30Sjl * poked in a moment.
36025cf1a30Sjl */
3616890d023SEric Saxe bitset_atomic_del(&cp->cp_haltset, cpu_sid);
36225cf1a30Sjl /*
3636890d023SEric Saxe * We may find the current CPU present in the halted cpu bitset
36425cf1a30Sjl * if we're in the context of an interrupt that occurred
36525cf1a30Sjl * before we had a chance to clear our bit in cpu_halt().
36625cf1a30Sjl * Poking ourself is obviously unnecessary, since if
36725cf1a30Sjl * we're here, we're not halted.
36825cf1a30Sjl */
36925cf1a30Sjl if (cpu != CPU)
37025cf1a30Sjl poke_cpu(cpu->cpu_id);
37125cf1a30Sjl return;
37225cf1a30Sjl } else {
37325cf1a30Sjl /*
37425cf1a30Sjl * This cpu isn't halted, but it's idle or undergoing a
37525cf1a30Sjl * context switch. No need to awaken anyone else.
37625cf1a30Sjl */
37725cf1a30Sjl if (cpu->cpu_thread == cpu->cpu_idle_thread ||
37825cf1a30Sjl cpu->cpu_disp_flags & CPU_DISP_DONTSTEAL)
37925cf1a30Sjl return;
38025cf1a30Sjl }
38125cf1a30Sjl
38225cf1a30Sjl /*
3836890d023SEric Saxe * No need to wake up other CPUs if this is for a bound thread.
38425cf1a30Sjl */
38525cf1a30Sjl if (bound)
38625cf1a30Sjl return;
38725cf1a30Sjl
38825cf1a30Sjl /*
3896890d023SEric Saxe * The CPU specified for wakeup isn't currently halted, so check
3906890d023SEric Saxe * to see if there are any other halted CPUs in the partition,
3916890d023SEric Saxe * and if there are then awaken one.
3926890d023SEric Saxe *
3936890d023SEric Saxe * If possible, try to select a CPU close to the target, since this
3946890d023SEric Saxe * will likely trigger a migration.
39525cf1a30Sjl */
39625cf1a30Sjl do {
3976890d023SEric Saxe cpu_found = bitset_find(&cp->cp_haltset);
3986890d023SEric Saxe if (cpu_found == (uint_t)-1)
39925cf1a30Sjl return;
4006890d023SEric Saxe } while (bitset_atomic_test_and_del(&cp->cp_haltset, cpu_found) < 0);
40125cf1a30Sjl
4026890d023SEric Saxe if (cpu_found != CPU->cpu_seqid)
4036890d023SEric Saxe poke_cpu(cpu_seq[cpu_found]->cpu_id);
4047c478bd9Sstevel@tonic-gate }
4057c478bd9Sstevel@tonic-gate
4067c478bd9Sstevel@tonic-gate void
mach_cpu_halt_idle(void)4070e751525SEric Saxe mach_cpu_halt_idle(void)
4087c478bd9Sstevel@tonic-gate {
40925cf1a30Sjl if (enable_halt_idle_cpus) {
41025cf1a30Sjl if (&cpu_halt_cpu) {
41125cf1a30Sjl idle_cpu = cpu_halt;
41225cf1a30Sjl disp_enq_thread = cpu_wakeup;
41325cf1a30Sjl }
41425cf1a30Sjl }
4157c478bd9Sstevel@tonic-gate }
4167c478bd9Sstevel@tonic-gate
4177c478bd9Sstevel@tonic-gate /*ARGSUSED*/
418982b9107Sjb int
cpu_intrq_setup(struct cpu * cp)4197c478bd9Sstevel@tonic-gate cpu_intrq_setup(struct cpu *cp)
4207c478bd9Sstevel@tonic-gate {
4217c478bd9Sstevel@tonic-gate /* Interrupt mondo queues not applicable to sun4u */
422982b9107Sjb return (0);
4237c478bd9Sstevel@tonic-gate }
4247c478bd9Sstevel@tonic-gate
4251ae08745Sheppo /*ARGSUSED*/
4261ae08745Sheppo void
cpu_intrq_cleanup(struct cpu * cp)4271ae08745Sheppo cpu_intrq_cleanup(struct cpu *cp)
4281ae08745Sheppo {
4291ae08745Sheppo /* Interrupt mondo queues not applicable to sun4u */
4301ae08745Sheppo }
4311ae08745Sheppo
4327c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4337c478bd9Sstevel@tonic-gate void
cpu_intrq_register(struct cpu * cp)4347c478bd9Sstevel@tonic-gate cpu_intrq_register(struct cpu *cp)
4357c478bd9Sstevel@tonic-gate {
4367c478bd9Sstevel@tonic-gate /* Interrupt/error queues not applicable to sun4u */
4377c478bd9Sstevel@tonic-gate }
4387c478bd9Sstevel@tonic-gate
4397c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4407c478bd9Sstevel@tonic-gate void
mach_htraptrace_setup(int cpuid)441db6d2ee3Ssvemuri mach_htraptrace_setup(int cpuid)
4427c478bd9Sstevel@tonic-gate {
4437c478bd9Sstevel@tonic-gate /* Setup hypervisor traptrace buffer, not applicable to sun4u */
4447c478bd9Sstevel@tonic-gate }
4457c478bd9Sstevel@tonic-gate
4467c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4477c478bd9Sstevel@tonic-gate void
mach_htraptrace_configure(int cpuid)448db6d2ee3Ssvemuri mach_htraptrace_configure(int cpuid)
4497c478bd9Sstevel@tonic-gate {
450db6d2ee3Ssvemuri /* enable/ disable hypervisor traptracing, not applicable to sun4u */
451db6d2ee3Ssvemuri }
452db6d2ee3Ssvemuri
453db6d2ee3Ssvemuri /*ARGSUSED*/
454db6d2ee3Ssvemuri void
mach_htraptrace_cleanup(int cpuid)455db6d2ee3Ssvemuri mach_htraptrace_cleanup(int cpuid)
456db6d2ee3Ssvemuri {
457db6d2ee3Ssvemuri /* cleanup hypervisor traptrace buffer, not applicable to sun4u */
4587c478bd9Sstevel@tonic-gate }
4597c478bd9Sstevel@tonic-gate
4601ae08745Sheppo void
mach_descrip_startup_init(void)4611ae08745Sheppo mach_descrip_startup_init(void)
4621ae08745Sheppo {
4631ae08745Sheppo /*
4641ae08745Sheppo * Only for sun4v.
4651ae08745Sheppo * Initialize Machine description framework during startup.
4661ae08745Sheppo */
4671ae08745Sheppo }
4681ae08745Sheppo void
mach_descrip_startup_fini(void)4691ae08745Sheppo mach_descrip_startup_fini(void)
4701ae08745Sheppo {
4711ae08745Sheppo /*
4721ae08745Sheppo * Only for sun4v.
4731ae08745Sheppo * Clean up Machine Description framework during startup.
4741ae08745Sheppo */
4751ae08745Sheppo }
4761ae08745Sheppo
4777c478bd9Sstevel@tonic-gate void
mach_descrip_init(void)4787c478bd9Sstevel@tonic-gate mach_descrip_init(void)
4797c478bd9Sstevel@tonic-gate {
4801ae08745Sheppo /*
4811ae08745Sheppo * Only for sun4v.
4821ae08745Sheppo * Initialize Machine description framework.
4831ae08745Sheppo */
4847c478bd9Sstevel@tonic-gate }
4857c478bd9Sstevel@tonic-gate
486c56c1e58Sgirish void
hsvc_setup(void)487c56c1e58Sgirish hsvc_setup(void)
488c56c1e58Sgirish {
489c56c1e58Sgirish /* Setup hypervisor services, not applicable to sun4u */
490c56c1e58Sgirish }
491c56c1e58Sgirish
4921ae08745Sheppo void
load_mach_drivers(void)4931ae08745Sheppo load_mach_drivers(void)
4941ae08745Sheppo {
4951ae08745Sheppo /* Currently no machine class (sun4u) specific drivers to load */
4961ae08745Sheppo }
4971ae08745Sheppo
4987c478bd9Sstevel@tonic-gate /*
4997c478bd9Sstevel@tonic-gate * Find a physically contiguous area of twice the largest ecache size
5007c478bd9Sstevel@tonic-gate * to be used while doing displacement flush of ecaches.
5017c478bd9Sstevel@tonic-gate */
5027c478bd9Sstevel@tonic-gate uint64_t
ecache_flush_address(void)5037c478bd9Sstevel@tonic-gate ecache_flush_address(void)
5047c478bd9Sstevel@tonic-gate {
5057c478bd9Sstevel@tonic-gate struct memlist *pmem;
5067c478bd9Sstevel@tonic-gate uint64_t flush_size;
5077c478bd9Sstevel@tonic-gate uint64_t ret_val;
5087c478bd9Sstevel@tonic-gate
5097c478bd9Sstevel@tonic-gate flush_size = ecache_size * 2;
51056f33205SJonathan Adams for (pmem = phys_install; pmem; pmem = pmem->ml_next) {
51156f33205SJonathan Adams ret_val = P2ROUNDUP(pmem->ml_address, ecache_size);
51256f33205SJonathan Adams if (ret_val + flush_size <= pmem->ml_address + pmem->ml_size)
5137c478bd9Sstevel@tonic-gate return (ret_val);
5147c478bd9Sstevel@tonic-gate }
5157c478bd9Sstevel@tonic-gate return ((uint64_t)-1);
5167c478bd9Sstevel@tonic-gate }
5177c478bd9Sstevel@tonic-gate
5187c478bd9Sstevel@tonic-gate /*
5197c478bd9Sstevel@tonic-gate * Called with the memlist lock held to say that phys_install has
5207c478bd9Sstevel@tonic-gate * changed.
5217c478bd9Sstevel@tonic-gate */
5227c478bd9Sstevel@tonic-gate void
phys_install_has_changed(void)5237c478bd9Sstevel@tonic-gate phys_install_has_changed(void)
5247c478bd9Sstevel@tonic-gate {
5257c478bd9Sstevel@tonic-gate /*
5267c478bd9Sstevel@tonic-gate * Get the new address into a temporary just in case panicking
5277c478bd9Sstevel@tonic-gate * involves use of ecache_flushaddr.
5287c478bd9Sstevel@tonic-gate */
5297c478bd9Sstevel@tonic-gate uint64_t new_addr;
5307c478bd9Sstevel@tonic-gate
5317c478bd9Sstevel@tonic-gate new_addr = ecache_flush_address();
5327c478bd9Sstevel@tonic-gate if (new_addr == (uint64_t)-1) {
5337c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC,
5347c478bd9Sstevel@tonic-gate "ecache_flush_address(): failed, ecache_size=%x",
5357c478bd9Sstevel@tonic-gate ecache_size);
5367c478bd9Sstevel@tonic-gate /*NOTREACHED*/
5377c478bd9Sstevel@tonic-gate }
5387c478bd9Sstevel@tonic-gate ecache_flushaddr = new_addr;
5397c478bd9Sstevel@tonic-gate membar_producer();
5407c478bd9Sstevel@tonic-gate }
541