1*25cf1a30Sjl /* 2*25cf1a30Sjl * CDDL HEADER START 3*25cf1a30Sjl * 4*25cf1a30Sjl * The contents of this file are subject to the terms of the 5*25cf1a30Sjl * Common Development and Distribution License (the "License"). 6*25cf1a30Sjl * You may not use this file except in compliance with the License. 7*25cf1a30Sjl * 8*25cf1a30Sjl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*25cf1a30Sjl * or http://www.opensolaris.org/os/licensing. 10*25cf1a30Sjl * See the License for the specific language governing permissions 11*25cf1a30Sjl * and limitations under the License. 12*25cf1a30Sjl * 13*25cf1a30Sjl * When distributing Covered Code, include this CDDL HEADER in each 14*25cf1a30Sjl * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*25cf1a30Sjl * If applicable, add the following below this CDDL HEADER, with the 16*25cf1a30Sjl * fields enclosed by brackets "[]" replaced with your own identifying 17*25cf1a30Sjl * information: Portions Copyright [yyyy] [name of copyright owner] 18*25cf1a30Sjl * 19*25cf1a30Sjl * CDDL HEADER END 20*25cf1a30Sjl */ 21*25cf1a30Sjl /* 22*25cf1a30Sjl * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23*25cf1a30Sjl * Use is subject to license terms. 24*25cf1a30Sjl */ 25*25cf1a30Sjl 26*25cf1a30Sjl #ifndef _SYS_OPL_HWDESC_H 27*25cf1a30Sjl #define _SYS_OPL_HWDESC_H 28*25cf1a30Sjl 29*25cf1a30Sjl #pragma ident "%Z%%M% %I% %E% SMI" 30*25cf1a30Sjl 31*25cf1a30Sjl #ifdef __cplusplus 32*25cf1a30Sjl extern "C" { 33*25cf1a30Sjl #endif 34*25cf1a30Sjl 35*25cf1a30Sjl /* 36*25cf1a30Sjl * Hardware Descriptor. 37*25cf1a30Sjl */ 38*25cf1a30Sjl 39*25cf1a30Sjl #define HWD_SBS_PER_DOMAIN 32 /* System boards per domain */ 40*25cf1a30Sjl #define HWD_CPUS_PER_CORE 4 /* Strands per physical core */ 41*25cf1a30Sjl #define HWD_CORES_PER_CPU_CHIP 4 /* Cores per processor chip */ 42*25cf1a30Sjl #define HWD_CPU_CHIPS_PER_CMU 4 /* Processor chips per CMU */ 43*25cf1a30Sjl #define HWD_SCS_PER_CMU 4 /* System controllers per CMU */ 44*25cf1a30Sjl #define HWD_DIMMS_PER_CMU 32 /* Memory DIMMs per CMU */ 45*25cf1a30Sjl #define HWD_IOCS_PER_IOU 2 /* Oberon chips per I/O unit */ 46*25cf1a30Sjl #define HWD_PCI_CHANNELS_PER_IOC 2 /* PCI channels per Oberon chip */ 47*25cf1a30Sjl #define HWD_LEAVES_PER_PCI_CHANNEL 2 /* Leaves per PCI channel */ 48*25cf1a30Sjl #define HWD_PCI_CHANNELS_PER_SB 4 /* PCI channels per system board */ 49*25cf1a30Sjl #define HWD_CMU_CHANNEL 4 /* CMU channel number */ 50*25cf1a30Sjl #define HWD_IO_BOATS_PER_IOU 6 /* I/O boats per I/O unit */ 51*25cf1a30Sjl #define HWD_BANKS_PER_CMU 8 /* Memory banks per CMU */ 52*25cf1a30Sjl #define HWD_MAX_MEM_CHUNKS 8 /* Chunks per board */ 53*25cf1a30Sjl 54*25cf1a30Sjl typedef uint32_t hwd_stat_t; /* component status */ 55*25cf1a30Sjl 56*25cf1a30Sjl /* 57*25cf1a30Sjl * Values for hwd_stat_t. 58*25cf1a30Sjl */ 59*25cf1a30Sjl #define HWD_STAT_UNKNOWN 0x0000 /* No status yet */ 60*25cf1a30Sjl #define HWD_STAT_PRESENT 0x0001 /* Present */ 61*25cf1a30Sjl #define HWD_STAT_MISS 0x0002 /* Missing */ 62*25cf1a30Sjl #define HWD_STAT_MISCONFIG 0x0003 /* Misconfigured */ 63*25cf1a30Sjl #define HWD_STAT_PASS 0x0004 /* Ok */ 64*25cf1a30Sjl #define HWD_STAT_FAIL 0x0080 /* Failed by XSCF */ 65*25cf1a30Sjl #define HWD_STAT_FAIL_OBP 0x0081 /* Failed by POST/OBP */ 66*25cf1a30Sjl #define HWD_STAT_FAIL_OS 0x0082 /* Failed by OS */ 67*25cf1a30Sjl 68*25cf1a30Sjl #define HWD_STAT_FAILED 0x0080 69*25cf1a30Sjl 70*25cf1a30Sjl #define HWD_MASK_NOT_USED 0x8000 /* If this bit is set, the component */ 71*25cf1a30Sjl /* is not used (even if it presents) */ 72*25cf1a30Sjl 73*25cf1a30Sjl #define HWD_STATUS_FAILED(stat) ((stat) & HWD_STAT_FAILED) 74*25cf1a30Sjl #define HWD_STATUS_OK(stat) ((stat) == HWD_STAT_PASS) 75*25cf1a30Sjl #define HWD_STATUS_PRESENT(stat) \ 76*25cf1a30Sjl ((stat) & (HWD_STAT_PRESENT | HWD_STAT_PASS)) 77*25cf1a30Sjl #define HWD_STATUS_NONE(stat) \ 78*25cf1a30Sjl (((stat) == HWD_STAT_UNKNOWN) || ((stat) == HWD_STAT_MISS)) 79*25cf1a30Sjl 80*25cf1a30Sjl #define HWD_VERSION_MAJOR 1 81*25cf1a30Sjl #define HWD_VERSION_MINOR 1 82*25cf1a30Sjl 83*25cf1a30Sjl /* 84*25cf1a30Sjl * Hardware Descriptor Header. 85*25cf1a30Sjl * 86*25cf1a30Sjl * Some fields occur repeatedly in different structures: 87*25cf1a30Sjl * 88*25cf1a30Sjl * spare* This field is for future use. 89*25cf1a30Sjl * 90*25cf1a30Sjl * filler* This field is used to show alignment. This could also 91*25cf1a30Sjl * be used in the future for something. 92*25cf1a30Sjl * 93*25cf1a30Sjl * check_sum This contains the check sum of the structure it resides in. 94*25cf1a30Sjl */ 95*25cf1a30Sjl typedef struct { 96*25cf1a30Sjl uint32_t hdr_magic; /* magic code ('HWDE') */ 97*25cf1a30Sjl struct hwdesc_version { 98*25cf1a30Sjl uint16_t major; 99*25cf1a30Sjl uint16_t minor; 100*25cf1a30Sjl } hdr_version; /* structure version */ 101*25cf1a30Sjl 102*25cf1a30Sjl /* 103*25cf1a30Sjl * Domain Identifier. The OPL system can have 104*25cf1a30Sjl * upto 24 domains so domain id can be 0 - 23. 105*25cf1a30Sjl */ 106*25cf1a30Sjl uint8_t hdr_domain_id; 107*25cf1a30Sjl char hdr_filler[3]; 108*25cf1a30Sjl 109*25cf1a30Sjl /* 110*25cf1a30Sjl * offsets from the beginning of the header to: 111*25cf1a30Sjl * - SB status information (hwd_sb_status_t) 112*25cf1a30Sjl * - domain information (hwd_domain_info_t) 113*25cf1a30Sjl * - SB information (hwd_sb_info_t). 114*25cf1a30Sjl */ 115*25cf1a30Sjl uint32_t hdr_sb_status_offset; 116*25cf1a30Sjl uint32_t hdr_domain_info_offset; 117*25cf1a30Sjl uint32_t hdr_sb_info_offset; 118*25cf1a30Sjl 119*25cf1a30Sjl uint32_t hdr_spare[9]; 120*25cf1a30Sjl uint32_t hdr_check_sum; 121*25cf1a30Sjl } hwd_header_t; 122*25cf1a30Sjl 123*25cf1a30Sjl /* 124*25cf1a30Sjl * SB Status 125*25cf1a30Sjl */ 126*25cf1a30Sjl typedef struct { 127*25cf1a30Sjl hwd_stat_t sb_status[HWD_SBS_PER_DOMAIN]; /* status of all LSBs */ 128*25cf1a30Sjl uint32_t sb_spare[15]; 129*25cf1a30Sjl uint32_t sb_check_sum; 130*25cf1a30Sjl } hwd_sb_status_t; 131*25cf1a30Sjl 132*25cf1a30Sjl /* 133*25cf1a30Sjl * SP -> Domain Information. 134*25cf1a30Sjl */ 135*25cf1a30Sjl typedef struct { 136*25cf1a30Sjl uint32_t dinf_reset_factor; /* domain reset reason */ 137*25cf1a30Sjl uint32_t dinf_host_id; /* domain unique id */ 138*25cf1a30Sjl uint64_t dinf_system_frequency; /* Hz */ 139*25cf1a30Sjl uint64_t dinf_stick_frequency; /* Hz */ 140*25cf1a30Sjl uint32_t dinf_scf_command_timeout; /* SCF i/f timeout seconds */ 141*25cf1a30Sjl uint32_t dinf_model_info; /* FF1/2 DC1/2/3 */ 142*25cf1a30Sjl uint8_t dinf_mac_address[6]; /* system MAC address */ 143*25cf1a30Sjl uint8_t dinf_filler1[10]; 144*25cf1a30Sjl uint8_t dinf_dr_status; /* 0: DR capable, !0: no DR */ 145*25cf1a30Sjl uint8_t dinf_filler2[7]; 146*25cf1a30Sjl /* 147*25cf1a30Sjl * Specification of degeneracy operation of POST by XSCF 148*25cf1a30Sjl * 0x00: off 149*25cf1a30Sjl * 0x20: component 150*25cf1a30Sjl * 0x40: board 151*25cf1a30Sjl * 0x80: system 152*25cf1a30Sjl */ 153*25cf1a30Sjl uint8_t dinf_config_policy; 154*25cf1a30Sjl /* 155*25cf1a30Sjl * Specification of diagnosis operation of POST by XSCF 156*25cf1a30Sjl * 0x00: off 157*25cf1a30Sjl * 0x20: min 158*25cf1a30Sjl * 0x40: max 159*25cf1a30Sjl */ 160*25cf1a30Sjl uint8_t dinf_diag_level; 161*25cf1a30Sjl /* 162*25cf1a30Sjl * Specification of boot operation of OBP by XSCF 163*25cf1a30Sjl * 0x00: It follows other settings. 164*25cf1a30Sjl * 0x80: Auto boot is not done. 165*25cf1a30Sjl */ 166*25cf1a30Sjl uint8_t dinf_boot_mode; 167*25cf1a30Sjl uint8_t dinf_spare1[5]; 168*25cf1a30Sjl int64_t dinf_cpu_start_time; /* seconds since the Epoch */ 169*25cf1a30Sjl char dinf_banner_name[64]; /* system banner string */ 170*25cf1a30Sjl char dinf_platform_token[64]; /* platform name */ 171*25cf1a30Sjl uint32_t dinf_floating_board_bitmap; /* bit 0 = SB0 ... */ 172*25cf1a30Sjl uint32_t dinf_spare2[12]; 173*25cf1a30Sjl uint32_t dinf_check_sum; 174*25cf1a30Sjl } hwd_domain_info_t; 175*25cf1a30Sjl 176*25cf1a30Sjl /* 177*25cf1a30Sjl * CPU Strand 178*25cf1a30Sjl */ 179*25cf1a30Sjl typedef struct { 180*25cf1a30Sjl hwd_stat_t cpu_status; 181*25cf1a30Sjl char cpu_component_name[32]; 182*25cf1a30Sjl uint16_t cpu_cpuid; /* 0x0000, 0x0001, ... 0x01ff */ 183*25cf1a30Sjl uint16_t cpu_filler; 184*25cf1a30Sjl uint32_t cpu_spare[6]; 185*25cf1a30Sjl } hwd_cpu_t; 186*25cf1a30Sjl 187*25cf1a30Sjl /* 188*25cf1a30Sjl * CPU Core 189*25cf1a30Sjl */ 190*25cf1a30Sjl typedef struct { 191*25cf1a30Sjl hwd_stat_t core_status; 192*25cf1a30Sjl char core_component_name[32]; 193*25cf1a30Sjl uint32_t core_filler1; 194*25cf1a30Sjl uint64_t core_frequency; /* Hz */ 195*25cf1a30Sjl uint64_t core_config; /* bus config reg */ 196*25cf1a30Sjl uint64_t core_version; /* processor VER */ 197*25cf1a30Sjl uint16_t core_manufacturer; /* VER.manuf */ 198*25cf1a30Sjl uint16_t core_implementation; /* VER.impl */ 199*25cf1a30Sjl uint8_t core_mask; /* VER.mask */ 200*25cf1a30Sjl uint8_t core_filler2[3]; 201*25cf1a30Sjl uint32_t core_l1_icache_size; 202*25cf1a30Sjl uint16_t core_l1_icache_line_size; 203*25cf1a30Sjl uint16_t core_l1_icache_associativity; 204*25cf1a30Sjl uint32_t core_num_itlb_entries; 205*25cf1a30Sjl uint32_t core_l1_dcache_size; 206*25cf1a30Sjl uint16_t core_l1_dcache_line_size; 207*25cf1a30Sjl uint16_t core_l1_dcache_associativity; 208*25cf1a30Sjl uint32_t core_num_dtlb_entries; 209*25cf1a30Sjl uint32_t core_spare1[4]; 210*25cf1a30Sjl uint32_t core_l2_cache_size; 211*25cf1a30Sjl uint16_t core_l2_cache_line_size; 212*25cf1a30Sjl uint16_t core_l2_cache_associativity; 213*25cf1a30Sjl uint32_t core_l2_cache_sharing; /* bit N:coreN */ 214*25cf1a30Sjl uint32_t core_spare2[5]; 215*25cf1a30Sjl hwd_cpu_t core_cpus[HWD_CPUS_PER_CORE]; 216*25cf1a30Sjl uint32_t core_spare3[4]; 217*25cf1a30Sjl } hwd_core_t; 218*25cf1a30Sjl 219*25cf1a30Sjl /* 220*25cf1a30Sjl * CPU Chip 221*25cf1a30Sjl */ 222*25cf1a30Sjl typedef struct { 223*25cf1a30Sjl hwd_stat_t chip_status; 224*25cf1a30Sjl char chip_component_name[32]; /* example: "CPU#x" */ 225*25cf1a30Sjl char chip_fru_name[32]; /* example: "CPU#x" */ 226*25cf1a30Sjl char chip_compatible[32]; /* example: "FJSV,SPARC64-VI" */ 227*25cf1a30Sjl /* 228*25cf1a30Sjl * Jupiter Bus Device ID 229*25cf1a30Sjl * 0x0400, 0x0408, ... , 0x05f8 230*25cf1a30Sjl */ 231*25cf1a30Sjl uint16_t chip_portid; 232*25cf1a30Sjl uint16_t chip_filler; 233*25cf1a30Sjl uint32_t chip_spare1[6]; 234*25cf1a30Sjl hwd_core_t chip_cores[HWD_CORES_PER_CPU_CHIP]; 235*25cf1a30Sjl uint32_t chip_spare2[4]; 236*25cf1a30Sjl } hwd_cpu_chip_t; 237*25cf1a30Sjl 238*25cf1a30Sjl /* 239*25cf1a30Sjl * SC 240*25cf1a30Sjl */ 241*25cf1a30Sjl typedef struct { 242*25cf1a30Sjl hwd_stat_t sc_status; 243*25cf1a30Sjl uint32_t sc_filler; 244*25cf1a30Sjl /* 245*25cf1a30Sjl * Top address of SC registers in this XSB 246*25cf1a30Sjl */ 247*25cf1a30Sjl uint64_t sc_register_address; 248*25cf1a30Sjl } hwd_sc_t; 249*25cf1a30Sjl 250*25cf1a30Sjl /* 251*25cf1a30Sjl * Bank 252*25cf1a30Sjl */ 253*25cf1a30Sjl typedef struct { 254*25cf1a30Sjl hwd_stat_t bank_status; 255*25cf1a30Sjl hwd_stat_t bank_cs_status[2]; /* DIMM pair status */ 256*25cf1a30Sjl uint32_t bank_filler1; 257*25cf1a30Sjl uint64_t bank_register_address; /* address of mem patrol regs */ 258*25cf1a30Sjl uint8_t bank_mac_ocd; /* calibrated MAC OCD value */ 259*25cf1a30Sjl uint8_t bank_filler2[3]; 260*25cf1a30Sjl uint8_t bank_dimm_ocd[4][2]; /* calibrated DIMM OCD value */ 261*25cf1a30Sjl uint32_t bank_tune; /* for POST use */ 262*25cf1a30Sjl uint32_t bank_spare[2]; 263*25cf1a30Sjl } hwd_bank_t; 264*25cf1a30Sjl 265*25cf1a30Sjl /* 266*25cf1a30Sjl * Chunk 267*25cf1a30Sjl */ 268*25cf1a30Sjl typedef struct { 269*25cf1a30Sjl uint64_t chnk_start_address; 270*25cf1a30Sjl uint64_t chnk_size; 271*25cf1a30Sjl } hwd_chunk_t; 272*25cf1a30Sjl 273*25cf1a30Sjl /* 274*25cf1a30Sjl * Dimm 275*25cf1a30Sjl */ 276*25cf1a30Sjl typedef struct { 277*25cf1a30Sjl hwd_stat_t dimm_status; 278*25cf1a30Sjl uint32_t dimm_filler1; 279*25cf1a30Sjl uint64_t dimm_capacity; /* bytes */ 280*25cf1a30Sjl uint64_t dimm_available_capacity; /* bytes */ 281*25cf1a30Sjl uint8_t dimm_rank; /* 1 or 2 */ 282*25cf1a30Sjl uint8_t dimm_filler2[7]; 283*25cf1a30Sjl char dimm_component_name[32]; /* "MEM#xyz" */ 284*25cf1a30Sjl char dimm_fru_name[32]; /* "MEM#xyz" */ 285*25cf1a30Sjl } hwd_dimm_t; 286*25cf1a30Sjl 287*25cf1a30Sjl /* 288*25cf1a30Sjl * CS 289*25cf1a30Sjl */ 290*25cf1a30Sjl typedef struct { 291*25cf1a30Sjl hwd_stat_t cs_status; 292*25cf1a30Sjl uint8_t cs_number_of_dimms; 293*25cf1a30Sjl uint8_t cs_filler[3]; 294*25cf1a30Sjl uint64_t cs_available_capacity; 295*25cf1a30Sjl uint64_t cs_dimm_capacity; 296*25cf1a30Sjl uint8_t cs_dimm_badd[8]; /* Value to initialize MAC by POST */ 297*25cf1a30Sjl uint16_t cs_dimm_add[8]; /* Value to initialize MAC by POST */ 298*25cf1a30Sjl uint8_t cs_pa_mac_table[64]; /* PA <-> MAC address conversion */ 299*25cf1a30Sjl } hwd_cs_t; 300*25cf1a30Sjl 301*25cf1a30Sjl /* 302*25cf1a30Sjl * Memory 303*25cf1a30Sjl */ 304*25cf1a30Sjl typedef struct { 305*25cf1a30Sjl uint64_t mem_start_address; /* Memory start for this LSB */ 306*25cf1a30Sjl uint64_t mem_size; /* Memory size for this LSB */ 307*25cf1a30Sjl hwd_bank_t mem_banks[HWD_BANKS_PER_CMU]; 308*25cf1a30Sjl /* 309*25cf1a30Sjl * Mirroring mode: 310*25cf1a30Sjl * 0x00 or 0x01 311*25cf1a30Sjl * 0x00 : not 'memory mirror mode' 312*25cf1a30Sjl * 0x01 : 'memory mirror mode' 313*25cf1a30Sjl */ 314*25cf1a30Sjl uint8_t mem_mirror_mode; /* mirroring mode */ 315*25cf1a30Sjl /* 316*25cf1a30Sjl * Memory configuration: 317*25cf1a30Sjl * 0x01 : 1 divided mode 318*25cf1a30Sjl * 0x02 : 2 divided mode 319*25cf1a30Sjl * 0x04 : 4 divided mode 320*25cf1a30Sjl * 321*25cf1a30Sjl * It is always set to 0x04 at the XSB mode. 322*25cf1a30Sjl */ 323*25cf1a30Sjl uint8_t mem_division_mode; 324*25cf1a30Sjl uint8_t mem_piece_number; /* 0-3 memory slot group used */ 325*25cf1a30Sjl uint8_t mem_cs_interleave; /* 1:cs interleave, 0:not */ 326*25cf1a30Sjl uint32_t mem_filler[3]; 327*25cf1a30Sjl uint8_t mem_available_bitmap[512]; /* for POST use */ 328*25cf1a30Sjl uint8_t mem_degrade_bitmap[16384]; /* for POST use */ 329*25cf1a30Sjl hwd_chunk_t mem_chunks[HWD_MAX_MEM_CHUNKS]; 330*25cf1a30Sjl hwd_dimm_t mem_dimms[HWD_DIMMS_PER_CMU]; 331*25cf1a30Sjl hwd_cs_t mem_cs[2]; 332*25cf1a30Sjl } hwd_memory_t; 333*25cf1a30Sjl 334*25cf1a30Sjl typedef struct { 335*25cf1a30Sjl hwd_stat_t scf_status; 336*25cf1a30Sjl char scf_component_name[32]; /* "SCFI#z" */ 337*25cf1a30Sjl } hwd_scf_interface_t; 338*25cf1a30Sjl 339*25cf1a30Sjl typedef struct { 340*25cf1a30Sjl hwd_stat_t tty_status; 341*25cf1a30Sjl char tty_component_name[32]; /* "TTY#z" */ 342*25cf1a30Sjl } hwd_tty_t; 343*25cf1a30Sjl 344*25cf1a30Sjl typedef struct { 345*25cf1a30Sjl uint8_t fver_major; /* firmware major version */ 346*25cf1a30Sjl uint8_t fver_minor; /* firmware minor version */ 347*25cf1a30Sjl uint8_t fver_local; /* firmware local version */ 348*25cf1a30Sjl uint8_t fver_filler; 349*25cf1a30Sjl } hwd_fmem_version_t; 350*25cf1a30Sjl 351*25cf1a30Sjl typedef struct { 352*25cf1a30Sjl hwd_stat_t fmem_status; /* status of flash */ 353*25cf1a30Sjl char fmem_component_name[32]; 354*25cf1a30Sjl uint8_t fmem_used; /* non-zero: fmem is used */ 355*25cf1a30Sjl uint8_t fmem_filler[3]; 356*25cf1a30Sjl hwd_fmem_version_t fmem_version; 357*25cf1a30Sjl uint32_t fmem_spare; 358*25cf1a30Sjl } hwd_fmem_t; 359*25cf1a30Sjl 360*25cf1a30Sjl /* 361*25cf1a30Sjl * CMU CH 362*25cf1a30Sjl */ 363*25cf1a30Sjl typedef struct { 364*25cf1a30Sjl hwd_stat_t chan_status; 365*25cf1a30Sjl /* 366*25cf1a30Sjl * CMU_CH port ID 367*25cf1a30Sjl * LSB0 is 0x0008, LSB1 is 0x0018, ... , LSB15 is 0x00f8 368*25cf1a30Sjl */ 369*25cf1a30Sjl uint16_t chan_portid; 370*25cf1a30Sjl uint16_t chan_filler; 371*25cf1a30Sjl char chan_component_name[32]; /* "U2P#z" */ 372*25cf1a30Sjl hwd_scf_interface_t chan_scf_interface; 373*25cf1a30Sjl hwd_tty_t chan_serial; 374*25cf1a30Sjl hwd_fmem_t chan_fmem[2]; 375*25cf1a30Sjl } hwd_cmu_chan_t; 376*25cf1a30Sjl 377*25cf1a30Sjl /* 378*25cf1a30Sjl * CMU 379*25cf1a30Sjl */ 380*25cf1a30Sjl typedef struct { 381*25cf1a30Sjl char cmu_component_name[32]; /* example: "CxS0y" */ 382*25cf1a30Sjl char cmu_fru_name[32]; /* example: "Cabinet#x-CMU#y" */ 383*25cf1a30Sjl 384*25cf1a30Sjl hwd_cpu_chip_t cmu_cpu_chips[HWD_CPU_CHIPS_PER_CMU]; /* CPU */ 385*25cf1a30Sjl hwd_sc_t cmu_scs[HWD_SCS_PER_CMU]; /* SC */ 386*25cf1a30Sjl hwd_memory_t cmu_memory; /* Memory */ 387*25cf1a30Sjl hwd_cmu_chan_t cmu_ch; /* CMU CH */ 388*25cf1a30Sjl uint32_t cmu_spare[32]; 389*25cf1a30Sjl } hwd_cmu_t; 390*25cf1a30Sjl 391*25cf1a30Sjl typedef struct { 392*25cf1a30Sjl hwd_stat_t slot_status; 393*25cf1a30Sjl char slot_name[16]; 394*25cf1a30Sjl } hwd_slot_t; 395*25cf1a30Sjl 396*25cf1a30Sjl /* 397*25cf1a30Sjl * IO Boat 398*25cf1a30Sjl */ 399*25cf1a30Sjl typedef struct { 400*25cf1a30Sjl hwd_stat_t iob_status; 401*25cf1a30Sjl char iob_component_name[32]; 402*25cf1a30Sjl char iob_fru_name[32]; 403*25cf1a30Sjl /* 404*25cf1a30Sjl * IO_Boat type 405*25cf1a30Sjl * 0x01 : PCI-X Slot Type 406*25cf1a30Sjl * 0x02 : PCI Express Slot Type 407*25cf1a30Sjl */ 408*25cf1a30Sjl uint32_t iob_type; /* PCI-X or PCI Express */ 409*25cf1a30Sjl uint64_t iob_io_box_info; /* location of I/O */ 410*25cf1a30Sjl /* 411*25cf1a30Sjl * Information of switch on IO_boat 412*25cf1a30Sjl * use only switch_status[0] when PCI-X type IO_boat 413*25cf1a30Sjl */ 414*25cf1a30Sjl hwd_stat_t iob_switch_status[3]; /* PCIE switch statuses */ 415*25cf1a30Sjl /* 416*25cf1a30Sjl * Information of bridge on IO_boat 417*25cf1a30Sjl * use only when PCI-X type IO_boat 418*25cf1a30Sjl */ 419*25cf1a30Sjl hwd_stat_t iob_bridge_status[3]; /* PCIX bridge statuses */ 420*25cf1a30Sjl hwd_slot_t iob_slot[6]; /* PCI slot names */ 421*25cf1a30Sjl uint32_t iob_spare[8]; 422*25cf1a30Sjl } hwd_io_boat_t; 423*25cf1a30Sjl 424*25cf1a30Sjl /* IOU PCI Express Slot */ 425*25cf1a30Sjl typedef struct { 426*25cf1a30Sjl uint32_t iou_type; /* 0: empty, 1: card, 2: IO boat */ 427*25cf1a30Sjl hwd_slot_t iou_slot; 428*25cf1a30Sjl hwd_io_boat_t iou_io_boat; 429*25cf1a30Sjl } hwd_iou_slot_t; 430*25cf1a30Sjl 431*25cf1a30Sjl typedef struct { 432*25cf1a30Sjl hwd_stat_t ff_onb_switch_status; 433*25cf1a30Sjl uint8_t ff_onb_filler[64]; 434*25cf1a30Sjl hwd_stat_t ff_onb_bridge_status; 435*25cf1a30Sjl hwd_stat_t ff_onb_sas_status; 436*25cf1a30Sjl hwd_stat_t ff_onb_gbe_status; 437*25cf1a30Sjl hwd_iou_slot_t ff_onb_slot; 438*25cf1a30Sjl hwd_slot_t ff_onb_xslot; 439*25cf1a30Sjl } hwd_ff_onboard_t; 440*25cf1a30Sjl 441*25cf1a30Sjl typedef struct { 442*25cf1a30Sjl hwd_stat_t ioua_status; /* IOUA status */ 443*25cf1a30Sjl char ioua_component_name[32]; 444*25cf1a30Sjl char ioua_fru_name[32]; 445*25cf1a30Sjl hwd_stat_t ioua_bridge_status; 446*25cf1a30Sjl hwd_stat_t ioua_sas_status; 447*25cf1a30Sjl hwd_stat_t ioua_gbe_status; 448*25cf1a30Sjl } hwd_ioua_t; 449*25cf1a30Sjl 450*25cf1a30Sjl typedef struct { 451*25cf1a30Sjl uint8_t iou_desc_filler[80]; 452*25cf1a30Sjl hwd_iou_slot_t iou_desc_slot; 453*25cf1a30Sjl } hwd_iou_slot_desc_t; 454*25cf1a30Sjl 455*25cf1a30Sjl typedef struct { 456*25cf1a30Sjl hwd_stat_t leaf_status; 457*25cf1a30Sjl uint16_t leaf_port_id; /* portid (logical leaf id) */ 458*25cf1a30Sjl uint8_t leaf_filler[6]; 459*25cf1a30Sjl uint32_t leaf_slot_type; /* card or boat */ 460*25cf1a30Sjl union { 461*25cf1a30Sjl hwd_ff_onboard_t leaf_ff_onboard; 462*25cf1a30Sjl hwd_ioua_t leaf_ioua; 463*25cf1a30Sjl hwd_iou_slot_desc_t leaf_iou_slot; 464*25cf1a30Sjl uint8_t leaf_spare[448]; 465*25cf1a30Sjl } leaf_u; 466*25cf1a30Sjl uint64_t leaf_cfgio_offset; /* config space offset */ 467*25cf1a30Sjl uint64_t leaf_cfgio_size; /* config space size */ 468*25cf1a30Sjl uint64_t leaf_mem32_offset; /* offset of mem32 area */ 469*25cf1a30Sjl uint64_t leaf_mem32_size; /* size of mem32 area */ 470*25cf1a30Sjl uint64_t leaf_mem64_offset; /* offset of mem64 area */ 471*25cf1a30Sjl uint64_t leaf_mem64_size; /* size of mem64 area */ 472*25cf1a30Sjl } hwd_leaf_t; 473*25cf1a30Sjl 474*25cf1a30Sjl /* 475*25cf1a30Sjl * PCI CH 476*25cf1a30Sjl */ 477*25cf1a30Sjl typedef struct { 478*25cf1a30Sjl hwd_stat_t pci_status; /* PCI CH status */ 479*25cf1a30Sjl char pci_component_name[32]; 480*25cf1a30Sjl char pci_fru_name[32]; 481*25cf1a30Sjl uint8_t pci_filler[12]; 482*25cf1a30Sjl hwd_leaf_t pci_leaf[HWD_LEAVES_PER_PCI_CHANNEL]; 483*25cf1a30Sjl } hwd_pci_ch_t; 484*25cf1a30Sjl 485*25cf1a30Sjl /* 486*25cf1a30Sjl * System Board 487*25cf1a30Sjl */ 488*25cf1a30Sjl typedef struct { 489*25cf1a30Sjl /* 490*25cf1a30Sjl * SB 491*25cf1a30Sjl */ 492*25cf1a30Sjl hwd_stat_t sb_status; 493*25cf1a30Sjl uint8_t sb_mode; /* 0:PSB 1:XSB */ 494*25cf1a30Sjl uint8_t sb_psb_number; /* PSB number for this LSB */ 495*25cf1a30Sjl uint8_t sb_filler1[10]; 496*25cf1a30Sjl 497*25cf1a30Sjl hwd_cmu_t sb_cmu; /* CMU */ 498*25cf1a30Sjl 499*25cf1a30Sjl hwd_pci_ch_t sb_pci_ch[HWD_PCI_CHANNELS_PER_SB]; /* PCI CH */ 500*25cf1a30Sjl 501*25cf1a30Sjl uint32_t sb_spare[31]; 502*25cf1a30Sjl uint32_t sb_check_sum; 503*25cf1a30Sjl } hwd_sb_t; 504*25cf1a30Sjl 505*25cf1a30Sjl #define HWD_DATA_SIZE (36 * 1024) /* Size of HWD data from SCF */ 506*25cf1a30Sjl 507*25cf1a30Sjl #ifdef __cplusplus 508*25cf1a30Sjl } 509*25cf1a30Sjl #endif 510*25cf1a30Sjl 511*25cf1a30Sjl #endif /* _SYS_OPL_HWDESC_H */ 512